FUJITSU MB1503

Sept. 1995
Edition 1.0a
DATA SHEET
MB1503
LOW-POWER PLL FREQUENCY SYNTHESIZER WITH
POWER SAVE FUNCTION (1.1GHz)
The Fujitsu MB1503 is a serial input phase-locked loop (PLL) frequency synthesizer with a
pulse-swallow function. A stand-by mode is provided to limit power consumption during
intermittent operation.
The MB1503 is configured of a 1.1GHz dual-modulus prescaler with 128/129 divide ratio,
control signal generator, 16-bit shift register, 15-bit latch, programmable reference divider
(binary 14-bit programmable reference counter), 1-bit switch counter, phase comparator
with phase conversion function, charge pump, crystal oscillator, 19-bit shift register, 18-bit
latch, programmable divider (binary 7-bit swallow counter and binary 11-bit programmable
counter), analog switches, and an intermittent operation control circuit that selects the
operating or stand-by mode depending on the power-save control input state (PS).
The MB1503 operates from a single +5 V supply. Fujitsu’s advanced technology achieves
an Icc of 8mA, typical. The stand-by mode current consumption is just 100µA.
Features
•
•
•
•
•
–
–
•
–
–
•
•
•
•
High operating frequency
Pulse-swallow function
: fIN = 1.1GHz (PIN = –10dBm)
: High-speed dual-modulus prescaler with 128/129
divide ratio
Low supply current
: ICC = 8mA typ. at 5V
Power-saving stand-by mode : 100µA
Serial input, 18-bit programmable divider consisting of:
Binary 7-bit swallow counter
: 0 to 127
Binary 11-bit programmable counter : 16 to 2,047
Serial input 15-bit programmable reference divider consisting of:
Binary 15-bit programmable reference counter: 8 to 16,383
1-bit switch counter sets prescaler divide ratio
On-chip analog switch for fast lock-up
On-chip charge pump
Wide operating temperature range: –40 to +85°C
Plastic 16–pin dual inline package (Suffix : –P)
Plastic 16–pin small outline package (Suffix : –PF)
PLASTIC PACKAGE
(FPT-16P-M06)
ABSOLUTE MAXIMUM RATINGS (See NOTE)
Ratings
Symbol
Value
Unit
VCC
–0.5 to +7.0
V
VP
VCC ≤ VP ≤ 10.0
V
Output Voltage
VOUT
–0.5 to VCC +0.5
V
Output Current
IOUT
±10
mA
Storage Temperature
Tstg
–55 to +125
°C
Supply Voltage
NOTE: Permanent device damage may occur if the above Absolute Maximum
Ratings are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure
to absolute maximum rating conditions for extended periods may affect device
reliability.
PLASTIC PACKAGE
(DIP-16P-M04)
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
fields. However, it is advised that normal precautions be
taken to avoid application of any voltage higher than
maximum rated voltages to this high impedance circuit.
Copyright  1994 by FUJITSULIMITED
1
MB1503
PIN ASSIGNMENT
(TOP VIEW)
2
OSCIN
1
16
PS
OSCOUT
2
15
fR
VP
3
14
fP
VCC
4
13
BiSW
DO
5
12
FC
GND
6
11
LE
LD
7
10
Data
fIN
8
9
Clock
MB1503
BLOCK DIAGRAM
OSCIN
1
16-bit Shift Register
Oscillator
VCC
4
fR
14
fP
15-bit Latch
15-bit Latch
3
15
Phase
Comparator
PS1
OSCOUT 2
VP
PS
To Lock Detector
16-bit Shift Register
PS1
16
Phase
Characteristics
Changing
Circuit
Programmable
Reference Divider
Binary 14-bit
Reference
Counter
S
W
PS1
From
Phase
Comparator
Charge
Pump
13
BiSW
12
FC
PS1
Intermittent
Operation
Control Circuit
From Charge
Pump
DO
5
GND
6
LD
7
Schmitt
Trigger
From
Phase
Comparator
Lock
Detection
Circuit
19-bit Shift Register
19-bit Shift Register
18-bit Latch
7-bit Latch
11-bit Latch
1-bit
Control
Latch
11
LE
Schmitt
Trigger
10
Data
Schmitt
Trigger
9
Clock
PS1
Programmable Divider
SW
fIN
8
Prescaler
Output
Prescaler
PS1
Binary 7-bit Binary 11-bit
Programmable
Swallow
Counter
Counter
MC
Control Circuit
3
MB1503
PIN DESCRIPTION
Pin No. Pin Name
4
I/O
Description
1
OSCIN
I
Programmable reference divider input
Oscillator input
An external crystal is connected to this pin.
2
OSCOUT
O
Oscillator output
An external crystal is connected to this pin.
3
VP
–
Power supply input for charge pump and analog switch
4
VCC
–
Power supply
5
DO
O
Charge pump output
The phase of the charge pump is reversed depending on the FC input.
6
GND
–
Ground
7
LD
O
Phase comparator output
The output level is high when LD is locked. The output level is low when LD is unlocked.
8
fIN
I
Prescaler input
Connection with an external VCO should be done by AC coupling.
9
Clock
I
Clock input for 19-bit and 16-bit shift registers
Data is shifted into the shift register on the rising edge of the clock.The Schmitt trigger is
contained.
10
Data
I
Serial data input using binary code
The last bit of the data is a control bit.
When the control bit is high, data is transmitted to the 15-bit latch.
When it is low, data is transmitted to the 18-bit latch.The Schmitt trigger input is involved.
11
LE
I
Load enable signal input
When LE is high, the data of the shift register are transferred to a latch, depending on the
control bit in the serial data. At the same time, an internal analog switch turns on and the output
of the internal charge pump is connected to the BiSW pin.The Schmitt trigger input is involved.
12
FC
I
Phase select input of phase comparator (with internal pull-up resistor)
When FC is low, the characteristics of the charge pump and phase comparator are reversed.
The FC input signal is also used to control the fOUT pin (test pin) of fR or fP.
13
BiSW
O
Analog switch output
BiSW is usually in the high-impedance state. When the switch is turned on (LE is high), the
state of the internal charge pump is output.
14
fP
O
Monitor pin of programmable counter output
15
16
fR
PS
O
I
Monitor pin of reference counter output
Power save signal input
Set PS low while the system is powered (never use pin 16 as it is opened)
PS = High : Operation mode
PS = Low : Stand-by mode
MB1503
FUNCTIONAL DESCRIPTIONS
Pulse swallow function
The divide ratio can be calculated using the following equation:
fVCO = [(M x N) + A] x fOSC ÷ R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N
: Preset divide ratio of binary 11-bit programmable counter (16 to 2,047)
A
: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
fOSC : Output frequency of the reference frequency oscillator
R
: Preset divide ratio of binary 14-bit programmable reference counter (8 to 16,383)
M
: Preset divide ratio of modules prescaler (128)
Serial data input
Serial data is input using the Data, Clock, and LE pins. Serial data controls the 15-bit programmable reference divider and 18-bit
programmable divider separately.
Binary serial data is input to the Data pin.
One bit of data is shifted into the internal shift registers on the rising edge of the clock. When the load enable pin is high or open, stored
data is latched depending on the control data as follows:
Control data
(a)
Destination of serial data
H
15-bit latch
L
18-bit latch
Programmable reference divider ratio
The programmable reference divider consists of a 15-bit latch and a 14-bit reference counter. The serial 16-bit data format is
shown below:
Direction of data shift
Control bit
LSB
C
S
1
S
2
S
3
S
4
Divide ratio setting bit for prescaler
MSB
S
5
S
6
S
7
S
8
S
9
S
10
S
11
S
12
S
13
S
14
SW
Divide ratio setting bit for programmable reference counter
5
MB1503
•
14-bit programmable reference counter divide ratio
Divide ratio
R
S
14
S
13
S
12
S
11
S
10
S
9
S
8
S
7
S
6
S
5
S
4
S
3
S
2
S
1
8
0
0
0
0
0
0
0
0
0
0
1
0
0
0
9
0
0
0
0
0
0
0
0
0
0
1
0
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(Divide ratio = 8 to 16,383)
Notes: 1. Divide ratios less than 8 are prohibited
2. SW: This bit selects the divide ratio of the prescaler
SW Low: 128 or 129 (SW must be always be low)
3. S1 to S14: These bits select the divide ratio of the programmable reference counter (8 to 16,383)
4. C: Control bit: Set high
5. Input MSB data first
(b)
Programmable divider divide ratio
The programmable divider consists of a 19-bit shift register, 18-bit latch, 7-bit swallow counter, and 11-bit programmable
counter. The serial 19-bit data format is shown below:
Direction of data shift
Control bit
LSB
C
S
1
S
2
S
3
S
4
MSB
S
5
S
6
Divide ratio setting bit for
swallow counter
6
S
7
S
8
S
9
S
10
S
11
S
12
S
13
S
14
S
15
S
16
S
17
Divide ratio setting bit for programmable counter
S
18
MB1503
•
•
7-bit swallow counter divide ratio
11-bit programmable counter divide ratio
Divide
ratio
A
S
7
S
6
S
5
S
4
S
3
S
2
S
1
Divide
ratio
N
S
18
S
17
S
16
S
15
S
14
S
13
S
12
S
11
S
10
S
9
S
8
0
0
0
0
0
0
0
0
16
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
17
0
0
0
0
0
0
1
0
0
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
127
1
1
1
1
1
1
1
2047
1
1
1
1
1
1
1
1
1
1
1
(Divide ratio = 0 to 127)
Notes: 1.
2.
3.
4.
5.
(Divide ratio = 16 to 2,047)
Divide ratios less than 16 are prohibited for the 11–bit programmable counter
S1 to S7: These bits select the divide ratio of the swallow counter (0 to 127)
S8 to S18: These bits select the divide ratio of the programmable counter (16 to 2,047)
C: Control bit: (Set low)
Input MSB data first
Serial data input timing
•
t1 (≥ 1µs) : Data setup time
t2 (≥ 1µs) : Data hold time
t4 (≥ 1µs) : LE setup time to the rising edge of last clock
Data
t3 (≥ 1µs) : Clock pulse width
t5 (≥ 1µs) : LE pulse width
S18 =
MSB
S17
S10
S9
S1 =
LSB
C: Control bit
(SW) (∗1)
(S14)
(S8)
(S7)
(S1)
(C: Control bit)
Clock
LE
t1
t2
t3
t4
t5
∗1 : Bits enclosed in parentheses are used when the divide ratio of the programmable reference divider is selected.
Note:
One bit of data is shifted into the shift register on the rising edge of the clock.
7
MB1503
Intermittent operation
Intermittent operation limits power consumption by shutting down or starting the internal circuits according to their necessity. If device
operation resumes uncontrolled, the error signal output from the phase comparator may exceed the limit due to an undefined phase
relationship between the reference frequency (fR) and the comparison frequency (fP) and frequency lock is lost.
To prevent this, an intermittent operation control circuit is provided to decrease the variation in the locking frequency by forcibly
correcting the phase of both frequencies to limit the error signal output. This is done by the PS control circuit. If PS is set high, the
circuit enters the operating mode. If PS is set low, operation stops and the device enters the stand-by mode. Each mode is explained
below:
•
Operating mode (PS =High Level)
All circuits are operating, and PLL operation is normal.
•
Stand-by mode (PS = Low level)
Circuits that do not affect operation are powered down to limit current consumption.
The current in the power save state is typically 100µA.
At this time, the levels of DO and LD are the same as when the PLL is locked.
Since DO is placed in the high-impedance state and the input voltage of the voltage controlled oscillator (VCO) is set to the voltage
in the operating mode (when locked) by the time constant of the low-pass filter, the frequency output from the VCO (fVCO) is kept at
the locking frequency.
The operating and stand-by modes alternate repeatedly. This intermittent operation limits the error signal by forcibly correcting the
phase of the reference and comparison frequencies to limit power consumption.
The device must be set in the stand-by mode (PS = low) when it is powered up.
Relationship between the FC input and phase characteristics
The FC pin changes the phase characteristics of the phase comparator. The internal charge pump output level (DO) is reversed,
depending on the FC pin input level. The relationship between the FC input level and DO is shown below:
FC = High or open
FC = Low
fR > fP
H
L
fR < fP
L
H
fR = fP
Z (∗1)
Z (∗1)
∗1: High impedance
When designing a synthesizer, the FC pin setting depends on the VCO characteristics.
1
∗: When the VCO characteristics are similar to
1 , set FC high or open.
∗: When the VCO characteristics are similar to
2 , set FC low.
VCO
output
frequency
2
VCO input voltage
8
MB1503
Phase comparator output waveform (FC = High)
fR
fP
LD
H
DO
Z
L
fR > fP
fR = fP
fR < fP
fR < fP
fR < fP
Notes: 1. Phase difference detection range: –2π to +2π
2. Spike appearance depends on the charge pump characteristics. Also, the spike is output to diminish
dead band.
3. When fR > fP or fR < fP, a spike might not appear depending on the charge pump characteristics.
4. LD is low when the phase difference is tw or more. LD is high when the phase difference is tw or less for
three or more cycles (when fOSCIN = 12.8MHz, tw = 625 to 1,250ns).
Analog switch
The LE signal turns the analog switch on or off. When the analog switch is turned on, the charge pump output (DO) is output through
the BiSW pin. When it is turned off, the BiSW pin is in the high-impedance state.
When LE = high (when the divide ratio of the internal divider is changed): Analog switch = on
When LE = low (normal operating mode): Analog switch = off
The LPF time constant can be decreased by inserting an analog switch between LPF1 and LPF2. This decreases the lock-up time
when the PLL channel is changed.
DO
CHP
LPF–1
LPF–2
VCO
BiSW
Analog
switch
(Control signal LE)
9
MB1503
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VCC
Min
Value
Typ
Max
4.5
5.0
5.5
Supply Voltage
VCC ≤ VP ≤ 8.0
VP
Unit
V
V
Input Voltage
VI
GND
–
VCC
V
Operating Temperature
TA
–40
–
+85
°C
HANDLING PRECAUTIONS
• This device should be transported and stored in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats.
• Always turn the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.
10
MB1503
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Supply Current
ICC
Min
Value
Typ
Max
–
8.0
12.0
Unit
Condition
mA
With fIN = 1.1GHz, OSCIN =
12MHz, VCC = 5.0V. Inputs
are VCC and outputs are
open.
IPS
–
100
–
µA
With fIN = 1.1GHz, OSCIN =
12MHz, VCC = 5.0V. The
PS pin is grounded, remaining inputs are at VCC, and
outputs are open.
fIN
fIN
10
–
1100
MHz
AC coupling. The minimum
operating frequency is
measured with a 100pF capacitor connected.
OSCIN
fOSC
–
12
20
MHz
—
fIN
Pf IN
–10
–
6
dBm
—
OSCIN
VOSC
0.5
–
–
Vp–p
—
VIH
VCC x 0.7
–
–
V
—
VIL
–
–
VCC x 0.3
V
—
IIH
–
1.0
–
µA
—
IIL
–
–1.0
–
µA
—
FC
IFC
–
–60
–
µA
—
OSCIN
IOSC
–
±50
–
µA
—
VOH
4.4
–
–
V
VCC = 5V
VOL
–
–
0.4
V
—
IOFF
–
–
1.1
µA
VDO = GND to 8V
VCC ≤ VP ≤ 8V
IOH
–1.0
–
–
mA
—
IOL
1.0
–
–
mA
—
RON
–
25
–
Ω
—
Stand-by Current
Operating Frequency
Input Sensitivity
High-level Input Voltage
Low-level Input Voltage
High-level Input Current
Except fIN and
OSCIN
Data, Clock,
LE
Low-level Input Current
Input Current
High-level Output
Voltage
Low-level Output Voltage
Except DO and
OSCOUT
High-impedance
Cut off Current
DO
Output Current
Except DO and
OSCOUT
Analog Switch ON Resistance
11
MB1503
TEST CIRCUIT
(FOR MEASURING PRESCALER INPUT SENSITIVITY)
VCC = 5V
X’ tal
0.1µ
VP = 6V
1000p
P·G
50Ω
8
7
6
5
4
3
2
1
VCC = 5V
9 10 11 12 13 14 15 16
Oscilloscope
12
MB1503
APPLICATION EXAMPLE
Output
LPF
VCO
From
controller
PS
16
fR
fP
15
14
BiSW FC
13
12
LE
Data
Clock
11
10
9
6
7
8
47K
47K
MB1513
1
2
3
4
OSCOUT VP
OSCIN
6V
X’ tal
C1
5
VCC
5V
DO
GND LD
fIN
1000p
C2
0.1µ
VP, VPX :
C1, C2 :
Maximum 8V
Depends on the crystal parameters
13
MB1503
PACKAGE DIMENSIONS
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M06)
.089(2.25)MAX
(MOUNTING HEIGHT)
.400 +.010 (10.15+0.25 )
–.008
–0.20
.002(0.05)MIN
(STAND OFF HEIGHT)
.307±.016
(7.80±0.40)
INDEX
“B”
.209±.012
(5.30±0.30)
.268 +.016 (6.80 +0.40 )
–.008
–0.20
.020±.008
(0.50±0.20)
.050(1.27)
TYP
.018±.004
(0.45±0.10)
“A”
Ø.005(0.13)
.006 +.002 (0.15 +0.05 )
–.001
–0.02
M
Details of “A” part
.016(0.40)
.004(0.10)
.350(8.89) REF
1991 FUJITSU LIMITED F16015S-2C
14
.008(0.20)
.007(0.18)
MAX
.027(0.68)
MAX
Details of “B” part
.006(0.15)
.008(0.20)
.007(0.18)
MAX
.027(0.68)
MAX
Dimensions in
inches (millimeters)
MB1503
16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-16P-M04)
15°MAX
.770 +.008 (19.55 +0.20 )
–.012
–0.30
INDEX-1
.244±.010
(6.20±0.25)
.300(7.62)
TYP
INDEX-2
.039 +.012
–0
(0.99 +0.30 )
–0
.060 +.012
–0
(1.52 +0.30 )
–0
.010±.002
(0.25±0.05)
.172(4.36)MAX
.118(3.00)MIN
.100(2.54)
TYP
.050(1.27)
MAX
1991 FUJITSU LIMITED D16033S-2C
.020(0.51)MIN
.018±.003
(0.46±0.08)
Dimensions in
inches (millimeters)
15