Military Plastic pASIC 3 Family 60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density Military pASIC 3 - 3.3V Family DEVICE HIGHLIGHTS FEATURES Device Highlights Features High Performance and High Density Total of 180 I/O pins ■ 60,000 Usable PLD Gates with 316 I/Os ■ 16-bit counter speeds over 300 MHZ, data path speeds over 400 MHz ■ 0.35um four-layer metal non-volatile CMOS process for smallest die sizes Easy to Use/Fast Development Cycles ■ 100% routable with 100% utilization and complete pin-out stability ■ Variable-grain logic cells provide high performance and 100% utilization ■ Comprehensive design tools include high quality Verilog/VHDL synthesis ■ 308 bidirectional input/output pins, PCI-compliant for 5.0 volt and 3.3 volt buses for -1/-2 speed grades ■ 8 high-drive input/distributed network pins Eight Low-Skew Distributed Networks ■ Two array clock/control networks available to the logic cell flip-flop clock, set and reset inputs - each driven by an input-only pin ■ Up to six global clock/control networks available to the logic cell F1, clock, set and reset inputs and the input and I/O register clock, reset and enable inputs as well as the output enable control - each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback Advanced I/O Capabilities High Performance ■ Interfaces with both 3.3 volt and 5.0 volt devices ■ PCI compliant with 3.3V and 5.0V buses for -1/-2 speed grades ■ Input + logic cell + output total delays under 6 ns ■ Data path speeds exceeding 400 MHz ■ Full JTAG boundary scan ■ ■ Registered I/O cells with individually controlled clocks and output enables Device QL3012 QL3025 QL3040 QL3060 Counter speeds over 300 MHz ASIC Gates PLD Gates Package Max I/O Qualification Level Supply Voltage 8,000 16,000 24,000 36,000 12,000 25,000 40,000 60,000 84PLCC 208PQFP 208PQFP 208PQFP 68 174 174 174 M M M M 3.3V 3.3V 3.3V 3.3V M = Military Temperature (-55 to +125 degrees C) TABLE 1: Selector Table Rev B 8-23 Military Plastic pASIC 3 Family PRODUCT SUMMARY Product Summary The pASIC 3 FPGA family features up to 60,000 usable PLD gates. pASIC 3 FPGAs are fabricated on a 0.35mm four-layer metal process using QuickLogic’s patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. The pASIC 3 product family contains 1,584 logic cells. With a maximum of 316 I/Os, and is available in 208-PQFP and 84-PLCC packages. Software support for the complete pASIC 3 family is available through three basic packages. The turnkey QuickWorks® package provides the most complete FPGA software solution from design entry to logic synthesis, to place and route, to simulation. The QuickWorksTM-Lite and QuickToolsTM packages provide a solution for designers who use Cadence, Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Veribest, or other third-party tools for design entry, synthesis, or simulation. PINOUT DIAGRAM 84-PIN PLCC Pinout Diagram 68-Pin CPGA TABLE 2: 84-pin PLCC 8-24 24 Preliminary Military Plastic pASIC 3 Family PINOUT DIAGRAM 208-PIN PQFP Pinout Diagram 208-Pin PQFP Pin #157 Pin #1 pASIC QL3060-1PQ208M Pin #53 Pin #105 8-25 Military Plastic pASIC 3 Family PQFP 208-PINOUT TABLE PQFP 208 Pinout Table 208 PQFP 208 1 2 3 4 5 NC 6 7 8 9 10 11 12 13 14 NC 15 16 17 18 19 20 NC 21 22 23 24 25 26 27 28 29 30 31 32 NC 33 NC 34 35 36 NC 37 38 39 NC 40 41 42 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O GCLK / I ACLK / I VCC GCLK / I GCLK / I VCC I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O 208 PQFP 43 44 45 46 47 48 NC 49 50 51 52 53 54 NC NC 55 56 NC 57 58 59 60 61 62 63 64 NC 65 66 67 NC 68 69 70 NC 71 NC 72 73 74 NC 75 76 77 78 79 80 81 82 83 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O GND I/O I/O I/O I/O VCCIO 208 PQFP 84 85 86 87 88 89 90 91 92 NC 93 94 95 96 97 98 99 100 NC 101 NC 102 NC NC 103 104 105 NC 106 107 108 109 NC 110 111 112 113 114 115 116 117 NC 118 119 120 121 NC 122 123 124 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O TRSTB TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 208 Function PQFP 125 I/O 126 I/O 127 GND 128 I/O NC I/O 129 GCLK / I 130 ACLK / I 131 VCC 132 GCLK / I 133 GCLK / I 134 VCC 135 I/O 136 I/O NC I/O 137 I/O NC GND 138 I/O 139 I/O 140 I/O 141 I/O 142 I/O NC I/O 143 I/O 144 I/O 145 VCC NC I/O 146 I/O 147 GND 148 I/O 149 I/O 150 I/O 151 I/O 152 I/O 153 I/O 154 I/O 155 I/O 156 I/O 157 TCK 158 STM NC I/O 159 I/O 160 I/O 161 I/O 162 I/O 163 GND 164 I/O 165 VCC 166 I/O NC I/O 167 I/O 8-26 26 Preliminary 208 PQFP 168 169 NC 170 171 172 173 174 175 NC 176 177 178 179 NC 180 181 182 NC 183 184 185 186 187 188 NC 189 190 191 192 193 194 NC 195 196 197 198 NC 199 200 201 202 203 204 205 206 207 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TDO Military Plastic pASIC 3 Family ABSOLUTE MAXIMUM RATINGS DC Input Current ...................... ±20 mA ESD Pad Protection ....................±2000V Storage Temperature .......-65°C to +150°C Lead Temperature ...........................300°C VCC Voltage ...........................-0.5 to 4.6V VCCIO Voltage .......................-0.5 to 7.0V Input Voltage.............. -0.5 to VCCIO+0.5V Latch-up Immunity .................. ±200 mA OPERATING RANGE Symbol VCC VCCIO TA TC K Parameter Min 3.0 3.0 -55 Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Case Temperature -0 Speed Grade -1 Speed Grade -2 Speed Grade Delay Factor 0.42 0.42 0.42 Military Max 3.6 5.5 125 2.03 1.64 1.37 Unit V V °C °C DC CHARACTERISTICS Symbol VIH VIL VOH Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VOL Output LOW Voltage II IOZ CI IOS I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitance [2] Output Short Circuit Current [3] ICC ICCIO D.C. Supply Current [4] D.C. Supply Current on VCCIO Conditions Min Max Unit 0.5VCC VCCIO+0.5 V -0.5 0.3VCC V IOH = -12 mA 2.4 V 0.9VCC V IOH = -500 µA IOL = 8 mA [1] 0.45 V IOL = 1.5 mA 0.1VCC V VI = VCCIO or GND -10 10 µA VI = VCCIO or GND -10 10 µA 10 pF VO = GND -15 -180 mA VO = VCC 40 210 mA VI, VIO = VCCIO or GND 0.50 (typ) 5 mA 0 100 µA Notes: [1] Military devices have 8 mA IOL specifications. [2] Capacitance is sample tested only. Clock pins are 12 pF maximum. [3] Only one output at a time. Duration should not exceed 30 seconds. [4] Maximum ICC is 5 mA for all military grade devices. For AC conditions, contact QuickLogic customer engineering. 8-27 Military Plastic pASIC 3 Family QL3012 QL3012 AC CHARACTERISTICS at VCC = 3.3V, TA = 25°C (K = 1.00) (To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.) Logic Cells Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Propagation Delays (ns) Fanout [5] 2 3 4 1.7 1.9 2.2 1.7 1.7 1.7 0.0 0.0 0.0 1.0 1.2 1.5 1.2 1.2 1.2 1.2 1.2 1.2 1.3 1.5 1.8 1.1 1.3 1.6 1.9 1.9 1.9 1.8 1.8 1.8 Parameter Combinatorial Delay [6] Setup Time [6] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8 8 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8 Input-Only/Clock Cells Symbol tIN tINI tISU tIH tlCLK tlRST tlESU tlEH Parameter High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1 1.5 1.6 3.1 0.0 0.7 0.6 2.3 0.0 Propagation Delays (ns) Fanout [5] 2 3 4 8 12 1.6 1.8 1.9 2.4 2.9 1.7 1.9 2.0 2.5 3.0 3.1 3.1 3.1 3.1 3.1 0.0 0.0 0.0 0.0 0.0 0.8 1.0 1.1 1.6 2.1 0.7 0.9 1.0 1.5 2.0 2.3 2.3 2.3 2.3 2.3 0.0 0.0 0.0 0.0 0.0 24 4.4 4.5 3.1 0.0 3.6 3.5 2.3 0.0 Notes: [5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [6] These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design. 8-28 28 Preliminary Military Plastic pASIC 3 Family QL3012 Clock Cells Symbol tACK tGCKP tGCKB Parameter 1 1.2 0.7 0.8 Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay Propagation Delays (ns) Loads per Half Column [7] 2 3 4 8 10 1.2 1.3 1.3 1.5 1.6 0.7 0.7 0.7 0.7 0.7 0.8 0.9 0.9 1.1 1.2 11 1.7 0.7 1.3 I/O Cells Symbol Parameter tI/O tISU tIH tlOCLK tlORST tlESU tlEH Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time Symbol Parameter tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State [8] Output Delay Low to Tri-State [8] 1 1.3 3.1 0.0 0.7 0.6 2.3 0.0 30 2.1 2.2 1.2 1.6 2.0 1.2 Propagation Delays (ns) Fanout [5] 2 3 4 8 1.6 1.8 2.1 3.1 3.1 3.1 3.1 3.1 0.0 0.0 0.0 0.0 1.0 1.2 1.5 2.5 0.9 1.1 1.4 2.4 2.3 2.3 2.3 2.3 0.0 0.0 0.0 0.0 Propagation Delays (ns) Output Load Capacitance (pF) 50 75 100 2.5 3.1 3.6 2.6 3.2 3.7 1.7 2.2 2.8 2.0 2.6 3.1 10 3.6 3.1 0.0 3.0 2.9 2.3 0.0 150 4.7 4.8 3.9 4.2 Notes: [7] The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11 loads per half column. [8] The following loads are used for tPXZ: tPHZ 1KΩ 5 pF 1KΩ tPLZ 5 pF 8-29 Military Plastic pASIC 3 Family QL3025 QL3025 AC CHARACTERISTICS at VCC = 3.3V, TA = 25°C (K = 1.00) (To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.) Logic Cells Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Propagation Delays (ns) Fanout [5] 2 3 4 1.7 1.9 2.2 1.7 1.7 1.7 0.0 0.0 0.0 1.0 1.2 1.5 1.2 1.2 1.2 1.2 1.2 1.2 1.3 1.5 1.8 1.1 1.3 1.6 1.9 1.9 1.9 1.8 1.8 1.8 Parameter Combinatorial Delay [6] Setup Time [6] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8 8 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8 Input-Only/Clock Cells Symbol tIN tINI tISU tIH tlCLK tlRST tlESU tlEH Parameter High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1 1.5 1.6 3.1 0.0 0.7 0.6 2.3 0.0 Propagation Delays (ns) Fanout [5] 2 3 4 8 12 1.6 1.8 1.9 2.4 2.9 1.7 1.9 2.0 2.5 3.0 3.1 3.1 3.1 3.1 3.1 0.0 0.0 0.0 0.0 0.0 0.8 1.0 1.1 1.6 2.1 0.7 0.9 1.0 1.5 2.0 2.3 2.3 2.3 2.3 2.3 0.0 0.0 0.0 0.0 0.0 24 4.4 4.5 3.1 0.0 3.6 3.5 2.3 0.0 Notes: [5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [6] These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design. 8-30 30 Preliminary Military Plastic pASIC 3 Family QL3025 Clock Cells Symbol tACK tGCKP tGCKB Parameter 1 1.2 0.7 0.8 Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay Propagation Delays (ns) Loads per Half Column [7] 2 3 4 8 10 1.2 1.3 1.3 1.5 1.6 0.7 0.7 0.7 0.7 0.7 0.8 0.9 0.9 1.1 1.2 12 1.7 0.7 1.3 15 1.8 0.7 1.4 I/O Cells Symbol Parameter tI/O tISU tIH tlOCLK tlORST tlESU tlEH Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time Symbol Parameter tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State [8] Output Delay Low to Tri-State [8] 1 1.3 3.1 0.0 0.7 0.6 2.3 0.0 30 2.1 2.2 1.2 1.6 2.0 1.2 Propagation Delays (ns) Fanout [5] 2 3 4 8 1.6 1.8 2.1 3.1 3.1 3.1 3.1 3.1 0.0 0.0 0.0 0.0 1.0 1.2 1.5 2.5 0.9 1.1 1.4 2.4 2.3 2.3 2.3 2.3 0.0 0.0 0.0 0.0 10 3.6 3.1 0.0 3.0 2.9 2.3 0.0 Propagation Delays (ns) Output Load Capacitance (pF) 50 75 100 2.5 3.1 3.6 2.6 3.2 3.7 1.7 2.2 2.8 2.0 2.6 3.1 150 4.7 4.8 3.9 4.2 Notes: [7] The array distributed networks consist of 56 half columns and the global distributed networks consist of 60 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 12 loads per half column. The global clock has up to 15 loads per half column. [8] The following loads are used for tPXZ: tPHZ 1KΩ 5 pF 1KΩ tPLZ 5 pF 8-31 Military Plastic pASIC 3 Family QL3040 QL3040 AC CHARACTERISTICS at VCC = 3.3V, TA = 25°C (K = 1.00) (To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.) Logic Cells Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Propagation Delays (ns) Fanout [5] 2 3 4 1.7 1.9 2.2 1.7 1.7 1.7 0.0 0.0 0.0 1.0 1.2 1.5 1.2 1.2 1.2 1.2 1.2 1.2 1.3 1.5 1.8 1.1 1.3 1.6 1.9 1.9 1.9 1.8 1.8 1.8 Parameter Combinatorial Delay [6] Setup Time [6] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8 8 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8 Input-Only/Clock Cells Symbol tIN tINI tISU tIH tlCLK tlRST tlESU tlEH Parameter High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1 1.5 1.6 3.1 0.0 0.7 0.6 2.3 0.0 Propagation Delays (ns) Fanout [5] 2 3 4 8 12 1.6 1.8 1.9 2.4 2.9 1.7 1.9 2.0 2.5 3.0 3.1 3.1 3.1 3.1 3.1 0.0 0.0 0.0 0.0 0.0 0.8 1.0 1.1 1.6 2.1 0.7 0.9 1.0 1.5 2.0 2.3 2.3 2.3 2.3 2.3 0.0 0.0 0.0 0.0 0.0 24 4.4 4.5 3.1 0.0 3.6 3.5 2.3 0.0 Notes: [5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [6] These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design. 8-32 32 Preliminary Military Plastic pASIC 3 Family QL3040 Clock Cells Symbol Parameter tACK tGCKP tGCKB Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay 1 1.2 0.7 0.8 2 1.2 0.7 0.8 Propagation Delays (ns) Loads per Half Column [7] 3 4 8 10 12 1.3 1.3 1.5 1.6 1.7 0.7 0.7 0.7 0.7 0.7 0.9 0.9 1.1 1.2 1.3 14 1.8 0.7 1.4 16 1.9 0.7 1.5 I/O Cells Symbol Parameter tI/O tISU tIH tlOCLK tlORST tlESU tlEH Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time Symbol Parameter tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State [8] Output Delay Low to Tri-State [8] 1 1.3 3.1 0.0 0.7 0.6 2.3 0.0 30 2.1 2.2 1.2 1.6 2.0 1.2 Propagation Delays (ns) Fanout [5] 2 3 4 8 1.6 1.8 2.1 3.1 3.1 3.1 3.1 3.1 0.0 0.0 0.0 0.0 1.0 1.2 1.5 2.5 0.9 1.1 1.4 2.4 2.3 2.3 2.3 2.3 0.0 0.0 0.0 0.0 Propagation Delays (ns) Output Load Capacitance (pF) 50 75 100 2.5 3.1 3.6 2.6 3.2 3.7 1.7 2.2 2.8 2.0 2.6 3.1 10 3.6 3.1 0.0 3.0 2.9 2.3 0.0 150 4.7 4.8 3.9 4.2 Notes: [7] The array distributed networks consist of 72 half columns and the global distributed networks consist of 76 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 14 loads per half column. The global clock has up to 16 loads per half column. [8] The following loads are used for tPXZ: tPHZ 1KΩ 5 pF 1KΩ tPLZ 5 pF 8-33 Military Plastic pASIC 3 Family QL3060 QL3060 AC CHARACTERISTICS at VCC = 3.3V, TA = 25°C (K = 1.00) (To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.) Logic Cells Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Propagation Delays (ns) Fanout [5] 2 3 4 1.7 1.9 2.2 1.7 1.7 1.7 0.0 0.0 0.0 1.0 1.2 1.5 1.2 1.2 1.2 1.2 1.2 1.2 1.3 1.5 1.8 1.1 1.3 1.6 1.9 1.9 1.9 1.8 1.8 1.8 Parameter Combinatorial Delay [6] Setup Time [6] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8 8 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8 Input-Only/Clock Cells Symbol tIN tINI tISU tIH tlCLK tlRST tlESU tlEH Parameter High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1 1.5 1.6 3.1 0.0 0.7 0.6 2.3 0.0 Propagation Delays (ns) Fanout [5] 2 3 4 8 12 1.6 1.8 1.9 2.4 2.9 1.7 1.9 2.0 2.5 3.0 3.1 3.1 3.1 3.1 3.1 0.0 0.0 0.0 0.0 0.0 0.8 1.0 1.1 1.6 2.1 0.7 0.9 1.0 1.5 2.0 2.3 2.3 2.3 2.3 2.3 0.0 0.0 0.0 0.0 0.0 24 4.4 4.5 3.1 0.0 3.6 3.5 2.3 0.0 Notes: [5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [6] These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design. 8-34 34 Preliminary Military Plastic pASIC 3 Family QL3060 Clock Cells Symbol Parameter tACK tGCKP tGCKB Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay Propagation Delays (ns) Loads per Half Column [7] 1 2 3 4 8 10 12 14 16 18 20 1.2 0.7 0.8 1.2 0.7 0.8 1.3 0.7 0.9 1.3 0.7 0.9 1.5 0.7 1.1 1.6 0.7 1.2 1.7 0.7 1.3 1.8 0.7 1.4 1.9 0.7 1.5 2 0.7 1.6 2.1 0.7 1.7 I/O Cells Symbol Parameter tI/O tISU tIH tlOCLK tlORST tlESU tlEH Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time Symbol Parameter tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State [8] Output Delay Low to Tri-State [8] 1 1.3 3.1 0.0 0.7 0.6 2.3 0.0 30 2.1 2.2 1.2 1.6 2.0 1.2 Propagation Delays (ns) Fanout [5] 2 3 4 8 1.6 1.8 2.1 3.1 3.1 3.1 3.1 3.1 0.0 0.0 0.0 0.0 1.0 1.2 1.5 2.5 0.9 1.1 1.4 2.4 2.3 2.3 2.3 2.3 0.0 0.0 0.0 0.0 Propagation Delays (ns) Output Load Capacitance (pF) 50 75 100 2.5 3.1 3.6 2.6 3.2 3.7 1.7 2.2 2.8 2.0 2.6 3.1 10 3.6 3.1 0.0 3.0 2.9 2.3 0.0 150 4.7 4.8 3.9 4.2 Notes: [7] The array distributed networks consist of 88 half columns and the global distributed networks consist of 92 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 18 loads per half column. The global clock has up to 20 loads per half column. [8] The following loads are used for tPXZ: tPHZ 1KΩ 5 pF 1KΩ tPLZ 5 pF 8-35 Military Plastic pASIC 3 Family Pin Descriptions Pin TDI Function Test Data In for JTAG TRSTB Active low Reset for JTAG TMS Test Mode Select for JTAG TCK Test Clock for JTAG TDO Test data out for JTAG STM Special Test Mode I/ACLK I High-drive input and/or array network driver High-drive input and/or global network driver High-drive input I/O Input/Output pin Can be configured as an input and/or output. VCC Power supply pin Connect to 3.3V supply. VCCIO Input voltage tolerance pin GND Ground pin Connect to 5.0 volt supply if 5 volt input tolerance is required, otherwise connect to 3.3V supply. Connect to ground. GND/THERM Ground/Thermal pin I/GCLK Description Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold LOW during normal operation. Connect to ground if not used for JTAG. Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG. Output that must be left unconnected if not used for JTAG. Must be grounded during normal operation. Can be configured as either or both. Can be configured as either or both. Use for input signals with high fanout. Available on 456-PBGA only. Connect to ground plane on PCB if heat sinking desired. Otherwise may be left unconnected. Ordering Information QL 3060 –1 PQ208 M QuickLogic pASIC device Operating Range M = Military pASIC 3 device part number 3012 3025 3040 3060 Package Code PL84 = 84-pin PLCC PQ208 = 208-pin PQFP Speed Grade 0 = quick 1 = fast 2 = faster 8-36 36 Preliminary