IDT74ALVC162268 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS IDT74ALVC162268 FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V µ W typ. static) • CMOS power levels (0.4µ • Rail-to-Rail output swing for increased noise margin • Available in SSOP, TSSOP, and TVSOP packages This registered bus exchanger is built using advanced dual metal CMOS technology. This device is used for applications in which data must be transferred from a narrow high-speed bus to a wide, lower-frequency bus. The ALVC162268 device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-tohigh transition of the clock (CLK) input when the appropriate clock-enable (CLKEN) inputs are low. The select (SEL) line is synchronous with CLK and selects 1B or 2B input data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be presented synchronously as a 24bit word on the B-port. Data flow is controlled by the active-low output enables (OEA and OEB). These control terminals are registered to synchronize the bus-direction changes with CLK. The ALVC162268 has series resistors in the device output structure of the “B” port which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. The “A” port has a ±24mA driver. DRIVE FEATURES: • High Output Drivers: ±24mA (A port) • Balanced Output Drivers: ±12mA (B port) APPLICATIONS: • 3.3V high speed systems • 3.3V and lower voltage computing systems FUNCTIONAL BLOCK DIAGRAM 29 CLK 2 CLKEN1B 27 CLKEN2B 30 CLKENA1 55 CLKENA2 C1 56 OEB 1D C1 28 SEL 1D 1 OEA CE C1 1D 1D 23 1B 1 C1 A1 CE C1 0 8 1D 1 CE C1 CE C1 1D 1D 6 2B 1 CE C1 1D 1 of 12 Channels The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE AUGUST 1999 1 © 1999 Integrated Device Technology, Inc. DSC-4550/1 IDT74ALVC162268 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description VTERM(2) Max Unit V Terminal Voltage with Respect to GND –0.5 to +4.6 O EA 1 56 O EB VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V CLKEN 1B 2 55 CLKEN A2 TSTG Storage Temperature –65 to +150 °C 2B 3 3 54 2B 4 IOUT DC Output Current –50 to +50 mA IIK Continuous Clamp Current, VI < 0 or VI > VCC ±50 mA IOK Continuous Clamp Current, VO < 0 –50 mA ICC ISS Continuous Current through each VCC or GND ±100 mA G ND 4 53 G ND 2B 2 5 52 2B 5 2B 1 6 51 2B 6 V CC 7 50 V CC A1 8 49 2B 7 A2 9 48 2B 8 A3 10 47 2B 9 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. G ND 11 46 G ND A4 12 45 2 B 10 A5 13 44 2 B 11 A6 14 43 2 B 12 A7 15 42 1 B 12 Symbol A8 16 41 1 B 11 CIN Input Capacitance VIN = 0V 5 7 pF COUT Output Capacitance VOUT = 0V 7 9 pF COUT I/O Port Capacitance VIN = 0V 7 9 pF CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Conditions Typ. Max. Unit A9 17 40 1 B 10 G ND 18 39 G ND A 10 19 38 1B 9 A 11 20 37 1B 8 A 12 21 36 1B 7 V CC 22 35 V CC 1B 1 23 34 1B 6 1B 2 24 33 1B 5 G ND 25 32 G ND CLK OEA OEB Ax 1Bx, 2Bx 1B 3 26 31 1B 4 ↑ H H Z Z CLKEN 2B 27 30 CLKEN A1 ↑ H L Z Active SE L 28 29 CLK ↑ L H Active Z ↑ L L Active Active NOTE: 1. As applicable to the device type. FUNCTION TABLES(1) OUTPUT ENABLE Inputs Outputs SSOP/ TSSOP/ TVSOP TOP VIEW A-TO-B STORAGE (OEB = L AND OEA = H) Inputs CLKENA1 2 CLKENA2 Outputs CLK Ax 1Bx (2) 1B0 H H X X L L ↑ L (3) L (3) 2Bx 2B0 L L L ↑ H X L ↑ L X L X L ↑ H X H H H (2) IDT74ALVC162268 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER INDUSTRIAL TEMPERATURE RANGE FUNCTION TABLES (CONTINUED)(1) B-TO-A STORAGE (OEA = L AND OEA = H) Inputs Output CLKEN1B CLKEN2B CLK SEL 1Bx 2Bx H X X H X X A0 X H X L X X A0 L X ↑ H L X L L X ↑ H H X H X L ↑ L X L L X L ↑ L X H H Ax (2) (2) NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance ↑ = LOW-to-HIGH transition 2. Output level before the indicated steady-state input conditions were established. 3. Two CLK edges are needed to propagate data. PIN DESCRIPTION Pin Names I/O Ax (1:12) I/O Bidirectional Data Port A. Usually connected to the CPU's address/data bus. Description 1Bx (1:12) I/O Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory. 2Bx (1:12) I/O Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory. CLK I Clock Input CLKENA1 I Clock Enable Input for the A-1B Register. If CLKENA1 is LOW during the rising edge of CLK, data will be clocked into register A-1B (Active LOW). CLKENA2 I Clock Enable Input for the A-1B Register. If CLKENA2 is LOW during the rising edge of CLK, data will be clocked into register A-2B (Active LOW). CLKEN1B I Clock Enable Input for the A-1B Register. If CLKEN1B is LOW during the rising edge of CLK, data will be clocked into register 1B-A (Active LOW). CLKEN2B I Clock Enable Input for the A-1B Register. If CLKEN2B is LOW during the rising edge of CLK, data will be clocked into register 2B-A (Active LOW). SEL I 1B or 2B Port Selection. When HIGH during the rising edge of CLK, SEL enables data transfer from 1B Port to A Port. When LOW during the rising edge of CLK, SEL enables data transfer from 2B Port to A Port (Active LOW). OEA I Synchronous Output Enable for A Port (Active LOW) OEB I Synchronous Output Enable for A Port (Active LOW) 3 IDT74ALVC162268 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V IIH Input HIGH Current VCC = 3.6V VI = VCC — — ±5 µA IIL Input LOW Current VCC = 3.6V VI = GND — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = VCC — — ±10 µA IOZL (3-State Output pins) VO = GND — — ±10 VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 0.1 — 40 mV µA Quiescent Power Supply Current Variation One input at VCC - 0.6V, other inputs at VCC or GND — — 750 µA NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. OUTPUT DRIVE CHARACTERISTICS (A PORT) Symbol VOH VOL Test Conditions(1) Parameter Output HIGH Voltage Output LOW Voltage Min. Max. Unit V VCC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 — VCC = 2.3V IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — VCC = 2.7V 2.2 — VCC = 3V 2.4 — VCC = 3V IOH = – 24mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. 4 IDT74ALVC162268 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS (B PORT) Symbol VOH Test Conditions(1) Parameter Output HIGH Voltage VCC = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V VCC = 2.7V VOL Output LOW Voltage Min. Max. Unit VCC – 0.2 — V IOH = – 4mA 1.9 — IOH = – 6mA 1.7 — IOH = – 4mA 2.2 — IOH = – 8mA 2 — VCC = 3V IOH = – 6mA 2.4 — IOH = – 12mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 4mA — 0.4 IOL = 6mA — 0.55 IOL = 4mA — 0.4 IOL = 8mA — 0.6 IOL = 6mA — 0.55 IOL = 12mA — 0.8 VCC = 2.7V VCC = 3V V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance Outputs enabled CPD Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz 5 VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Typical Typical Unit 87 120 pF 80 118 IDT74ALVC162268 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS (A PORT)(1) VCC = 2.5V ± 0.2V Symbol Parameter Min. fMAX tPLH Propagation Delay tPHL CLK to Ax (1B) tPLH Propagation Delay tPHL CLK to Ax (2B) tPLH Propagation Delay tPHL CLK to Ax (SEL) tPZH Output Enable Time VCC = 2.7V Max. Min. 120 — 1.6 5.8 1.6 VCC = 3.3V ± 0.3V Max. Min. Max. Unit 125 — — 5.4 150 — MHz 1.7 4.8 ns 5.8 — 5.3 1.8 4.8 ns 2.5 7.3 — 6.5 2.4 5.8 ns 2 6.2 — 5.6 1.8 5.1 ns 2 6.5 — 5.4 2.1 5 ns 4.5 — 4 — 3.4 — ns tPZL CLK to Ax tPHZ Output Disable Time tPLZ CLK to Ax tSU Set-up Time, Ax data before CLK↑ tSU Set-up Time, SEL before CLK↑ 1.4 — 1.6 — 1.3 — ns tSU Set-up Time, CLKENA1 or CLKENA2 before CLK↑ 3.6 — 3.4 — 2.8 — ns tSU Set-up Time, OEA before CLK↑ 4.2 — 3.9 — 3.2 — ns tH Hold Time, Ax data after CLK ↑ 0 — 0 — 0.2 — ns tH Hold Time, SEL after CLK↑ tH Hold Time, CLKENA1 or CLKENA2 after CLK↑ tH Hold Time, OEA after CLK↑ tW Pulse Width, CLK HIGH or LOW Output Skew(2) — tSK(O) 1 — 1 — 1 — ns 0.1 — 0.1 — 0.4 — ns 0 — 0 — 0.2 — ns 3.3 — 3.3 — 3.3 — ns — — — — 500 ps NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. SWITCHING CHARACTERISTICS (B PORT)(1) VCC = 2.5V ± 0.2V Symbol Parameter Min. fMAX tPLH Propagation Delay tPHL CLK to 1Bx, 2Bx tPZH Output Enable Time VCC = 2.7V Max. Min. 120 — 1.6 6.1 2.7 VCC = 3.3V ± 0.3V Max. Min. Max. Unit 125 — — 5.9 150 — MHz 1.8 5.4 ns 7.2 — 6.8 2.6 6.1 ns 2.8 7.2 — 6.1 2.5 5.9 ns — 1.2 — 1 — ns tPZL CLK to 1Bx, 2Bx tPHZ Output Disable Time tPLZ CLK to 1Bx, 2Bx tSU Set-up Time, Bx data before CLK↑ 0.8 tSU Set-up Time, CLKEN1B or CLKEN2B before CLK↑ 3.2 — 3 — 2.5 — ns tSU Set-up Time, OEB before CLK↑ 4.2 — 3.9 — 3.2 — ns tH Hold Time, Bx data after CLK ↑ 1.3 — 1.2 — 1.3 — ns tH Hold Time, CLKEN1B or CLKEN2B after CLK↑ 0.1 — 0 — 0.5 — ns tH Hold Time, OEB after CLK↑ 0 — 0 — 0.2 — ns Output Skew(2) — — — — — 500 ps tSK(O) NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 6 IDT74ALVC162268 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS VCC(1)= 3.3V±0.3V VCC(1)= 2.7V Symbol V IH VT 0V SAME PH ASE INPU T TRANSITION VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF t PLH t PHL tPLH t PHL V OH VT V OL OUTPUT V IH VT 0V OPPOSITE PHASE INPU T TRANSITION ALVC Link Propagation Delay V LOAD V CC Open 500 Ω (1, 2) V IN CON TROL INPU T V OUT Pulse Generator DISABLE EN ABLE GND D.U.T. VT t PZL OUTPUT SW ITCH NOR MALLY CLO SED LOW t PZH OUTPUT SW ITCH NOR MALLY O PE N HIGH 500 Ω RT CL ALVC Link Test Circuit for All Outputs DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. VLOAD Disable High Enable High GND All Other Tests Open V LOAD/2 V OL + V LZ V OL t PHZ V OH V OH - V HZ VT 0V 0V Enable and Disable Times SWITCH POSITION Open Drain Disable Low Enable Low V LOAD/2 VT NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. DATA INPU T Switch 0V t PLZ ALV C Link NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns. Test V IH tS U V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V tH TIM ING INPU T tR EM ASYNC HRONOUS CON TROL SYNCH RONOUS CON TROL tS U tH ALVC Link Set-up, Hold, and Release Times V IH INPU T VT 0V tPHL1 t PLH1 LOW -HIGH-LOW PU LSE V OH OUTPUT 1 tSK (x) VT V OL t SK (x) tW V OH HIGH-LOW -HIGH PU LSE VT V OL OUTPUT 2 t PLH2 VT ALVC Link t PHL2 Pulse Width t SK (x) = t PLH2 - tP LH1 or t PH L2 - t PHL1 Output Skew - tSK(X) VT ALVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 7 IDT74ALVC162268 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX ALVC Tem p. Range X XX XXX XX Bus-Hold Family Device Type Package CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 PV PA PF Shrink S m all Outline Package Thin Shrink Sm all Outline Package Thin Very Small Outline Package 268 12-Bit to 24-Bit Registered Bus Exchanger w ith 3-State Outputs 162 Double-Density, ±24m A (A port) ±12m A (B port) Blank No Bus-Hold 74 –40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 8 for Tech Support: [email protected] (408) 654-6459