ETC AM186CH

Am186™CH
High-Performance, 80C186-Compatible
16-Bit Embedded HDLC Microcontroller
DISTINCTIVE CHARACTERISTICS
■ E86™ family of x86 embedded processors
offers improved time-to-market
– Software migration (backwards- and upwardscompatible)
– World-class development tools, applications, and
system software
■ Serial Communications Peripherals
– Programmable I/O (48 PIO signals)
– Interrupt Controller (36 maskable interrupts)
■ Memory and Peripheral Interface
– Integrated DRAM controller
– Glueless interface to RAM/ROM/Flash memory
(55-ns Flash memory required for zero-wait-state
operation at 50 MHz)
– Two High-level Data Link Control (HDLC) channels
– Fourteen chip selects (8 peripherals, 6 memory)
– Two independent Time Slot Assigners (TSAs)
– External bus mastering support
– Physical interface for HDLC channels can be raw
DCE or PCM Highway
– Multiplexed and nonmultiplexed address/data bus
– High-Speed UART with autobaud
– UART
– Synchronous serial interface (SSI)
– SmartDMA™ channels (4) to support HDLC
■ System Peripherals
– Three programmable 16-bit timers
– Hardware watchdog timer
– General-purpose DMA (4 channels)
– Programmable bus sizing
– 8-bit boot option
■ Available in the following package:
– 160-pin plastic quad flat pack (PQFP)
– 25-, 40-, and 50-MHz operating frequencies
– Low-voltage operation, VCC = 3.3 V ± 0.3 V
– Commercial and industrial temperature rating
– 5-V-tolerant I/O (3.3-V output levels)
GENERAL DESCRIPTION
The Am186™CH HDLC microcontroller is a member of
AMD’s Comm86™ family of communications-specific
microcontrollers. The microcontroller is a derivative of
the Am186CC communications controller and is pincompatible with that device.
The Am186CH HDLC microcontroller is a costeffective, high-performance microcontroller solution for
communications applications. This highly integrated
microcontroller enables customers to save system
costs and increase perfor mance over 8-bit
microcontrollers and other 16-bit microcontrollers.
applications, including High-level Data Link Control
(HDLC).
Comprehensive development support is available from
AMD and its FusionE86 SM par tners. A customer
development platform board is available. AMD and its
FusionE86 partners also offer boards, schematics,
drivers, protocol stacks, and routing software to enable
fast time to market.
The microcontroller offers the advantages of the x86
development environment’s widely available native
development tools, applications, and system software.
Additionally, the microcontroller uses the industrystandard 186 instruction set that is part of the AMD
E86™ family, which continually offers instruction-setcompatible upgrades. Built into the Am186CH HDLC
microcontroller is a wide range of communications
features required in many communications
© Copyright 2000 Advanced Micro Devices, Inc. All rights reserved
Publication# 22024 Rev: B Amendment/0
Issue Date: May 2000
ORDERING INFORMATION
Am186CH
–50
K
C
\W
LEAD FORMING
\W=Trimmed and Formed
TEMPERATURE RANGE
C= Am186CH Commercial (TC =0•C to +100•C)
I = Am186CH Industrial (TA =–40•C to +85•C)
where: TC = case temperature
where: TA = ambient temperature
PACKAGE TYPE
K=160-Pin Plastic Quad Flat Pack (PQFP)
SPEED OPTION
–25 = 25 MHz
–40 = 40 MHz
–50 = 50 MHz
DEVICE NUMBER/DESCRIPTION
Am186CH high-performance 80C186-compatible
16-bit embedded HDLC microcontroller
Valid Combinations
Am186CH–25
Am186CH–40
KC\W
Am186CH–50
Am186CH–25
Am186CH–40
2
Valid Combinations
Valid combinations list configurations planned to be
supported in volume for this device. Consult the
local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
KI\W
Am186™CH HDLC Microcontroller Data Sheet
TABLE OF CONTENTS
Distinctive Characteristics ............................................................................................................ 1
General Description ..................................................................................................................... 1
Ordering Information .................................................................................................................... 2
Table of Contents ........................................................................................................................ 3
List of Figures .............................................................................................................................. 4
List of Tables ............................................................................................................................... 5
Logic Diagram By Interface ......................................................................................................... 6
Logic Diagram By Default Pin Function ....................................................................................... 7
Pin Connection Diagram—160-Pin PQFP Package .................................................................... 8
Pin and Signal Tables .................................................................................................................. 9
Signal Descriptions ............................................................................................................... 12
Architectural Overview ............................................................................................................... 24
Detailed Description .............................................................................................................. 24
Am186™ Embedded CPU .................................................................................................... 25
Memory Organization ............................................................................................................ 25
I/O Space .............................................................................................................................. 25
Serial Communications Support ............................................................................................ 26
Two HDLC Channels and Two TSAs ............................................................................... 26
Four SmartDMA™ Channels............................................................................................ 26
Two Asynchronous Serial Ports ....................................................................................... 26
Synchronous Serial Port................................................................................................... 27
System Peripherals ............................................................................................................... 27
Interrupt Controller ........................................................................................................... 27
Four General-Purpose DMA Channels ............................................................................ 27
48 Programmable I/O Signals .......................................................................................... 27
Three Programmable Timers ........................................................................................... 27
Hardware Watchdog Timer .............................................................................................. 28
Memory and Peripheral Interface .......................................................................................... 28
System Interfaces............................................................................................................. 28
DRAM Support ................................................................................................................. 30
Chip Selects ..................................................................................................................... 30
Clock Control ......................................................................................................................... 31
In-Circuit Emulator Support ................................................................................................... 31
Applications ............................................................................................................................... 31
Clock Generation and Control ................................................................................................... 33
Features ................................................................................................................................ 33
System Clock ........................................................................................................................ 33
Crystal-Driven Clock Source ................................................................................................. 34
External Clock Source ........................................................................................................... 35
Static Operation .................................................................................................................... 35
PLL Bypass Mode ................................................................................................................. 35
UART Baud Clock ................................................................................................................. 35
Power Supply Operation ............................................................................................................ 36
Power Supply Connections ................................................................................................... 36
Input/Output Circuitry ............................................................................................................ 36
PIO Supply Current Limit ...................................................................................................... 36
Absolute Maximum Ratings ....................................................................................................... 37
Operating Ranges ...................................................................................................................... 37
DC Characteristics over Commercial and Industrial Operating Ranges .................................... 37
Maximum Load Derating ............................................................................................................ 38
Capacitance ............................................................................................................................... 38
Power Supply Current ................................................................................................................ 38
Am186™CH HDLC Microcontroller Data Sheet
3
Thermal Characteristics—PQFP Package ................................................................................ 39
Commercial and Industrial Switching Characteristics and Waveforms ...................................... 40
Switching Characteristics over Commercial and Industrial Operating Ranges ......................................47
Appendix A—Pin Tables ............................................................................................................A-1
CPU PLL Modes.............................................................................................................. A-7
Pin List Table Column Definitions ......................................................................................A-10
Appendix B—Physical Dimensions: PQR160, Plastic Quad Flat Pack (PQFP) ........................B-1
Appendix C—Customer Support ...............................................................................................C-1
Related AMD Products—E86™ Family Devices ..................................................................C-1
Related Documents ..............................................................................................................C-2
Am186CC/CH/CU Microcontroller Customer Development Platform ..................................C-2
Third-Party Development Support Products .................................................................................C-2
Customer Service .................................................................................................................C-2
Hotline and World Wide Web Support............................................................................. C-2
Corporate Applications Hotline........................................................................................ C-2
World Wide Web Home Page ......................................................................................... C-3
Documentation and Literature ......................................................................................... C-3
Literature Ordering .......................................................................................................... C-3
Index ................................................................................................................................... Index-1
LIST OF FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
4
Am186CH Microcontroller Block Diagram ............................................................. 24
Two-Component Address Example ...................................................................... 25
Am186CH Microcontroller Address Bus — Default Operation .............................. 29
Am186CH Microcontroller—Address Bus Disable In Effect .................................. 29
32-Channel Linecard System Application ............................................................. 32
System Clock Generation ..................................................................................... 33
Suggested System Clock Frequencies, Clock Modes, and Crystal Frequencies . 34
External Interface to Support Clocks—Fundamental Mode Crystal ...................... 34
External Interface to Support Clocks—External Clock Source ............................. 35
UART and High-Speed UART Clocks ................................................................... 35
Typical Icc Versus Frequency ................................................................................ 38
Thermal Resistance(•C/Watt) ............................................................................... 39
Thermal Characteristics Equations ....................................................................... 39
Key to Switching Waveforms ................................................................................ 40
Read Cycle Waveforms ........................................................................................ 49
Write Cycle Waveforms ......................................................................................... 52
Software Halt Cycle Waveforms ........................................................................... 53
Peripheral Timing Waveforms ............................................................................... 54
Reset Waveforms .................................................................................................. 55
Signals Related to Reset (System PLL in 1x or 2x Mode) .................................... 56
Signals Related to Reset (System PLL in 4x Mode) ............................................. 56
Synchronous Ready Waveforms ........................................................................... 57
Asynchronous Ready Waveforms ......................................................................... 58
Entering Bus Hold Waveforms .............................................................................. 59
Exiting Bus Hold Waveforms ................................................................................. 60
System Clocks Waveforms—Active Mode (PLL 1x Mode) ................................... 62
PCM Highway Waveforms (Timing Slave) ............................................................ 63
PCM Highway Waveforms (Timing Master) .......................................................... 64
DCE Transmit Waveforms .................................................................................... 65
DCE Receive Waveforms ..................................................................................... 65
SSI Waveforms ..................................................................................................... 66
DRAM Read Cycle without Wait States Waveform ............................................... 68
Am186™CH HDLC Microcontroller Data Sheet
Figure 33.
Figure 34.
Figure 35.
Figure 36.
DRAM Read Cycle with Wait States Waveform .................................................... 68
DRAM Write Cycle without Wait States Waveform ............................................... 69
DRAM Write Cycle with Wait States Waveform .................................................... 69
DRAM Refresh Cycle Waveform ........................................................................... 70
LIST OF TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
PQFP Pin Assignments—Sorted by Pin Number .................................................. 10
PQFP Pin Assignments—Sorted by Signal Name ................................................ 11
Signal Descriptions Table Definitions..................................................................... 12
Signal Descriptions ............................................................................................... 13
Segment Register Selection Rules ....................................................................... 26
Crystal Parameters ................................................................................................ 34
Typical Power Consumption Calculation................................................................ 38
Thermal Characteristics (°C/Watt) ........................................................................ 39
Alphabetical Key to Switching Parameter Symbols .............................................. 41
Numerical Key to Switching Parameter Symbols .................................................. 44
Read Cycle Timing ................................................................................................ 47
Write Cycle Timing ................................................................................................ 50
Software Halt Cycle Timing ................................................................................... 53
Peripheral Timing ................................................................................................. 54
Reset Timing ......................................................................................................... 55
External Ready Cycle Timing ................................................................................ 57
Bus Hold Timing .................................................................................................... 59
System Clocks Timing ........................................................................................... 61
PCM Highway Timing (Timing Slave) .................................................................. 62
PCM Highway Timing (Timing Master) ................................................................. 64
DCE Interface Timing ........................................................................................... 65
SSI Timing ............................................................................................................. 66
DRAM Timing ........................................................................................................ 67
Power-On Reset (POR) Pin Defaults ...................................................................A-2
Multiplexed Signal Trade-Offs ..............................................................................A-5
Reset Configuration Pins (Pinstraps) ...................................................................A-7
PIOs Sorted by PIO Number ................................................................................A-8
PIOs Sorted by Signal Name ...............................................................................A-9
Pin List Table Definitions.....................................................................................A-10
Pin List Summary ...............................................................................................A-11
Am186™CH HDLC Microcontroller Data Sheet
5
LOGIC DIAGRAM BY INTERFACE1
CLKOUT
RES
RESOUT
X1
X2
Reset/
Clocks
Address and
Address/Data
Buses
20
A19–A0
16
AD15–AD0
2
/
Bus Status and
Control
3
Programmable
Timers
Debug
Programmable I/O
(PIO)
Configuration
Pinstraps
/
ALE
ARDY
BHE
BSIZE8
DEN
DS
DRQ1–DRQ0
DT/R
HLDA
HOLD
RD
S2–S0
S6
SRDY
WHB
WLB
WR
INT8–INT0
NMI
LCS
MCS3–MCS0
PCS7–PCS0
UCS
Am186CH HDLC
Microcontroller
2
/
2
/
QS1–QS0
/
48
/
PIO47–PIO0
{ADEN}
{CLKSEL1}
{CLKSEL2}
{ONCE}
{UCSX8}
4
8
/
DCE_RXD_A, B
DCE_TXD_A, B
DCE_RCLK_A, B
DCE_TCLK_A, B
DCE_CTS_A, B
DCE_RTR_A, B
PCM_RXD_A, B
PCM_TXD_A, B
PCM_CLK_A, B
PCM_FSC_A, B
PCM_TSC_A, B
Interrupts
Chip
Selects
/
/
CAS0
CAS1
RAS0
RAS1
PWD
TMRIN1–TMRIN0
TMROUT1–TMROUT0
2
9
DRAM Control
2
2
/
/
2
/
/
2
/
2
/
2
2
2
/
/
2
/
/
2
/
2
DCE Interface
(HDLC A–B)1
PCM Interface
(HDLC A–B)1
SDEN
SCLK
SDATA
Synchronous
Serial Interface
RXD_U
TXD_U
CTS_U
RTR_U
Asynchronous
Serial Interface
(UART)
RXD_HU
TXD_HU
CTS_HU
RTR_HU
High-Speed
UART
UCLK
UART Clock
Notes:
1. Because of multiplexing, not all interfaces are available at once. Refer to Table 25, “Multiplexed Signal Trade-Offs,” on page A-5.
6
Am186™CH HDLC Microcontroller Data Sheet
LOGIC DIAGRAM BY DEFAULT PIN FUNCTION1
CLKOUT
RES
RESOUT
X1
X2
Reset/
Clocks
Address and
Address/Data Buses
20
16
A19–A0
AD15–AD0
ALE [PIO33]
ARDY [PIO8]
BHE [PIO34] {ADEN}
BSIZE8
DEN [DS] [PIO30]
DRQ1
DT/R [PIO29]
HLDA {CLKSEL1}
HOLD
RD
Bus Status and
Control
S0
S1
S2
S6
SRDY [PIO35]
WHB
WLB
WR [PIO15]
Debug
QS1–QS0
High-Speed UART
TXD_HU
LCS [RAS0]
MCS1 [CAS1]
MCS2 [CAS0]
PCS0 [PIO13]
PCS1 [PIO14]
PCS2
PCS3
UCS {ONCE}
Chip
Selects
Interrupts
Reserved
DCE_RXD_A [PCM_RXD_A]
DCE_TXD_A [PCM_TXD_A]
DCE_RCLK_A [PCM_CLK_A]
DCE_TCLK_A [PCM_FSC_A]
6
/
INT5–INT0
NMI
—
—
—
—
—
—
—
—
RSVD_104
RSVD_103
RSVD_102
RSVD_101
RSVD_81
RSVD_80
RSVD_76
RSVD_75
PIO0 [TMRIN1]
PIO1 [TMROUT1]
PIO2 [PCS5]
PIO3 [PCS4] {CLKSEL2}
PIO4 [MCS0] {UCSX8}
PIO5 [MCS3] [RAS1]
PIO6 [INT8] [PWD]
PIO7 [INT7]
PIO8 [ARDY]
PIO9 [DRQ0]
PIO10 [SDEN]
Am186CH HDLC
Microcontroller
HDLC A
(DCE)
Programmable
I/O (PIO)
PIO11 [SCLK]
PIO12 [SDATA]
PIO16 [RXD_HU]
PIO17 [DCE_CTS_A] [PCM_TSC_A]
PIO18 [DCE_RTR_A]
PIO19 [INT6]
PIO20 [TXD_U]
PIO21 [UCLK]
PIO22
PIO23
PIO24 [CTS_U]
PIO25 [RTR_U]
PIO26 [RXD_U]
PIO27 [TMRIN0]
PIO28 [TMROUT0]
PIO31[PCS7]
PIO32[PCS6]
PIO36 [DCE_RXD_B] [PCM_RXD_B]
PIO37 [DCE_TXD_B] [PCM_TXD_B]
PIO38 [DCE_CTS_B] [PCM_TSC_B]
PIO39 [DCE_RTR_B]
PIO40 [DCE_RCLK_B] [PCM_CLK_B]
PIO41 [DCE_TCLK_B] [PCM_FSC_B]
PIO42
PIO43
PIO44
PIO45
PIO46 [CTS_HU]
PIO47 [RTR_HU]
Notes:
1. Pin names in bold indicate the default pin function. Brackets, [ ], indicate alternate, multiplexed functions. Braces, { }, indicate pinstrap pins.
Am186™CH HDLC Microcontroller Data Sheet
7
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
VCC
TXD_U
RXD_U
CTS_U
RTR_U
VSS
PIO43
PIO42
PIO44
PIO45
PIO22
PIO23
VCC
INT8/PWD
INT7
INT6
TMRIN1
TMROUT1
TMRIN0
TMROUT0
VSS
DCE_TXD_B/PCM_TXD_B
DCE_RXD_B/PCM_RXD_B
DCE_CTS_B/PCM_TSC_B
DCE_RTR_B
DCE_RCLK_B/PCM_CLK_B
DCE_TCLKB/PCM_FSC_B
VCC
UCS {ONCE}
LCS/RAS0
VSS
MCS3/RAS1
MCS2/CAS0
MCS1/CAS1
MCS0 {UCSX8}
VCC
DRQ0
DCE_CTS_A/PCM_TSC_A
DCE_RTR_A
VSS
PIN CONNECTION DIAGRAM—160-PIN PQFP PACKAGE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VSS
SDEN
SCLK
SDATA
PCS0
PCS1
PCS2
PCS3
PCS4 {CLKSEL2}
PCS5
PCS6
VCC
PCS7
ARDY
15 SRDY
120
119
118
117
116
115
114
113
112
111
110
109
108
107
VCC
DRQ1
RSVD_104
RSVD_103
RSVD_102
RSVD_101
VSS
HOLD
HLDA {CLKSEL1}
RD
WLB
WHB
BSIZE8
AD15
AD7
VCC
A19
A18
A17
AD14
AD6
A16
A15
VSS
VSS
RSVD_81
106
WR
DT/R
DEN/DS
ALE
BHE {ADEN}
VSS
UCLK
RTR_HU
CTS_HU
RXD_HU
TXD_HU
VCC
AD0
AD8
A0
A1
A2
VSS
AD1
AD9
A3
A4
AD2
AD10
VCC
VSS
A5
A6
A7
A8
AD3
AD11
VCC
A9
A10
AD4
AD12
VSS
S6
S2
S1
S0
RESOUT
VCC
CLKOUT
VSS
QS0
QS1
A11
A12
AD5
AD13
VCC
A13
A14
VSS
VSS_A
X1
X2
RSVD_75
RSVD_76
VCC_A
VCC
VCC
RSVD_80
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Am186CH HDLC
Microcontroller
VCC
DCE_TXD_A/PCM_TXD_A
DCE_RXD_A/PCM_RXD_A
DCE_RCLK_A/PCM_CLK_A
DCE_TCLK_A/PCM_FSC_A
NMI
RES
INT5
INT4
INT3
INT2
INT1
VSS
INT0
8
Am186™CH HDLC Microcontroller Data Sheet
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
PIN AND SIGNAL TABLES
Table 1 on page 10 and Table 2 on page 11 show the
pi n s s o r t ed by pi n nu mb e r a nd s i g na l n a me,
respectively.
Table 4 on page 13 contains the signal descriptions
(grouped alphabetically within function). The table
includes columns listing the multiplexed functions and
I/O type. Table 3 on page 12 defines terms used in
Table 4.
Refer to Appendix A, “Pin Tables,” on page A-1 for an
a d d i ti on a l gr o u p o f t a bl e s w i th t h e f o l l ow i n g
information:
■ Power-on reset (POR) pin defaults including pin
numbers and multiplexed functions—Table 24 on
page A-2.
■ Multiplexed
page A-5.
signal
trade-offs—Table 25
on
■ Pinstraps and
page A-7.
pinstrap
options—Table 26
on
■ Programmable I/O pins ordered by PIO pin number
and multiplexed signal name, respectively, including pin numbers, multiplexed functions, and pin configurations following system reset—Table 27 on
page A-8 and Table 28 on page A-9.
■ Pin and signal summary showing signal name and
alternate function, pin number, I/O type, maximum
load values, POR default function, reset state, POR
default operation, hold state, and voltage—Table 30
on page A-11.
In all tables the brackets, [ ], indicate alternate,
multiplexed functions, and braces, { }, indicate reset
configuration pins (pinstraps). The line over a pin name
indicates an active Low. The word pin refers to the
physical wire; the word signal refers to the electrical
signal that flows through it.
Am186™CH HDLC Microcontroller Data Sheet
9
Table 1. PQFP Pin Assignments—Sorted by Pin Number1
Pin No. Name—Left Side
Pin No. Name—Bottom Side Pin No. Name—Right Side
VSS
41
VSS
81
RSVD_81
121
VSS
2
SDEN/PIO10
42
A5
82
VSS
122
DCE_RTR_A/PIO18
3
SCLK/PIO11
43
A6
83
VSS
123
DCE_CTS_A/
PCM_TSC_A/PIO17
4
SDATA/PIO12
44
A7
84
A15
124
DRQ0/PIO9
5
PCS0/PIO13
45
A8
85
A16
125
VCC
MCS0/PIO4{UCSX8}
6
PCS1/PIO14
46
AD3
86
AD6
126
7
PCS2
47
AD11
87
AD14
127
MCS1/CAS1
8
PCS3
48
VCC
88
A17
128
MCS2/CAS0
MCS3/RAS1/PIO5
9
PCS4/PIO3{CLKSEL2}
49
A9
89
A18
129
10
PCS5/PIO2
50
A10
90
A19
130
VSS
11
PCS6/PIO32
51
AD4
91
VCC
131
LCS/RAS0
12
VCC
52
AD12
92
AD7
132
UCS{ONCE}
13
PCS7/PIO31
53
VSS
93
AD15
133
VCC
14
ARDY/PIO8
54
S6
94
BSIZE8
134
DCE_TCLK_B/
PCM_FSC_B/PIO41
15
SRDY/PIO35
55
S2
95
WHB
135
DCE_RCLK_B/
PCM_CLK_B/PIO40
16
WR/PIO15
56
S1
96
WLB
136
DCE_RTR_B/PIO39
17
DT/R/PIO29
57
S0
97
RD
137
DCE_CTS_B/
PCM_TSC_B/PIO38
18
DEN/DS/PIO30
58
RESOUT
98
HLDA{CLKSEL1}
138
DCE_RXD_B/
PCM_RXD_B/PIO36
19
ALE/PIO33
59
VCC
99
HOLD
139
DCE_TXD_B/
PCM_TXD_B/PIO37
20
BHE/PIO34{ADEN}
60
CLKOUT
100
VSS
140
VSS
21
VSS
61
VSS
101
RSVD_101
141
TMROUT0/PIO28
22
UCLK/PIO21
62
QS0
102
RSVD_102
142
TMRIN0/PIO27
23
RTR_HU/PIO47
63
QS1
103
RSVD_103
143
TMROUT1/PIO1
24
CTS_HU/PIO46
64
A11
104
RSVD_104
144
TMRIN1/PIO0
25
RXD_HU/PIO16
65
A12
105
DRQ1
145
INT6/PIO19
INT7/PIO7
26
TXD_HU
66
AD5
106
VCC
146
27
VCC
67
AD13
107
INT0
147
INT8/PWD/PIO6
28
AD0
68
VCC
108
VSS
148
VCC
29
AD8
69
A13
109
INT1
149
PIO23
30
A0
70
A14
110
INT2
150
PIO22
31
A1
71
VSS
111
INT3
151
PIO45
32
A2
72
VSS_A
112
INT4
152
PIO44
33
VSS
73
X1
113
INT5
153
PIO42
34
AD1
74
X2
114
RES
154
PIO43
35
AD9
75
RSVD_75
115
NMI
155
VSS
36
A3
76
RSVD_76
116
DCE_TCLK_A/
PCM_FSC_A
156
RTR_U/PIO25
37
A4
77
VCC_A
117
DCE_RCLK_A/
PCM_CLK_A
157
CTS_U/PIO24
38
AD2
78
VCC
118
DCE_RXD_A/
PCM_RXD_A
158
RXD_U/PIO26
39
AD10
79
VCC
119
DCE_TXD_A/
PCM_TXD_A
159
TXD_U/PIO20
40
VCC
80
RSVD_80
120
VCC
160
VCC
Notes:
1. SeeTable 27, “PIOs Sorted by PIO Number,” on page A-8 for PIOs sorted by PIO number.
10
Pin No. Name—Top Side
1
Am186™CH HDLC Microcontroller Data Sheet
Table 2. PQFP Pin Assignments—Sorted by Signal Name 1
Signal Name
Pin No. Signal Name
Pin No.
Signal Name
Pin No. Signal Name
Pin No.
A0
30
CLKOUT
60
PCS4/PIO3{CLKSEL2}
9
TXD_U/PIO20
A1
31
CTS_HU/PIO46
24
PCS5/PIO2
10
UCLK/PIO21
159
22
A10
50
CTS_U/PIO24
157
PCS6/PIO32
11
UCS {ONCE}
132
A11
64
DCE_CTS_A/
PCM_TSC_A/PIO17
123
PCS7/PIO31
13
VCC
12
A12
65
DCE_CTS_B/
PCM_TSC_B/PIO38
137
PIO22
150
VCC
27
A13
69
DCE_RCLK_A/
PCM_CLK_A
117
PIO23
149
VCC
40
A14
70
DCE_RCLK_B/
PCM_CLK_B/PIO40
135
PIO42
153
VCC
48
A15
84
DCE_RTR_A/PIO18
122
PIO43
154
VCC
59
A16
85
DCE_RTR_B/PIO39
136
PIO44
152
VCC
68
A17
88
DCE_RXD_A/PCM_RXD_A
118
PIO45
151
VCC
78
A18
89
DCE_RXD_B/
PCM_RXD_B/PIO36
138
QS0
62
VCC
91
A19
90
DCE_TCLK_A/
PCM_FSC_A
116
QS1
63
VCC
106
A2
32
DCE_TCLK_B/
PCM_FSC_B/PIO41
134
RD
97
VCC
120
A3
36
DCE_TXD_A/PCM_TXD_A
119
RES
114
VCC
125
A4
37
DCE_TXD_B/
PCM_TXD_B/PIO37
139
RESOUT
58
VCC
133
A5
42
DEN/DS/PIO30
18
RSVD_75
75
VCC
148
A6
43
DRQ0/PIO9
124
RSVD_76
76
VCC
160
A7
44
DRQ1
105
RSVD_80
80
VCC
79
A8
45
DT/R/PIO29
17
RSVD_81
81
VCC_A
77
A9
49
HLDA{CLKSEL1}
98
RSVD_101
101
VSS
1
AD0
28
HOLD
99
RSVD_102
102
VSS
21
AD1
34
INT0
107
RSVD_103
103
VSS
33
AD2
38
INT1
109
RSVD_104
104
VSS
41
AD3
46
INT2
110
RTR_HU/PIO47
23
VSS
53
AD4
51
INT3
111
RTR_U/PIO25
156
VSS
61
AD5
66
INT4
112
RXD_HU/PIO16
25
VSS
71
AD6
86
INT5
113
RXD_U/PIO26
158
VSS
83
AD7
92
INT6/PIO19
145
S0
57
VSS
100
AD8
29
INT7/PIO7
146
S1
56
VSS
108
AD9
35
INT8/PWD/PIO6
147
S2
55
VSS
121
AD10
39
LCS/RAS0
131
S6
54
VSS
130
AD11
47
MCS0/PIO4{UCSX8}
126
SCLK/PIO11
3
VSS
140
AD12
52
MCS1/CAS1
127
SDATA/PIO12
4
VSS
155
AD13
67
MCS2/CAS0
128
SDEN/PIO10
2
VSS
82
AD14
87
MCS3/RAS1/PIO5
129
SRDY/PIO35
15
VSS_A
72
AD15
93
NMI
115
TMRIN0/PIO27
142
WHB
95
96
ALE/PIO33
19
PCS0/PIO13
5
TMRIN1/PIO0
144
WLB
ARDY/PIO8
14
PCS1/PIO14
6
TMROUT0/PIO28
141
WR/PIO15
16
BHE/PIO34{ADEN}
20
PCS2
7
TMROUT1/PIO1
143
X1
73
BSIZE8
94
PCS3
8
TXD_HU
26
X2
74
Notes:
1. See Table 27, “PIOs Sorted by PIO Number,” on page A-8 for PIOs sorted by signal name.
Am186™CH HDLC Microcontroller Data Sheet
11
Signal Descriptions
Table 3.
Table 4 on page 13 contains a description of the
Am186CH HDLC microcontroller signals. Table 3
describes the terms used in Table 4. The signals are
organized alphabetically within the following functional
groups:
■ Bus interface/general-purpose
DMA request (page 13)
■ Clocks/reset/watchdog timer (page 17)
Term
[]
Indicates the pin alternate function; a pin
defaults to the signal named without the
brackets.
{}
Indicates the reset configuration pin (pinstrap).
pin
Refers to the physical wire.
reset
An external or power-on reset is caused by
asserting RES. An internal reset is initiated by
the watchdog timer. A system reset is one that
resets the Am186CH HDLC microcontroller (the
CPU plus the internal peripherals) as well as
any external peripherals connected to
RESOUT. An external reset always causes a
system reset; an internal reset can optionally
cause a system reset.
signal
Refers to the electrical signal that flows across
a pin.
■ Power and ground (page 18)
■ Debug support (page 18)
■ Chip selects (page 19)
■ DRAM (page 19)
■ Interrupts (page 20)
■ Programmable timers (page 21)
SIGNAL
■ Asynchronous serial ports (UART and High-Speed
UART) (page 21)
■ Synchronous serial interface (SSI) (page 22)
■ HDLC synchronous communication interfaces:
channels A and B for Data Communications
Equipment (DCE) and Pulse-Code Modulation
(PCM) interfaces (page 22)
For pinstraps refer to Table 26, “Reset Configuration
Pins (Pinstraps),” on page A-7.
A line over a signal name indicates that the
signal is active Low; a signal name without a
line is active High.
Signal types
B
Bidirectional
H
High
LS
Programmable to hold last state of pin
O
Totem pole output
OD
Open drain output
OD-O
Open drain output or totem pole output
PD
Internal pulldown resistor
PU
Internal pullup resistor
STI
Schmitt trigger input
STI-OD
TS
12
Definition
General terms
■ Reserved (page 18)
■ Programmable I/O (PIOs) (page 21)
Signal Descriptions Table Definitions
Schmitt trigger input or open drain output
Three-state output
Am186™CH HDLC Microcontroller Data Sheet
Table 4.
Signal Name
Multiplexed
Signal(s)
Signal Descriptions
Type Description
BUS INTERFACE/GENERAL-PURPOSE DMA REQUEST
A19–A0
—
O
Address Bus supplies nonmultiplexed memory or I/O addresses to the system
one half of a CLKOUT period earlier than the multiplexed address and data bus
(AD15–AD0). During bus-hold or reset conditions, the address bus is threestated with pulldowns.
When the lower or upper chip-select regions are configured for DRAM mode, the
A19–A0 bus provides the row and column addresses at the appropriate times.
The upper and lower memory chip-select ranges can be individually configured
for DRAM mode.
AD15–AD0
—
B
Address and Data Bus time-multiplexed pins supply memory or I/O addresses
and data to the system. This bus can supply an address to the system during the
first period of a bus cycle (t1). It transmits (write cycle) or receives (read cycle)
data to or from the system during the remaining periods of that cycle (t2, t3, and
t4). The address phase of these pins can be disabled—see the {ADEN} pin
description in Table 26, “Reset Configuration Pins (Pinstraps),” on page A-7.
During a reset condition, the address and data bus is three-stated with
pulldowns, and during a bus hold it is three-stated.
In addition, during a reset the state of the address and data bus pins (AD15–
AD0) is latched into the Reset Configuration (RESCON) register. This feature
can be used to provide software with information about the external system at
reset time.
ALE
[PIO33]
O
Address Latch Enable indicates to the system that an address appears on the
address and data bus (AD15–AD0). The address is guaranteed valid on the
falling edge of ALE.
ALE is three-stated and has a pulldown resistor during bus-hold or reset
conditions.
ARDY
[PIO8]
STI
Asynchronous Ready is a true asynchronous ready that indicates to the
microcontroller that the addressed memory space or I/O device will complete a
data transfer. The ARDY pin is asynchronous to CLKOUT and is active High. To
guarantee the number of wait states inserted, ARDY or SRDY must be
synchronized to CLKOUT. If the falling edge of ARDY is not synchronized to
CLKOUT as specified, an additional clock period can be added.
To always assert the ready condition to the microcontroller, tie ARDY and SRDY
High. If the system does not use ARDY, tie the pin Low to yield control to SRDY.
Am186™CH HDLC Microcontroller Data Sheet
13
Table 4. Signal Descriptions (Continued)
Signal Name
BHE
Multiplexed
Signal(s)
[PIO34]
{ADEN}
Type Description
O
Bus High Enable: During a memory access, BHE and the least-significant
address bit (AD0) indicate to the system which bytes of the data bus (upper,
lower, or both) participate in a bus cycle. The BHE and AD0 pins are encoded as
follows:
Data Byte Encoding
BHE
AD0
0
0
Type of Bus Cycle
Word transfer
0
1
High byte transfer (bits 15–8)
1
0
Low byte transfer (bits 7–0)
1
1
Refresh
BHE is asserted during t1 and remains asserted through t3 and tW. BHE does not
require latching. BHE is three-stated with a pullup during bus-hold and reset
conditions.
WLB and WHB implement the functionality of BHE and AD0 for high and low byte
write enables, and they have timing appropriate for use with the nonmultiplexed
bus interface.
BHE also signals DRAM refresh cycles when using the multiplexed address and
data (AD) bus. A refresh cycle is indicated when both BHE and AD0 are High.
During refresh cycles, the AD bus is driven during the t1 phase and three-stated
during the t2, t3, and t4 phases. The value driven on the A bus is undefined during
a refresh cycle. For this reason, the A0 signal cannot be used in place of the AD0
signal to determine refresh cycles.
—
BSIZE8
DEN
[DS]
[PIO30]
[DRQ0]
PIO9
DRQ1
[DS]
—
DEN
[PIO30]
O
Bus Size 8 is asserted during t1–t4 to indicate an 8-bit cycle, or is deasserted to
indicate a 16-bit cycle.
O
Data Enable supplies an output enable to an external data-bus transceiver. DEN
is asserted during memory and I/O cycles. DEN is deasserted when DT/R
changes state. DEN is three-stated with a pullup during bus-hold or reset
conditions.
STI
DMA Requests 0 and 1 indicate to the microcontroller that an external device is
ready for a DMA channel to perform a transfer. DRQ1–[DRQ0] are leveltriggered and internally synchronized. DRQ1–[DRQ0] are not latched and must
remain active until serviced.
STI
O
Data Strobe provides a signal where the write cycle timing is identical to the read
cycle timing. When used with other control signals, [DS] provides an interface for
68K-type peripherals without the need for additional system interface logic.
When [DS] is asserted, addresses are valid. When [DS] is asserted on writes,
data is valid. When [DS] is asserted on reads, data can be driven on the AD bus.
Following a reset, this pin is configured as DEN. The pin is then configured by
software to operate as [DS].
DT/R
14
[PIO29]
O
Data Transmit or Receive indicates which direction data should flow through an
external data-bus transceiver. When DT/R is asserted High, the microcontroller
transmits data. When this pin is deasserted Low, the microcontroller receives
data. DT/R is three-stated with a pullup during a bus-hold or reset condition.
Am186™CH HDLC Microcontroller Data Sheet
Table 4. Signal Descriptions (Continued)
Signal Name
Multiplexed
Signal(s)
HLDA
{CLKSEL1}
Type Description
O
Bus-Hold Acknowledge is asserted to indicate to an external bus master that
the microcontroller has relinquished control of the local bus. When an external
bus master requests control of the local bus (by asserting HOLD), the
microcontroller completes the bus cycle in progress, then relinquishes control of
the bus to the external bus master by asserting HLDA and three-stating S2–S0,
AD15–AD0, S6, and A19–A0. The following are also three-stated and have
pullups: UCS, LCS, MCS3–MCS0, PCS7–PCS0, DEN, RD, WR, BHE, WHB,
WLB, and DT/R. ALE is three-stated and has a pulldown.
When the external bus master has finished using the local bus, it indicates this
to the microcontroller by deasserting HOLD. The microcontroller responds by
deasserting HLDA.
If the microcontroller requires access to the bus (for example, for refresh), the
microcontroller deasserts HLDA before the external bus master deasserts
HOLD. The external bus master must be able to deassert HOLD and allow the
microcontroller access to the bus. See the timing diagrams for bus hold on
page 59.
HOLD
—
STI
Bus-Hold Request indicates to the microcontroller that an external bus master
needs control of the local bus.
The microcontroller HOLD latency time—the time between HOLD request and
HOLD acknowledge—is a function of the activity occurring in the processor
when the HOLD request is received. A HOLD request is second only to DRAM
refresh requests in priority of activity requests received by the processor. This
implies that if a HOLD request is received just as a DMA transfer begins, the
HOLD latency can be as great as four bus cycles. This occurs if a DMA word
transfer operation is taking place from an odd address to an odd address. This
is a total of 16 clock cycles or more if wait states are required. In addition, if
locked transfers are performed, the HOLD latency time is increased by the
length of the locked transfer. HOLD latency is also potentially increased by
DRAM refreshes.
The board designer is responsible for properly terminating the HOLD input.
For more information, see the HLDA pin description above.
RD
—
O
Read Strobe indicates to the system that the microcontroller is performing a
memory or I/O read cycle. RD is guaranteed not to be asserted before the
address and data bus is three-stated during the address-to-data transition. RD
is three-stated with a pullup during bus-hold or reset conditions.
Am186™CH HDLC Microcontroller Data Sheet
15
Table 4. Signal Descriptions (Continued)
Signal Name
Multiplexed
Signal(s)
S0
—
S1
—
S2
—
Type Description
O
Bus Cycle Status 2–0 indicate to the system the type of bus cycle in progress.
S2 can be used as a logical memory or I/O indicator, and S1 can be used as a
data transmit or receive indicator. S2–S0 are three-stated during bus hold and
three-stated with a pullup during reset. The S2–S0 pins are encoded as follows:
Bus Status Pins
S6
SRDY
—
[PIO35]
S2
S1
S0
Bus Cycle
0
0
0
Reserved
0
0
1
Read data from I/O
0
1
0
Write data to I/O
0
1
1
Halt
1
0
0
Instruction fetch
1
0
1
Read data from memory
1
1
0
Write data to memory
1
1
1
None (passive)
O
Bus Cycle Status Bit 6: This signal is asserted during t 1–t4 to indicate a DMAinitiated bus cycle or a refresh cycle. S6 is three-stated during bus hold and
three-stated with a pulldown during reset.
STI
Synchronous Ready indicates to the microcontroller that the addressed
memory space or I/O device will complete a data transfer. The SRDY pin accepts
an active High input synchronized to CLKOUT.
Using SRDY instead of ARDY allows a relaxed system timing because of the
elimination of the one-half clock period required to internally synchronize ARDY.
To always assert the ready condition to the microcontroller, tie SRDY High. If the
system does not use SRDY, tie the pin Low to yield control to ARDY.
WHB
—
O
WLB
—
O
Write High Byte and Write Low Byte indicate to the system which bytes of the
data bus (upper, lower, or both) participate in a write cycle. In 80C186
microcontroller designs, this information is provided by BHE, AD0, and WR.
However, by using WHB and WLB, the standard system interface logic and
external address latch that were required are eliminated.
WHB is asserted with AD15–AD8. WHB is the logical AND of BHE and WR. This
pin is three-stated with a pullup during bus-hold or reset conditions.
WLB is asserted with AD7–AD0. WLB is the logical AND of AD0 and WR. This
pin is three-stated with a pullup during bus-hold or reset conditions.
WR
16
[PIO15]
O
Write Strobe indicates to the system that the data on the bus is to be written to
a memory or I/O device. WR is three-stated with a pullup during bus-hold or reset
conditions.
Am186™CH HDLC Microcontroller Data Sheet
Table 4. Signal Descriptions (Continued)
Signal Name
Multiplexed
Signal(s)
Type Description
CLOCKS/RESET/WATCHDOG TIMER
CLKOUT
—
O
Clock Output supplies the clock to the system. Depending on the values of the
CPU mode select pinstraps, {CLKSEL1} and {CLKSEL2}, CLKOUT operates at
either the PLL frequency or the source input frequency during PLL Bypass
mode. (See Table 26, “Reset Configuration Pins (Pinstraps),” on page A-7.)
CLKOUT remains active during bus-hold or reset conditions.
The DISCLK bit in the SYSCON register can be set to disable the CLKOUT
signal. Refer to the Am186™CC/CH/CU Microcontrollers Register Set Manual,
order #21916.
All synchronous AC timing specifications not associated with SSI, HDLCs, and
UARTs are synchronous to CLKOUT.
—
RES
STI
Reset requires the microcontroller to perform a reset. When RES is asserted,
the microcontroller immediately terminates its present activity, clears its internal
logic, and on the deassertion of RES, transfers CPU control to the reset address
FFFF0h.
RES must be asserted for at least 1 ms to allow the internal circuits to stabilize.
RES can be asserted asynchronously to CLKOUT because RES is synchronized
internally. For proper initialization, VCC must be within specifications, and
CLKOUT must be stable for more than four CLKOUT periods during which RES
is asserted.
If RES is asserted while the watchdog timer is performing a watchdog-timer reset,
the external reset takes precedence over the watchdog-timer reset. This means
that the RESOUT signal asserts as with any external reset and the WDTCON
register will not have the RSTFLAG bit set. In addition, the microcontroller will exit
reset based on the external reset timing (i.e., 4.5 clocks after the deassertion of
RES rather than 216 clocks after the watchdog timer timeout occurred).
The microcontroller begins fetching instructions approximately 6.5 CLKOUT
periods after RES is deasserted. This input is provided with a Schmitt trigger to
facilitate power-on RES generation via a resistor-capacitor (RC) network.
RESOUT
—
O
Reset Out indicates that the microcontroller is being reset (either externally or
internally), and the signal can be used as a system reset to reset any external
peripherals connected to RESOUT.
During an external reset, RESOUT remains active (High) for two clocks after
RES is deasserted. The microcontroller exits reset and begins the first valid bus
cycle approximately 4.5 clocks after RES is deasserted.
[UCLK]
PIO21
STI
UART Clock can be used instead of the processor clock as the source clock for
either the UART or the High-Speed UART. The source clock for the UART and
the High-Speed UART are selected independently and both can use the same
source.
CPU Crystal Input (X1) and CPU Crystal Output (X2) provide connections for
a fundamental mode, parallel-resonant crystal used by the internal oscillator
circuit. If an external oscillator is used, inject the signal directly into X1 and leave
X2 floating.
X1
—
STI
X2
—
O
Am186™CH HDLC Microcontroller Data Sheet
17
Table 4. Signal Descriptions (Continued)
Signal Name
Multiplexed
Signal(s)
Type Description
PINSTRAPS (See Table 26, “Reset Configuration Pins (Pinstraps),” on page A-7.)
RESERVED
RSVD_101
—
RSVD_102
—
RSVD_103
—
RSVD_104
—
RSVD_75
—
RSVD_76
—
RSVD_80
—
RSVD_81
—
The pins RSVD_104–RSVD_101, RSVD_75, RSVD_76, RSVD_80, and
RSVD_81 are reserved.
The RSVD_75 pin should be tied externally to VSS. All other seven reserved pins
should not be connected.
POWER AND GROUND
VCC (16)
—
STI
Digital Power Supply pins supply power (+3.3 ± 0.3 V) to the Am186CH HDLC
microcontroller logic.
VCC _A (1)
—
STI
Analog Power Supply pin supplies power (+3.3 ± 0.3 V) to the oscillators and
PLLs.
VSS (16)
—
STI
Digital Ground pins connect the Am186CH HDLC microcontroller logic to the
system ground.
VSS _A (1)
—
STI
Analog Ground pin connects the oscillators and PLLs to the system ground.
QS0
—
O
QS1
—
O
Queue Status 1–0 values provide information to the system concerning the
interaction of the CPU and the instruction queue. The pins have the following
meanings:
DEBUG SUPPORT
Queue Status Pins
QS1 QS0 Queue Operation
0
0
None
0
1
First opcode byte fetched from queue
1
0
Queue was initialized
1
1
Subsequent byte fetched from queue
The following signals are also used by emulators: A19–A0, AD15–AD0, {ADEN}, ALE, ARDY, BHE, BSIZE8, CAS1–CAS0,
CLKOUT, {CLKSEL2–CLKSEL1}, HLDA, HOLD, LCS, MCS3–MCS0, NMI, {ONCE}, QS1–QS0, RAS1–RAS0, RD, RES,
RESOUT, S2–S0, S6, SRDY, UCS, {UCSX8}, WHB, WLB, WR. See the Am186CC/CH/CU Microcontrollers User’s Manual,
order #21914, for more information.
18
Am186™CH HDLC Microcontroller Data Sheet
Table 4. Signal Descriptions (Continued)
Signal Name
Multiplexed
Signal(s)
Type Description
CHIP SELECTS
LCS
[RAS0]
O
Lower Memory Chip Select indicates to the system that a memory access is in
progress to the lower memory block. The base address and size of the lower
memory block are programmable up to 512 Kbyte. LCS can be configured for 8bit or 16-bit bus size. LCS is three-stated with a pullup resistor during bus-hold
or reset conditions.
[MCS0]
{UCSX8}
PIO4
O
MCS1
[CAS1]
MCS2
[CAS0]
Midrange Memory Chip Selects 3–0 indicate to the system that a memory
access is in progress to the corresponding region of the midrange memory block.
The base address and size of the midrange memory block are programmable.
The midrange chip selects can be configured for 8-bit or 16-bit bus size. The
midrange chip selects are three-stated with pullup resistors during bus-hold or
reset conditions.
[MCS3]
[RAS1]
PIO5
[MCS0] can be programmed as the chip select for the entire middle chip select
address range.
Unlike the UCS and LCS chip selects that operate relative to the earlier timing of
the nonmultiplexed A address bus, the MCS outputs assert with the multiplexed
AD address and data bus timing.
PCS0
[PIO13]
PCS1
[PIO14]
O
PCS2
—
PCS3
—
[PCS4]
PIO3
{CLKSEL2}
[PCS5]
PIO2
[PCS6]
PIO32
[PCS7]
PIO31
UCS
{ONCE}
Peripheral Chip Selects 7–0 indicate to the system that an access is in
progress to the corresponding region of the peripheral address block (either I/O
or memory address space). The base address of the peripheral address block is
programmable. PCS7–PCS0 are three-stated with pullup resistors during bushold or reset conditions.
Unlike the UCS and LCS chip selects that operate relative to the earlier timing of
the nonmultiplexed A address bus, the PCS outputs assert with the multiplexed
AD address and data bus timing.
O
Upper Memory Chip Select indicates to the system that a memory access is in
progress to the upper memory block. The base address and size of the upper
memory block are programmable up to 512 Kbytes. UCS is three-stated with a
weak pullup during bus-hold or reset conditions.
The UCS can be configured for an 8-bit or 16-bit bus size out of reset. For
additional information, see the {UCSX8} pin description in Table 26, “Reset
Configuration Pins (Pinstraps),” on page A-7.
After reset, UCS is active for the 64-Kbyte memory range from F0000h to FFFFFh,
including the reset address of FFFF0h.
DRAM
[CAS0]
MCS2
O
Column Address Strobes 1–0: When either the upper or lower chip select
regions are configured for DRAM, these pins provide the column address strobe
signals to the DRAM. The CAS signals can be used to perform byte writes in a
manner similar to WLB and WHB, respectively (i.e., [CAS0] corresponds to the
low byte (WLB) and [CAS1] corresponds to the high byte (WHB)).
[CAS1]
MCS1
[RAS0]
LCS
O
Row Address Strobe 0: When the lower chip select region is configured to
DRAM, this pin provides the row address strobe signal to the lower DRAM bank.
[RAS1]
[MCS3]
PIO5
O
Row Address Strobe 1: When the upper chip select region is configured to
DRAM, this pin provides the row address strobe signal to the upper DRAM bank.
Am186™CH HDLC Microcontroller Data Sheet
19
Table 4. Signal Descriptions (Continued)
Signal Name
Multiplexed
Signal(s)
Type Description
INTERRUPTS
NMI
—
STI
Nonmaskable Interrupt indicates to the microcontroller that an interrupt request
has occurred. The NMI signal is the highest priority hardware interrupt and cannot
be masked. The microcontroller always transfers program execution to the
location specified by the nonmaskable interrupt vector in the microcontroller’s
interrupt vector table when NMI is asserted.
Although NMI is the highest priority hardware interrupt source, it does not
participate in the priority resolution process of the maskable interrupts. There is
no bit associated with NMI in the interrupt in-service or interrupt request
registers. This means that a new NMI request can interrupt an executing NMI
interrupt service routine. As with all hardware interrupts, the interrupt flag (IF) is
cleared when the processor takes the interrupt, disabling the maskable interrupt
sources. However, if maskable interrupts are re-enabled by software in the NMI
interrupt service routine (for example, via the STI instruction), the fact that an
NMI is currently in service does not have any effect on the priority resolution of
maskable interrupt requests. For this reason, it is strongly advised that the
interrupt service routine for NMI should not enable the maskable interrupts.
An NMI transition from Low to High is latched and synchronized internally, and it
initiates the interrupt at the next instruction boundary. To guarantee that the interrupt
is recognized, the NMI pin must be asserted for at least one CLKOUT period.
The board designer is responsible for properly terminating the NMI input.
—
INT5–INT0
STI
[INT6]
PIO19
STI
[INT7]
PIO7
STI
[INT8]
[PWD]
PIO6
STI
Maskable Interrupt Requests 8–0 indicate to the microcontroller that an
external interrupt request has occurred. If the individual pin is not masked, the
microcontroller transfers program execution to the location specified by the
associated interrupt vector in the microcontroller’s interrupt vector table.
Interrupt requests are synchronized internally and can be edge-triggered or
level-triggered. The interrupt polarity is programmable.To guarantee interrupt
recognition for edge-triggered interrupts, the user should hold the interrupt
source for a minimum of five system clocks. A second interrupt from the same
source is not recognized until after an acknowledge of the first.
The board designer is responsible for properly terminating the INT8–INT0 inputs.
Also configurable as interrupts are PIO5, PIO15, PIO27, PIO29, PIO30, PIO33, PIO34, and PIO35.
(See the Am186CC/CH/CU Microcontrollers User’s Manual, order #21914 for more information.)
20
Am186™CH HDLC Microcontroller Data Sheet
Table 4. Signal Descriptions (Continued)
Signal Name
Multiplexed
Signal(s)
Type Description
PROGRAMMABLE I/O (PIOS)
PIO47–PIO0
(For multiplexed
signals see Table
27, “PIOs Sorted
by PIO Number,”
on page A-8 and
Table 28, “PIOs
Sorted by Signal
Name,” on page
A-9.)
B
Shared Programmable I/O pins can be programmed with the following
attributes: PIO function (enabled/disabled), direction (input/output), and weak
pullup or pulldown.
After a reset, the PIO pins default to various configurations. The column entitled
“Pin Configuration Following System Reset” in Table 27 on page A-8 and
Table 28 on page A-9 lists the defaults for the PIOs. Most of the PIO pins are
configured as PIO inputs with pullup after reset. See Table 30 on page A-11 for
detailed termination information for all pins. The system initialization code must
reconfigure any PIO pins as required.
PIO5, PIO15, PIO27, PIO29, PIO30, and PIO33–PIO35 are capable of
generating an interrupt on the shared interrupt channel 14.
The multiplexed signals PIO33/ALE, PIO8/ARDY, PIO34/BHE, PIO30/DEN,
PIO29/DT/R, PIO14/PCS1–PIO13/PCS0, PIO35/SRDY, and PIO15/WR default
to non-PIO operation at reset.
The following PIO signals are multiplexed with alternate signals that can be used
by emulators: PIO8, PIO15, PIO33, PIO34, and PIO35. Consider any emulator
requirements for the alternate signals before using these pins as PIOs.
PROGRAMMABLE TIMERS
[PWD]
[INT8]
PIO6
STI
Pulse-Width Demodulator: If pulse-width demodulation is enabled, [PWD]
processes a signal through the Schmitt trigger input. [PWD] is used internally to
drive [TMRIN0] and [INT8], and [PWD] is inverted internally to drive [TMRIN1]
and an additional internal interrupt. If interrupts are enabled and Timer 0 and
Timer 1 are properly configured, the pulse width of the alternating [PWD] signal
can be calculated by comparing the values in Timer 0 and Timer 1.
In PWD mode, the signals [TMRIN0]/PIO27 and [TMRIN1]/PIO0 can be used as
PIOs. If they are not used as PIOs they are ignored internally.
The additional internal interrupt used in PWD mode uses the same interrupt
channel as [INT7]. If [INT7] is used, it must be assigned to the shared interrupt
channel.
[TMRIN0]
PIO27
STI
[TMRIN1]
PIO0
STI
Timer Inputs 1–0 supply a clock or control signal to the internal microcontroller
timers. After internally synchronizing a Low-to-High transition on [TMRIN1]–
[TMRIN0], the microcontroller increments the timer. [TMRIN1]–[TMRIN0] must
be tied High if not being used. When PIO is enabled for one or both, the pin is
pulled High internally.
[TMRIN1]–[TMRIN0] are driven internally by [INT8]/[PWD] when pulse-width
demodulation functionality is enabled. The [TMRIN1]–[TMRIN0] pins can be
used as PIOs when pulse-width demodulation is enabled.
[TMROUT0]
PIO28
O
[TMROUT1]
PIO1
O
Timer Outputs 1–0 supply the system with either a single pulse or a continuous
waveform with a programmable duty cycle. [TMROUT1]–[TMROUT0] are threestated during bus-hold or reset conditions.
ASYNCHRONOUS SERIAL PORTS (UART AND HIGH-SPEED UART)
UART
[RXD_U]
PIO26
STI
[TXD_U]
PIO20
O
Receive Data UART is the asynchronous serial receive data signal that supplies
data from the asynchronous serial port to the microcontroller.
Transmit Data UART is the asynchronous serial transmit data signal that
supplies data to the asynchronous serial port from the microcontroller.
Am186™CH HDLC Microcontroller Data Sheet
21
Table 4. Signal Descriptions (Continued)
Signal Name
Multiplexed
Signal(s)
[CTS_U]
PIO24
STI
Clear-To-Send UART provides the Clear-to-Send signal from the asynchronous
serial port when hardware flow control is enabled for the port. The [CTS_U]
signal gates the transmission of data from the serial port transmit shift register.
When [CTS_U] is asserted, the transmitter begins transmission of a frame of
data, if any is available. If [CTS_U] is deasserted, the transmitter holds the data
in the serial port transmit shift register. The value of [CTS_U] is checked only at
the beginning of the transmission of the frame. [CTS_U] and [RTR_U] form the
hardware handshaking interface for the UART.
[RTR_U]
PIO25
O
Ready-To-Receive UART provides the Ready-to-Receive signal for the
asynchronous serial port when hardware flow control is enabled for the port. The
[RTR_U] signal is asserted when the associated serial port receive data register
does not contain valid, unread data. [CTS_U] and [RTR_U] form the hardware
handshaking interface for the UART.
STI
Receive Data High-Speed UART is the asynchronous serial receive data signal
that supplies data from the high-speed serial port to the microcontroller.
O
Transmit Data High-Speed UART is the asynchronous serial transmit data
signal that supplies data to the high-speed serial port from the microcontroller.
Type Description
HIGH-SPEED UART
[RXD_HU]
PIO16
TXD_HU
—
[CTS_HU]
PIO46
STI
Clear-To-Send High-Speed UART provides the Clear-to-Send signal from the
high-speed asynchronous serial port when hardware flow control is enabled for
the port. The [CTS_HU] signal gates the transmission of data from the serial port
transmit shift register. When [CTS_HU] is asserted, the transmitter begins
transmission of a frame of data, if any is available. If [CTS_HU] is deasserted,
the transmitter holds the data in the serial port transmit shift register. The value
of [CTS_HU] is checked only at the beginning of the transmission of the frame.
[CTS_HU] and [RTR_HU] form the hardware handshaking interface for the HighSpeed UART.
[RTR_HU]
PIO47
O
Ready-To-Receive High-Speed UART provides the Ready-to-Receive signal to
the high-speed asynchronous serial port when hardware flow control is enabled
for the port. The [RTR_HU] signal is asserted when the associated serial port
receive data register does not contain valid, unread data. [CTS_HU] and
[RTR_HU] form the hardware handshaking interface for the High-Speed UART.
SYNCHRONOUS SERIAL INTERFACE (SSI)
[SCLK]
PIO11
O
Serial Clock provides the clock for the synchronous serial interface to allow
synchronous transfers between the microcontroller and a slave device.
[SDATA]
PIO12
B
Serial Data is used to transmit and receive data between the microcontroller and
a slave device on the synchronous serial interface.
[SDEN]
PIO10
O
Serial Data Enable enables data transfers on the synchronous serial interface.
HIGH-LEVEL DATA LINK CONTROL SYNCHRONOUS COMMUNICATION INTERFACES
HDLC Channel A (DCE)
DCE_RXD_A
[PCM_RXD_A]
DCE_TXD_A
[PCM_TXD_A]
DCE_RCLK_A
[PCM_CLK_A]
STI
DCE Receive Data Channel A is the serial data input pin for the channel A DCE
interface.
OD-O DCE Transmit Data Channel A is the serial data output pin for the channel A
DCE interface.
STI
DCE Receive Clock Channel A provides the receive clock to the channel A
DCE interface. If the same clock is to be used for both transmit and receive, then
this pin should be tied to the DCE_TCLK_A pin externally.
The DCE function is the default at reset, so the board designer is responsible for
properly terminating the DCE_RCLK_A input.
22
Am186™CH HDLC Microcontroller Data Sheet
Table 4. Signal Descriptions (Continued)
Signal Name
Multiplexed
Signal(s)
DCE_TCLK_A
[PCM_FSC_A]
Type Description
STI
DCE Transmit Clock Channel A provides the transmit clock to the channel A
DCE interface. If the same clock is to be used for both transmit and receive, then
this pin should be tied to the DCE_RCLK_A pin externally.
The DCE function is the default at reset, so the board designer is responsible for
properly terminating the DCE_TCLK_A input.
[DCE_CTS_A]
[PCM_TSC_A]
PIO17
[DCE_RTR_A]
PIO18
STI
DCE Clear-To-Send Channel A indicates to the channel A DCE interface that
an external serial interface is ready to receive data. [DCE_CTS_A] and
[DCE_RTR_A] provide the handshaking for the channel A DCE interface.
O
DCE Ready-to-Receive Channel A indicates to an external serial interface that
the internal channel A DCE interface is ready to accept data. [DCE_CTS_A] and
[DCE_RTR_A] provide the handshaking for the channel A DCE interface.
HDLC Channel B (DCE)
[DCE_RXD_B]
[PCM_RXD_B]
PIO36
STI
DCE Receive Data Channel B is the serial data input pin for the channel B DCE
interface.
[DCE_TXD_B]
[PCM_TXD_B]
PIO37
OD-O
DCE Transmit Data Channel B is the serial data output pin for the channel B
DCE interface.
[DCE_RCLK_B] [PCM_CLK_B]
PIO40
STI
DCE Receive Clock Channel B provides the receive clock to the channel B
DCE interface. If the same clock is to be used for both transmit and receive, this
pin should be tied to the [DCE_TCLK_B] pin externally.
[DCE_TCLK_B]
[PCM_FSC_B]
PIO41
STI
DCE Transmit Clock Channel B provides the transmit clock to the channel B
DCE interface. If the same clock is to be used for both transmit and receive, this
pin should be tied to the [DCE_RCLK_B] pin externally.
[DCE_CTS_B]
[PCM_TSC_B]
PIO38
STI
DCE Clear-To-Send Channel B indicates to the channel B DCE interface that
an external serial interface is ready to receive data. [DCE_CTS_B] and
[DCE_RTR_B] provide the handshaking for the channel B DCE interface.
[DCE_RTR_B]
PIO39
O
DCE Ready-to-Receive Channel B indicates to an external serial interface that
the internal channel B DCE interface is ready to accept data. [DCE_CTS_B] and
[DCE_RTR_B] provide the handshaking for the channel B DCE interface.
HDLC Channel A (PCM)
[PCM_RXD_A]
DCE_RXD_A
STI
PCM Receive Data Channel A is the serial data input pin for the channel A PCM
Highway interface.
[PCM_TXD_A]
DCE_TXD_A
O-LSOD
PCM Transmit Data Channel A is the serial data output pin for the channel A
PCM Highway interface.
[PCM_CLK_A]
DCE_RCLK_A
STI
PCM Clock is the single transmit and receive data clock pin for the channel A
PCM Highway interface.
[PCM_FSC_A]
DCE_TCLK_A
STI
PCM Frame Synchronization Clock provides the Frame Synchronization
Clock input (usually 8 kHz) for the channel A PCM Highway interface.
[PCM_TSC_A]
[DCE_CTS_A]
PIO17
OD
PCM Time Slot Control A enables an external buffer device when channel A PCM
Highway data is present on the [PCM_TXD_A] output pin in PCM Highway mode.
HDLC Channel B (PCM)
[PCM_RXD_B]
[DCE_RXD_B]
PIO36
STI
PCM Receive Data Channel B is the serial data input pin for the channel B PCM
Highway interface.
[PCM_TXD_B]
[DCE_TXD_B]
PIO37
O-LSOD
PCM Transmit Data Channel B is the serial data output pin for the channel B
PCM Highway interface.
[PCM_CLK_B]
[DCE_RCLK_B]
PIO40
STI
PCM Clock is the single transmit and receive data clock pin for the channel B
PCM Highway interface.
[PCM_FSC_B]
[DCE_TCLK_B]
PIO41
STI
PCM Frame Synchronization Clock provides the Frame Synchronization
Clock input (usually 8 kHz) for the channel B PCM Highway interface.
[PCM_TSC_B]
[DCE_CTS_B]
PIO38
OD
PCM Time Slot Control B enables an external buffer device when channel B PCM
Highway data is present on the [PCM_TXD_B] output pin in PCM Highway mode.
Am186™CH HDLC Microcontroller Data Sheet
23
ARCHITECTURAL OVERVIEW
The architectural goal of the Am186CH HDLC
m i c r o c on t r o l l e r i s to p r ov i d e c o m pr e h e n s i ve
communications features on a processor running the
widely known x86 instruction set. The Am186CH HDLC
microcontroller combines two HDLC channels and
general communications peripherals with the Am186
microcontroller. This highly integrated microcontroller
provides system cost and performance advantages for
a wide range of communications applications. Figure 1
is a block diagram of the Am186CH HDLC
microcontroller followed by sections providing an
overview of the features.
Serial Communications Peripherals
Am186
CPU
Chip
Selects
(14)
PIOs
(48)
Watchdog
Timer
Interrupt
Controller
(17 Ext.
Sources)
UART
High-Speed
UART with
Autobaud
Synchronous
Serial
Interface (SSI)
Physical
Interface
Glueless
Interface
to RAM/ROM
DRAM
Controller
Memory Peripherals
Timers
(3)
SmartDMA
Channels
(4)
GeneralPurpose
DMA (4)
HDLC
TSA
System Peripherals
Raw DCE
Muxing
HDLC
PCM
Highway
TSA
Figure 1. Am186CH Microcontroller Block Diagram
Detailed Description
■ Two independent High-level Data Link Control
(HDLC) channels support a wide range of
external interfaces
– External interface connection for HDLCs can be
PCM Highway or raw DCE
– Data rate of up to 10 Mbit/s
– Receive and transmit FIFOs
– Support for HDLC, Synchronous Data Link
Control (SDLC), Line Access Procedure
Balanced (LAP-B), Line Access Procedure D
(LAP-D), Point-to-Point Protocol (PPP), and
v.120 (support of v.110 In transparent mode)
– Two dedicated buffer descriptor ring SmartDMA
channels per HDLC
– One independent time-slot assigner per HDLC
– Clear-to-Send/Ready-to-Receive (CTS/RTR)
hardware handshaking and auto-enable operation
– Collision detection for multidrop applications
– Transparency mode
– Address comparison on receive
– Flag or mark idle operation
24
■ Two independent Time Slot Assigners (TSAs)
provide flexible time slot allocation
– Allows isolation of Time Division Multiplexed (TDM)
time slot of choice from a variety of TDM carriers
– Up to 4096 sequential bits can be isolated
– TDM bus can have up to 512 8-bit time slots
– Start bit and stop bit times identify isolated
portion of TDM frame
– 12-bit counters define the start/stop bit times as
the number of bits after frame synchronization
– Entire frame down to 1 bit per frame can be isolated
■ 8 Direct Memory Access (DMA) channels
– Four buffer descriptor ring SmartDMA channels
for the two HDLC channels
– Four general-purpose DMAs support the two
integrated asynchronous serial ports; two DMA
channels have external DMA request inputs
Am186™CH HDLC Microcontroller Data Sheet
■ High-speed asynchronous serial interface
provides enhanced UART functions
– Independent baud generator with clock input
source programmable to use CPU or external
clock input pin
■ Synchronous Serial Interface (SSI) provides
half-duplex, bidirectional interface to highspeed peripherals
–
–
–
–
–
Capable of sustained operation at 460 Kbaud
7-, 8-, or 9-bit data transfers
FIFOs to support high-speed operation
DMA support available
Automatic baud-rate detection that allows
emulation of a Hayes AT-compatible modem
– Independent baud generator with clock input
source programmable to use CPU or external
clock input pin
■ Asynchronous serial interface (UART)
– Useful with many telecommunication interface
peripherals such as codecs, line interface units,
and transceivers
– Selectable device-select polarity
– Selectable bit shift order on transmit and receive
– Glueless connection to AMD Subscriber Line
Audio Processing Circuit (SLAC™) devices
■ Clocking options offer high flexibility
– 7-, 8-, or 9-bit data transfers
– DMA support available
– CPU can run in 1x, 2x, or 4x mode
Am186™ Embedded CPU
and adding the 16-bit offset value to yield a 20-bit
physical address (see Figure 2). This allows for a
1-Mbyte physical address size.
All members of the Am186 family, including the
Am186CH HDLC microcontroller, are compatible with
the original industry-standard 186 parts, and build on
the same core set of 186 registers, address generation,
I/O space, instruction set, segments, data types, and
addressing modes.
All instructions that address operands in memory must
specify the segment value and the 16-bit offset value.
For speed and compact instruction encoding, the
segment register used for physical address generation
is implied by the addressing mode used (see Table 5
on page 26).
Memory Organization
Memory is organized in sets of segments. Each
segment is a linear contiguous sequence of 64K (216)
8-bit bytes. Memor y is addressed using a twocomponent address consisting of a 16-bit segment
value and a 16-bit offset. The 16-bit segment values
are contained in one of four internal segment registers
(CS, DS, SS, or ES). The physical address is
calculated by shifting the segment value left by 4 bits
15
Shift
Left
4 Bits
1
19
1
2
A
2
A
4
Segment Base
Logical Address
0
0
2
2
Offset
0
0
0
0
2
19
1
4
0
15
0
The I/O space consists of 64K 8-bit or 32K 16-bit ports.
Separate instructions (IN/INS and OUT/OUTS)
address the I/O space with either an 8-bit port address
specified in the instruction, or a 16-bit port address in
the DX register. Eight-bit port addresses are zeroextended such that A15–A8 are Low.
0
15
0
I/O Space
2
0
2
A
6
2
Physical Address
To Memory
Figure 2.
Two-Component Address Example
Am186™CH HDLC Microcontroller Data Sheet
25
Table 5.
Memory Reference Needed
Instructions
Local Data
Stack
External Data (Global)
Segment Register Selection Rules
Segment Register Used Implicit Segment Selection Rule
Code (CS)
Instructions (including immediate data)
Data (DS)
All data references
All stack pushes and pops;
Stack (SS)
any memory references that use the BP register
Extra (ES)
All string instruction references that use the DI register as an index
Serial Communications Support
The Am186CH HDLC microcontroller supports five
serial interfaces. This includes two HDLC channels,
two UARTs, and a synchronous serial interface.
Two HDLC Channels and Two TSAs
The Am186CH HDLC microcontroller provides two
HDLC channels that support the HDLC, SDLC, LAP-B,
LAP-D, PPP, and v.120 protocols. The HDLC channels
can also be used in transparent mode to support v.110.
Each HDLC channel can connect to an external serial
interface directly (nonmultiplexed mode), or can pass
through a TSA (multiplexed mode). The flexible interface
multiplexing arrangement allows each HDLC channel to
have its own external raw DCE or PCM highway
interface, share a common PCM highway or other time
TDM bus with one or more channels, or work in some
combination.
Each HDLC channel’s independent TSA allows it to
extract a subset of data from a TDM bus. The entire
frame, or as little as 1 bit per frame, can be extracted.
Twelve-bit counters define the start/stop bit times as
the number of bits after frame synchronization. The
time slot can be an arbitrary number of bits up to 4096
bits. Start bit and stop bit times identify the isolated
portion of the TDM frame. Support of less than eight
bits per time slot, or bit slotting, allows isolation of from
one to eight bits in a single time slot. Each TDM bus
can have up to 512 8-bit time slots. Support of these
features allows interoperation with PCM highway, E1,
IOM-2, T1, and other TDM buses.
The HDLC channels have features that make the
Am186CH HDLC microcontroller an attractive device
for use where general HDLC capability is required.
T h e s e f e a t u r e s i n c l u d e C T S / RT R h a r d w a r e
handshaking and auto-enable operation, collision
detection for multidrop applications, transparency
mode, address comparison on receive, flag or mark
idle operation, two dedicated buffer descriptor ring
SmartDMA channels per HDLC, transmit and receive
FIFOs, and full-duplex data transfer. Each TSA
channel can support a burst data rate to/from the
HDLC of up to 10 Mbit/s in both raw DCE and PCM
Highway modes. Total system data throughput is highly
dependent on the amount of per-packet and per-byte
CPU processing, the rate at which packets are being
sent, and other CPU activity.
26
When combined with the TSAs, the HDLC channels
can be used in a wide variety of applications such as
P CM hi g h way, X . 2 5, Fra m e R e l ay, an d o t he r
proprietary Wide Area Network (WAN) connections.
Four SmartDMA™ Channels
The Am186CH HDLC microcontroller provides four
SmartDMA channels that provide a faster method for
moving data between peripherals and memory with
lower CPU utilization. Smar tDMA transmits and
receives data across multiple memory buffers and a
sophisticated buffer-chaining mechanism. These
channels are always used in pairs: transmitter and
receiver. The transmit channels can only transfer data
from memory to a peripheral; the receive channels can
only transfer data from a peripheral to memory.
The four channels (two pairs) are dedicated for use
with the two on-board HDLC channels.
In addition to the four Smar tDMA channels, the
Am186CH HDLC microcontroller provides four
general-purpose DMA channels (see page 27).
Two Asynchronous Serial Ports
The Am186CH HDLC microcontroller has two
asynchronous serial ports (a UART and a High-Speed
UART) that provide full-duplex, bidirectional data
transfer at speeds of up to 115.2 Kbaud or up to 460
Kbaud, respectively. The High-Speed UART has
16-byte transmit and 32-byte receive FIFOs, specialcharac ter matching, and automatic baud-rate
detection, suitable for implementation of a Hayescompatible modem interface to a host PC. There is
also a lower speed UART that typically is used for a low
baud-rate system configuration port or debug port.
Each of these UARTs can derive its baud rate from the
system clock or from a separate baud-rate generator
clock input. Both UARTs support 7-, 8-, or 9-bit data
transfers; address bit generation and detection in 7- or
8-bit frames; one or two stop bits; even, odd, or no
parity; break generation and detection; hardware flow
control; and DMA to and/or from the serial ports using
the general-purpose DMA channels.
Am186™CH HDLC Microcontroller Data Sheet
Synchronous Serial Port
The Am186CH HDLC microcontroller includes one SSI
por t that provides a half-duplex, bidirectional,
communications interface between the Am186CH
HDLC microcontroller and other system components.
This interface is typically used by the microcontroller to
monitor the status of other system devices and/or to
configure these devices under software control. In a
communications application, these devices could be
system components such as audio codecs, line
interface units, and transceivers. The SSI supports
data transfer speeds of up to 25 Mbit/s with a 50-MHz
system clock.
The SSI port operates as an interface master, with the
other attached devices acting as slave devices. Using
this protocol, the microcontroller sends a command byte
to the attached device, and then follows that with either
a read or write of a byte of data.
The SSI port consists of three I/O pins: an enable
(SDEN), a clock (SCLK), and a bidirectional data pin
(SDATA). SDEN can be used directly as an enable for
a single attached device. When more than one device
requires control via the SSI, PIOs can be used to
provide enable pins for those devices.
The Am186CH SSI is, in general, software compatible
with software written for the Am186EM SSI. (Additional
features have been added to the Am186CH SSI
implementation.) The Am186CH HDLC microcontroller
features the additional capability of selecting the
polarity of the SCLK and SDEN pins, as well as the shift
order of bits on the SDATA pin (least-significant-bit first
versus most-significant-bit first). The SSI port also
offers a programmable clock divisor (dividing the clock
from 2 to 256 in power of 2 increments), a bidirectional
transmit/receive shift register, and direct connection to
AMD SLAC devices.
interrupts. The 36 maskable interrupt sources include 19
internal sources and 17 external sources.
Four General-Purpose DMA Channels
The Am186CH HDLC microcontroller provides a total
of 12 DMA channels that can be used for data transfer
between memory and I/O spaces (i.e., memory-to-I/O
or I/O-to-memory) or within the same space (i.e.,
memory-to-memory or I/O-to-I/O). In addition, the
Am186CH HDLC microcontroller suppor ts data
transfer between peripherals and memory or I/O.
Internal peripherals that support general-purpose DMA
are Timer 2 and the two asynchronous serial ports
(UART and High-Speed UART). External peripherals
support DMA transfers through the external DMA
request pins. Each general-purpose channel can
accept synchronized DMA requests from one of three
sources: DMA request pins (DRQ1–DRQ0), Timer 2, or
the UARTs. In addition, system software can initialize
and start unsynchronized DMA transfers.
In addition to the four general-purpose channels, the
Am186CH HDLC microcontroller provides four
SmartDMA channels (see page 26).
48 Programmable I/O Signals
The Am186CH HDLC microcontroller provides 48
user-programmable input/output signals (PIOs). All but
six of the 48 signals share a pin with at least one
alternate function. If an application does not need the
alternate function, the associated PIO can be used by
programming the PIO registers.
System Peripherals
If a pin is enabled to function as a PIO signal, the
alternate function is disabled and does not affect the
pin. A PIO signal can be configured to operate as an
input or output, with or without internal pullup or
pulldown resistors (pullup or pulldown depends on the
pin configuration and is not user-configurable), or as an
open-drain output. Additionally, eight PIOs can be
configured as external interrupt sources.
Interrupt Controller
Three Programmable Timers
The Am186CH HDLC microcontroller features an
interrupt controller that arranges the 36 maskable
interrupt requests by priority and presents them one at
a time to the CPU. In addition to interrupts managed by
the i nte rr up t co ntr ol ler, the A m1 86CH HDL C
m i c r o c o n t r o l l e r s u p p or t s ei g h t n o n m a s k a bl e
interrupts—an external or internal nonmaskable
interrupt (NMI), a trace interrupt, and software
interrupts and exceptions.
There are three 16-bit programmable timers in the
Am186CH HDLC microcontroller. Timers 0 and 1 are
highly versatile and are each connected to two external
pins (each one has an input and an output). These two
timers can be used to count or time external events that
drive the timer input pins. Timers 0 and 1 can also be
used to generate nonrepetitive or variable-duty-cycle
waveforms on the timer output pins.
The interrupt controller supports the 36 maskable
interrupt sources through the use of 15 channels.
Because of this, most channels support multiple
interrupt sources. These channels are programmable to
support the external interrupt pins and/or various
peripheral devices that can be configured to generate
Timer 2 is not connected to any external pins. It can be
used by software to generate interrupts, or it can be
polled for real-time coding and time-delay applications.
Timer 2 can also be used as a prescaler to Timer 0 and
Timer 1, or as a DMA request source.
The source clock for Timer 2 is one-fourth of the
system clock frequency. The source clock for Timers 0
Am186™CH HDLC Microcontroller Data Sheet
27
and 1 can be configured to be one-fourth of the system
clock, or they can be driven from their respective timer
input pins. When driven from a timer input pin, the timer
is counting the “event” of an input transition.
The Am186CH HDLC microcontroller also provides a
pulse width demodulation (PWD) option so that a
toggling input signal’s Low state and High state
durations can be measured.
Hardware Watchdog Timer
The Am186CH HDLC microcontroller provides a fullfeatured watchdog timer, which includes the ability to
generate Non-Maskable Interrupts (NMIs), microcontroller
resets, and system resets when the timeout value is
reached. The timeout value is programmable and ranges
from 210 to 226 processor clocks.
The watchdog timer is used to regain control when a
system has failed due to a software error or to failure of
an external device to respond in the expected way.
Software errors can sometimes be resolved by
recapturing control of the execution sequence via a
watchdog-timer-generated NMI. When an external
device fails to respond, or responds incorrectly, it may be
necessary to reset the controller or the entire system,
including external devices. The watchdog timer provides
the flexibility to support both NMI and reset generation.
Memory and Peripheral Interface
System Interfaces
The Am186CH HDLC microcontroller bus interface
controls all accesses to the peripheral control block
(PCB), memory-mapped and I/O-mapped external
peripherals, and memory devices. Internal peripherals
are accessed by the bus interface through the PCB.
The bus interface features programmable bus sizing;
individually selectable chip selects for the upper (UCS)
memory space, lower (LCS) memory space, all non-UCS,
non-LCS and I/O memory spaces; separate byte-write
enables; and, boot option from an 8- or 16-bit device.
The integrated peripherals are controlled by 16-bit
read/write registers. The peripheral registers are
contained within an internal 1-Kbyte control block. At
reset, the base of the PCB is set to FC00h in I/O space.
The registers are physically located in the peripheral
devices they control, but they are addressed as a
single 1-Kbyte block. For details on the PCB registers,
refer to the Am186™CC/CH/CU Microcontrollers
Register Set Manual, order #21916.
Accesses to the PCB should be performed by direct
processor actions. The use of DMA to write or read
from the PCB results in unpredictable behavior, except
where explicit exception is made to suppor t a
peripheral function, such as the High-Speed UART
transmit and receive data registers.
28
The 80C186 and 80C188 microcontrollers use a
multiplexed address and data (AD) bus. The address is
present on the AD bus only during the t1 clock phase.
The Am186CH HDLC microcontroller continues to
provide the multiplexed AD bus and, in addition,
provide a nonmultiplexed address (A) bus. The A bus
provides an address to the system for the complete bus
cycle (t 1 –t 4 ). During refresh cycles, the AD bus is
driven during the t1 phase and the values are unknown
during the t2, t3, and t4 phases. The value driven on the
A bus is undefined during a refresh cycle.
The nonmultiplexed address bus (A19–A0) is valid
one-half CLKOUT cycle in advance of the address on
the AD bus. When used with the modified UCS and
LCS outputs and the byte write enable signals, the
A19–A0 bus provides a seamless interface to SRAM,
DRAM, and Flash/EPROM memory systems.
For systems where power consumption is a concern, it
is possible to disable the address from being driven on
the AD bus on the Am186CH HDLC microcontroller
during the normal address portion of the bus cycle for
accesses to upper (UCS) and/or lower (LCS) address
spaces. In this mode, the affected bus is placed in a
high-impedance state during the address portion of the
bus cycle. This feature is enabled through the DA bits
in the Upper Memory Chip Select (UMCS) and Lower
Memory Chip Select (LMCS) registers.
When address disable is in effect, the number of
signals that assert on the bus during all normal bus
cycles to the associated address space is reduced,
thus decreasing power consumption, reducing
processor switching noise, and preventing bus
contention with memory devices and peripherals when
operating at high clock rates.
If the ADEN pin is asserted during processor reset, the
value of the DA bits in the UMCS and LMCS registers is
ignored and the address is driven on the AD bus for all
accesses, thus preserving the industry-standard
80C186 and 80C188 microcontrollers’ multiplexed
address bus and providing suppor t for existing
emulation tools. For details on these registers, refer to
the Am186™CC/CH/CU Microcontrollers Register Set
Manual, order #21916.
Figure 3 on page 29 shows the affected signals during
a normal read or write operation. The address and data
are multiplexed onto the AD bus.
Figure 4 on page 29 shows a bus cycle when address
bus disable is in effect, which causes the AD bus to
operate in a nonmultiplexed data-only mode. The
A bus has the address during a read or write operation.
Am186™CH HDLC Microcontroller Data Sheet
t1
t2
Address
Phase
t3
t4
Data
Phase
CLKOUT
A19–A0
Address
AD15–AD0
(Read)
Address
AD15–AD0
(Write)
Address
Data
Data
LCS or UCS
MCSx, PCSx
Figure 3. Am186CH Microcontroller Address Bus — Default Operation
t1
Address
Phase
t2
t3
Data
Phase
t4
CLKOUT
A19–A0
Address
AD7–AD0
(Read)
Data
AD15–AD8
(Read)
Data
AD15–AD0
(Write)
Data
LCS or UCS
Figure 4.
Am186CH Microcontroller—Address Bus Disable In Effect
Am186™CH HDLC Microcontroller Data Sheet
29
Bus Interface
The bus interface controls all accesses to external
peripherals and memory devices. External accesses
include those to memory devices, as well as those to
memory-mapped and I/O-mapped peripherals and the
peripheral control block. The Am186CH HDLC
microcontroller provides an enhanced bus interface
unit with the following features:
■ Nonmultiplexed address bus
■ Separate byte write enables for high and low bytes
■ Output enable
The standard 80C186/80C188 multiplexed address
and data bus requires system interface logic and an external address latch. On the Am186CH HDLC microcontroller, byte write enables and a nonmultiplexed
address bus can reduce design costs by eliminating
this external logic.
Nonmultiplexed Address Bus
The nonmultiplexed address bus (A19–A0) is valid
one-half CLKOUT cycle in advance of the address on
the AD bus. When used with the modified UCS and
LCS outputs and the byte write enable signals, the
A19–A0 bus provides a seamless interface to external
SRAM, and Flash memory/EPROM systems.
Byte Write Enables
The Am186CH HDLC microcontroller provides the
WHB (Write High Byte) and WLB (Write Low Byte)
signals that act as byte write enables.
WHB is the logical OR of BHE and WR. WHB is Low
when both BHE and WR are Low. WLB is the logical
OR of A0 and WR. WLB is Low when A0 and WR are
both Low.
T h e b y t e w r i t e e n a b l e s a r e d r i ve n w i t h t h e
nonmultiplexed address bus as required for the write
timing requirements of common SRAMs.
Output Enable
The Am186CH HDLC microcontroller provides the RD
(Read) signal that acts as an output enable for memory
or peripheral devices. The RD signal is Low when a
word or byte is read by the microcontroller.
DRAM Support
To s u p p o r t D R A M , t h e A m 1 8 6 C H H D L C
microcontroller has a fully integrated DRAM controller
that provides a glueless interface to 25–70-ns
Extended Data Out (EDO) DRAM. (EDO DRAM is
sometimes called Hyper-Page Mode DRAM.) Up to two
banks of 4-Mbit (256 Kbit x 16 bit) DRAM can be
accessed. Page Mode DRAM, Fast Page Mode
DRAM, Asymmetrical DRAM, and 8-bit wide DRAM are
not supported. The microcontroller provides zero-wait
state operation at up to 50 MHz with 40-ns DRAM. This
allows designs requiring larger amounts of memory to
30
save system cost over SRAM designs by taking
advantage of low DRAM memory costs.
The DRAM interface uses various chip select pins to
implement the RAS/CAS interface required by DRAMs.
The DRAM controller drives the RAS/CAS interface
appropriately during both normal memory accesses
and during refresh. All signals required are generated
by the microcontroller and no external logic is required.
The DRAM multiplexed address pins are connected to
the odd address pins of the Am186CH HDLC
microcontroller, starting with A1 on the Am186CH
HDLC microcontroller connecting to MA0 on the
DRAM. The correct row and column addresses are
generated on these odd address pins during a DRAM
access.
The RAS pins are multiplexed with LCS and MCS3,
allowing a DRAM bank to be present in either high or
low memory space. The MCS1 and MCS2 function as
the upper and lower CAS pins, respectively, and define
which byte of data in a 16-bit DRAM is being accessed.
The microcontroller supports the most common DRAM
refresh option, CAS-Before-RAS. All refresh cycles
contain three wait states to support the DRAMs at
various frequencies. The DRAM controller never
performs a burst access. All accesses are single
accesses to DRAM. If the PCS chip selects are
decoded to be in the DRAM address range, PCS
accesses take precedence over the DRAM.
Chip Selects
The Am186CH HDLC microcontroller provides six chip
select outputs for use with memory devices and eight
more for use with peripherals in either memory or I/O
space. The six memory chip selects can be used to
address three memory ranges. Each peripheral chip
select addresses a 256-byte block offset from a
programmable base address.
The microcontroller can be programmed to sense a
ready signal for each of the peripheral or memory chip
select lines. A bit in each chip select control register
determines whether the external ready signal is
required or ignored.
The chip selects can control the number of wait states
inserted in the bus cycle. Although most memory and
peripheral devices can be accessed with three or less
wait states, some slower devices cannot. This feature
allows devices to use wait states to slow down the bus.
The chip select lines are active for all memory and I/O
cycles in their programmed areas, whether they are
generated by the CPU or by the integrated DMA unit.
General enhancements over the original 80C186
include bus mastering (three-state) support for all chip
selects and activation only when the associated
register is written, not when it is read.
Am186™CH HDLC Microcontroller Data Sheet
Clock Control
The processor supports clock rates from 16 to 50 MHz
using an integrated cr ystal oscillator and PLL.
Commercial and industrial temperature ratings are
available. The CPU can run in 1x, 2x, or 4x PLL mode.
In-Circuit Emulator Support
Because pins are an expensive resource, many play a
dual role, and the programmer selects PIO operation or
an alternate function. However, a pin configured to be
a PIO may also be required for emulation support.
Therefore, it is impor tant that before a design is
committed to hardware, a user should contact potential
emulator suppliers for a list of their emulator’s pin
r e q ui r em e n ts. T h e fo l l owi n g P I O s i g na l s ar e
multiplexed with alternate signals that may be used by
emulators: PIO8, PIO15, PIO33–PIO35.
The Am186CH HDLC microcontroller was designed to
minimize conflicts. In most cases, pin conflict is
avoided. For example, if the ALE signal is required for
multiplex bus support, then it is not programmed as
PIO33. If the multiplexed AD bus is not used, then ALE
ca n be pro gramme d as a P IO pi n. And i f th e
multiplexed bus is not in use, then the emulator does
not require the ALE signal. However, an emulator is
likely to always use the de-multiplexed address,
regardless of how the AD bus is programmed.
APPLICATIONS
The Am186CH HDLC microcontroller with its
integrated HDLC and other communications features
provides a highly integrated, cost-effective solution for
a wide range of telecommunications and networking
applications.
■ Linecard Applications: Typically, the microcontroller linecards used in Central Offices (COs), PABX
equipment, and other telephony applications require
one or two channels of HDLC. Linecard manufacturers are moving to more lines per card for analog
POTS as a means of cost reduction. This and digital
linecards often require higher performance than existing 8-bit devices can offer. The Am186CH HDLC
microcontroller is an ideal solution for these applications because it integrates much of the necessary
glue logic while providing higher performance.
Figure 5 on page 32 shows a 32-channel linecard
system application.
The 32-channel linecard design demonstrates the
Am186CH HDLC microcontroller’s use in a linecard
application where 32 incoming POTS lines are
aggregated onto a single E1 connection.
■ Industrial Control: Embedded x86 processors
have long been used in the industrial control
market. These applications often require a robust,
high-performance processor solution with the
capability to easily communicate with other parts of
a system. TheAm186CH HDLC microcontroller
provides numerous interfaces to achieve this
communication, including the SSI interface, highspeed UART, and the HDLC channels that also can
be used to create a multidrop backplane.
■ General Communications Applications: The
Am186CH HDLC microcontroller will also find a
home in general embedded applications, because
many devices will incorporate communications
capability in the future. Many designs are adding
HDLC capability as a robust means of inter- and
intra-system communications. The microcontroller is
especially attractive for 186 designs adding HDLC.
Am186™CH HDLC Microcontroller Data Sheet
31
*The Am186CH HDLC microcontroller does not have a USB peripheral controller or a GCI interface.
Figure 5.
32
32-Channel Linecard System Application
Am186™CH HDLC Microcontroller Data Sheet
CLOCK GENERATION AND CONTROL
The Am186CH HDLC microcontroller clocks include
the general system clock (CLKOUT), transmitter/
receiver clocks for each HDLC channel, and the baud
rate generator clock for UART and High-Speed UART.
The SSI and the timers (Timers 0, 1, and 2) derive their
clocks from the system clock.
Features
The Am186CH HDLC microcontroller clocks include
the following features and characteristics:
■ A crystal-controlled oscillator that uses an external
fundamental mode crystal or oscillator to generate
the system input clock.
■ An internal PLL that generates a system clock
(CLKOUT) that is 1x, 2x, or 4x the system input
clock.
■ Each HDLC receives its clock inputs directly from
the external communication clock pins (TCLK _X
and RCLK_X) in all modes. The system clock must
be at least the same frequency as any HDLC clock.
– HDLC DCE and PCM modes support clocks up to
10 MHz.
■ SSI clock (SCLK) is derived from the system clock,
divided by 2, 4, 8, 16, 32, 64, 128, or 256.
■ UART clock can be derived from the internal system
clock frequency or from the UART clock (UCLK)
input.
See Figure 6 for a diagram of the basic clock
generation and Figure 7 on page 34 for suggested
clock frequencies and modes.
System Clock
The system PLL generates frequencies from 16 to
50 MHz. The reference for the system PLL can vary
from 8 to 40 MHz, depending on the PLL mode selected
and the desired system frequency (see Figure 7 on
page 34).
The system PLL modes are chosen by the state of the
{CLKSEL1} and {CLKSEL2} pins during reset. For these
pinstrap settings see Table 26, “Reset Configuration
Pins (Pinstraps),” on page A-7.
The system clock can be generated in one of two ways:
■ Using the internal PLL running at 1x, 2x, or 4x the
reference clock. The reference clock can be
generated from an external crystal using the
integrated oscillator or an external oscillator input.
■ Bypassing the internal PLL. The external reference
generated from either a crystal or an external
oscillator input is used to generate the system clock
(see “PLL Bypass Mode” on page 35).
■ Timers 0 and 1 can be configured to be driven by
the timer input pins (TMRIN1, TMRIN0) or at onefourth of the system clock. Timer 2 is driven at onefourth of the system clock.
Am186CH HDLC Microcontroller
1x
X1
X2
PLL
System Clock
2x
CLKOUT
4x
PLL Bypass Mode
{CLKSEL2}–{CLKSEL1}
Figure 6.
System Clock Generation
Am186™CH HDLC Microcontroller Data Sheet
33
System Operating Frequency
20 MHz
0 MHz
30 MHz
24 MHz
40 MHz
32 MHz
16 MHz
8-MHz to 12.5-MHz Xtal or Clock
4x Mode
8-MHz to 25-MHz Xtal or Clock
2x Mode
16-MHz to 40-MHz Xtal or Clock1
1x Mode
PLL
Bypass
Mode
0-MHz to 24-MHz Xtal or Clock
PLL Bypass Mode
1The
1x Mode
2x Mode
4x Mode
crystal oscillator is not guaranteed above 40 MHz.
Figure 7.
Suggested System Clock Frequencies, Clock Modes, and Crystal Frequencies
Crystal-Driven Clock Source
The internal oscillator circuit is designed to function
with an external parallel-resonant fundamental mode
crystal. The crystal frequency can vary from 8 to
40 MHz, depending on the PLL mode selected and desired system frequency.
When selecting a crystal, the load capacitance should
always be specified (C L ). This value can cause
variance in the oscillation frequency from the desired
specified value (resonance). The load capacitance and
the loading of the feedback network have the following
relationship:
Table 6. Crystal Parameters
Parameter
Min.
Value
Max.
Value
Units
Frequency
8
40
MHz
ESR
8–24 MHz
20
90
ohms
24–50 MHz
20
60
ohms
Load capacitance
10
—
pF
CL = (C1 ⋅ C2) + CS
(C1 + C2)
Xtal
where CS is the stray capacitance of the circuit.
Table 6 shows crystal parameter values. Figure 8
shows the system clocks using an external crystal and
the integrated oscillator. The specific values for C 1 and
C 2 must be determined by the designer and are
dependent on the characteristics of the chosen crystal
and board design.
34
50 MHz
X1
X2
C1
Figure 8.
C2
External Interface to Support Clocks—
Fundamental Mode Crystal
Am186™CH HDLC Microcontroller Data Sheet
External Clock Source
The internal oscillator also can be driven by an external
clock source. The external clock source should be
connected to the input of the inverting amplifier (X1)
with the output (X2) left unconnected. Figure 9 shows
the system clocks using an external clock source
(oscillator bypass).
Note: X1 and X2 are not 5-V tolerant and have a
maximum input equal to VCC.
X1
External
Clock
When changing frequency in PLL Bypass mode, the X1
input must not have any short or “runt” pulses. At
24 MHz, the nominal High/Low time is 21 ns. The
actual High times and Low times must not fall below 16
ns. These values allow a 60%/40% duty cycle at X1.
In the Am186CH microcontroller, the system clock
must be at the same or a greater frequency than the
HDLC clock and UCLK (if using UCLK). Therefore, if
reducing the system clock frequency, disable these
interfaces or run them at a lower frequency.
UART Baud Clock
NC
Figure 9.
an external clock source. For PLL Bypass Mode
enabling, see Table 26, “Reset Configuration Pins
(Pinstraps),” on page A-7.
X2
External Interface to Support Clocks—
External Clock Source
Static Operation
The Am186CH HDLC microcontroller is a fully static
design and can be placed in static mode by stopping
the input clock. See the PLL Bypass Mode discussion
below.
Note: It is the responsibility of the system designer to
ensure that no short clock phases are generated when
starting or stopping the clock.
The UART and High-Speed UART have two possible
clock sources: the system clock or the UCLK input pin.
If UCLK is used for the UART clock, the system clock
must be at least the same frequency as UCLK. The
clock configurations are shown graphically in
Figure 10.
The baud clock is generated by dividing the clock
source by the value of the baud rate divisor register.
The serial port logic can select its baud rate clock from
either an external pin (UCLK) or from the system clock.
The system or UCLK clock is selected independent of
any other settings.
The formula for determining the baud rate divisor
register value is:
PLL Bypass Mode
BAUDDIV = (clock frequency/(16 • baud rate))
The Am186CH HDLC microcontroller provides a PLL
Bypass mode that allows the X1 input frequency to be
anywhere from 0 to 24 MHz. When the microcontroller
is in PLL Bypass mode, the CLKOUT frequency equals
the X1 input frequency. This mode must be used with
Note: UCLK cannot be clocked at a frequency higher
than the system clock frequency.
Oversample
Clock
System Clock
Baud
Divisor
UCLK
UART/High-Speed UART
Clock Select
Divide for
Oversampling
Baud Clock
Autobaud Clock
(High-Speed UART Only)
Figure 10.
UART and High-Speed UART Clocks
Am186™CH HDLC Microcontroller Data Sheet
35
POWER SUPPLY OPERATION
CMOS dynamic power consumption is proportional to
the square of the operating voltage multiplied by
capacitance and operating frequency. Static CPU
operation can reduce power consumption by enabling
the system designer to reduce operating frequency
when possible. However, operating voltage is always the
dominant factor in power consumption. By reducing the
operating voltage from 5 V to 3.3 V for any device, the
power consumed is reduced by 56%.
Reduction of CPU and system logic operating voltage
dramatically reduces overall system power consumption. Additional power savings can be realized as lowvoltage mass storage and peripheral devices become
available.
Two basic strategies exist in designing systems
containing the Am186CH HDLC microcontroller. The
first strategy is to design a homogenous system in
which all logic components operate at 3.3 V. This
provides the lowest overall power consumption.
However, system designers may need to include
devices for which 3.3-V versions are not available.
n During power-up, if the 3.3-V supply has a
significant delay in achieving stable operation
relative to 5-V supply, then the 5-V circuitry in the
system may start driving the processor’s inputs
above the maximum levels (V CC + 2.6 V). The
system design should ensure that the 5-V supply
does not exceed 2.6 V above the 3.3-V supply
during a power-on sequence.
n Preferably, all inputs are driven by sources that can
be three-stated during a system reset condition.
The system reset condition should persist until
stable V CC conditions are met. This should help
ensure that the maximum input levels are not
exceeded during power-up conditions.
n Preferably, all pullup resistors are tied to the 3.3-V
supply, which ensures that inputs requiring pullups
are not over stressed during power-up.
PIO Supply Current Limit
Each programmable I/O output is able to sink or source
a sustained 16-mA drive current. However, only 40 mA
of sustained PIO current is allowed for each supply pin
(VCC), and only 60 mA is allowed for each ground pin
(VSS).
In the second strategy, the system designer must then
design a mixed 5-V/3.3-V system. This compromise
enables the system designer to minimize the system
logic power consumption while still including the
functionality of the 5-V features. The choice of a mixed
voltage system design also involves balancing design
complexity with the need for the additional features.
To calculate the PIO current for each supply or ground
pin, sum the applicable current (source or sink) of all
PIO pins on either side of the pin (to the adjacent
corresponding pins), and divide the sum by two. The
resulting value should not exceed 40 mA for VCC or
60 mA for VSS.
Power Supply Connections
Exclude the following pins from this calculation: 72
(VSS_A), 82 (VSS), 77 (VCC_A), and 79 (VCC).
Connect all V CC pins together to the 3.3-V power
supply and all ground pins to a common system
ground.
Input/Output Circuitry
For example, to calculate the PIO current for pin 83
(VSS), total the sustained sinking current for all PIO
pins between pin 71 (V SS ) and pin 100 (V SS ), and
divide the sum by two.
To accommodate current 5-V systems, the Am186CH
HDLC microcontroller has 5-V tolerant I/O drivers. The
drivers produce TTL-compatible drive output (minimum
2.4-V logic High) and receive TTL and CMOS levels (up
to VCC + 2.6 V). The following are some design issues
that should be considered with mixed 3.3-V/5-V
designs:
36
Am186™CH HDLC Microcontroller Data Sheet
ABSOLUTE MAXIMUM RATINGS1
Parameter
Symbol
Minimum
Maximum
Unit
0
100
°C
2
Temperature under bias: commercial
TC
Industrial
TA3
–40
+85
°C
Storage temperature
—
–65
+150
°C
Voltage on 5-V-tolerant pins4 with respect to ground
—
–0.5
VCC + 2.6
V
Voltage on other pins with respect to ground
—
–0.5
VCC + 0.5
V
—
40
—
mA
—
60
—
mA
Sustained current on any supply (VCC) pin
5
Sustained PIO current on any ground (VSS) pin5
Notes:
1. Stresses above those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
2. TC = case temperature.
3. TA = ambient temperature.
4. 5-V-tolerant pins are indicated in Table 30, “Pin List Summary,” on page A-11.
5. See “PIO Supply Current Limit” on page 36.
OPERATING RANGES1
Parameter
Symbol
Minimum
Maximum
Unit
2
Commercial
TC
0
100
°C
Industrial
TA3
–40
+ 85
°C
Supply voltage with respect to ground
VCC
3.0
3.6
V
Notes:
1. Operating Ranges define those limits between which the functionality of the device is guaranteed.
2. TC = case temperature.
3. TA = ambient temperature.
DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES1
Symbol
VOH
Preliminary
Parameter
Output High voltage (IOH = –2.4 mA)
mA)2
Minimum
Maximum
2.4
—
Unit
V
VOH
Output High voltage (IOH = –0.1
VCC – 0.2
—
V
VOL
Output Low voltage (IOL = 4.0 mA)
—
0.45
V
VIH5
5-V tolerant Input High voltage
2.0
VCC + 2.6
V
VIH
Input High voltage, except 5-V tolerant
2.0
VCC + 0.3
V
VIL
Input Low voltage
–0.3
0.8
V
ILI
Input leakage current (0.1 V ˆ VOUT ˆ VCC)
(all pins except those with internal pullup/pulldown resistors)
—
±10
mA
ILO
Output leakage current3 (0.1 V ˆ VOUT ˆ VCC)
—
±15
mA
PCC
Power consumption
—
1.2
W
Notes:
1. Current out of pin is stated as a negative value.
2. Characterized but not tested.
3. This parameter is for three-state outputs where VOUT is driven on the three-state output.
Am186™CH HDLC Microcontroller Data Sheet
37
CAPACITANCE
Symbol
Preliminary
Parameter
Minimum
Maximum
Unit
CIN
Input capacitance
—
15
pF
CCLK
Clock capacitance
—
15
pF
COUT
Output capacitance
—
20
pF
CI/O
I/O pin capacitance
—
20
pF
MAXIMUM LOAD DERATING
■ No DC loads on the output buffers
All maximum delay numbers should be increased by
0.035 ns for every pF of load over the maximum load
(up to a maximum of 150 pF) specified in Table 30, “Pin
List Summary,” on page A-11.
■ Output capacitive load set to 30 pF
■ AD bus set to data only
■ PIOs are disabled
POWER SUPPLY CURRENT
■ Timer, serial port, refresh, and DMA are enabled
For the following typical system specification shown in
Figure 11, ICC has been measured at 6 mA per MHz of
system clock. The typical system is measured while the
system is executing code in a typical application with
nominal voltage and maximum case temperature.
Actual power supply current is dependent on system
design and may be greater or less than the typical ICC
figure presented here.
Table 7 shows the values that are used to calculate the
typical power consumption value for the Am186CH
HDLC microcontroller.
Table 7.
Typical Power Consumption Calculation
MHz ¼ ICC ¼ Volts / 1000 = P
Typical current in Figure 11 is given by:
ICC = 6 mA ¼ freq(MHz)
Please note that dynamic ICC measurements are dependent upon chip activity, operating frequency, output
buffer logic, and capacitive/resistive loading of the outputs. For these ICC measurements, the devices were
set to the following modes:
MHz
Typical ICC
Volts
Typical Power
in Watts
25
6
3.3
0.495
40
6
3.3
0.792
50
6
3.3
0.99
320
280
240
200
ICC (mA) 160
120
80
40
0
10
20
30
40
Clock Frequency (MHz)
Figure 11. Typical Icc Versus Frequency
38
Am186™CH HDLC Microcontroller Data Sheet
50
THERMAL CHARACTERISTICS—PQFP PACKAGE
The Am186CH HDLC microcontroller is specified for
operation with case temperature ranges from 0•C to
+100•C for 3.3 V ± 0.3 V (commercial). Case
temperature is measured at the top center of the
pack age a s s hown in Fi gur e 12 . Th e va r i ous
temperatures and ther mal resistances can be
determined using the equations in Figure 13 with
information given in Table 8.
The total thermal resistance is qJA; qJA is the sum of
qJC, the internal thermal resistance of the assembly,
and qCA, the case-to-ambient thermal resistance.
qJA
qCA
TC q
JC
qJA = qJC + qCA
Figure 12.
Thermal Resistance(•C/Watt)
The variable P is power in watts. Power supply current
(ICC) is in mA per MHz of clock frequency.
qJA = qJC + qCA
P = ICC ¼ freq (MHz) ¼ VCC
TJ = TC + (P ¼ qJC)
TJ = TA + (P ¼ qJA)
¼ qJC)
¼ qCA)
TA = TJ – (P ¼ qJA)
TA = TC – (P ¼ qCA)
TC = TJ – (P
TC = TA + (P
Figure 13.
Thermal Characteristics Equations
Table 8. Thermal Characteristics (•C/Watt)
Package/Board
PQFP/2-Layer
PQFP/4-Layer
to 6-Layer
Airflow
(Linear Feet
per Minute)
qJC
qCA
qJA
0 fpm
7
38
45
200 fpm
7
32
39
400 fpm
7
28
35
600 fpm
7
26
33
0 fpm
5
18
23
200 fpm
5
16
21
400 fpm
5
14
19
600 fpm
5
12
17
Am186™CH HDLC Microcontroller Data Sheet
39
COMMERCIAL AND INDUSTRIAL SWITCHING CHARACTERISTICS AND WAVEFORMS
In the switching waveforms that follow, several
abbreviations are used to indicate the specific periods
of a bus cycle. These periods are referred to as time
states. A typical bus cycle is composed of four
consecutive time states: t1, t2, t3, and t4. Wait states,
which represent multiple t3 states, are referred to as tw
states. When no bus cycle is pending, an idle (ti) state
occurs.
bus; the demultiplexed address is referred to as the A
address bus. Figure 14 defines symbols used in the
switching waveform diagrams.
Table 9 on page 41 contains an alphabetical listing of
the switching parameter symbols (grouped by
function), and Table 10 on page 44 contains a
numerical listing of the switching parameter symbols
(grouped by function).
In th e sw i tc hi n g pa r am e t e r d e s c r i p ti o n s, t h e
multiplexed address is referred to as the AD address
WAVEFORM
INPUT
OUTPUT
Must be
Steady
Will be
Steady
May change
from H to L or
from H to threestate
Will be changing
from H to L or
from H to threestate
May change
from L to H or
from L to threestate
Will be changing
from L to H or
from L to threestate
Figure 14. Key to Switching Waveforms
40
Am186™CH HDLC Microcontroller Data Sheet
Table 9. Alphabetical Key to Switching Parameter Symbols
Parameter
Symbol
No.
Description
tARYCH
49
ARDY resolution transition setup time
tARYCHL
51
ARDY inactive holding time
tARYHDSH
951
ARDY High to DS High
tARYHDV
891
ARDY assert to data valid
tARYLCL
52
ARDY setup time
1
tARYLDSH
96
ARDY Low to DS High
tAVBL
87
A address valid to WHB, WLB Low
tAVCH
14
AD address valid to clock High
tAVLL
12
AD address valid to ALE Low
tAVRL
66
A address valid to RD Low
tAVWL
65
A address valid to WR Low
tAZRL
24
AD address float to RD active
tCH1CH2
45
CLKOUT rise time
tCHAV
68
CLKOUT High to A address valid
tCHCAS
404
Change in CAS delay
tCHCK
38
X1 High time
tCHCL
44
CLKOUT High time
tCHCSV
67
CLKOUT High to LCS/UCS valid
tCHCSX
18
MCSx/PCSx inactive delay
tCHCTV
22
Control active delay 2
tCHCV
64
Command lines valid delay (after float)
tCHCZ
63
Command lines float delay
tCHDX
8
Status hold time
tCHLH
9
ALE active delay
tCHLL
11
ALE inactive delay
tCHQS0V
55
Queue status 0 output delay
tCHQS1V
56
Queue status 1 output delay
tCHRAS
403
Change in RAS delay
tCHRFD
791
CLKOUT High to RFSH valid
tCHSV
3
Status active delay
tCICO
69
X1 to CLKOUT skew
tCKHL
39
X1 fall time
tCKIN
36
X1 period
tCKLH
40
X1 rise time
tCL2CL1
46
CLKOUT fall time
tCLARX
50
ARDY active hold time
tCLAV
5
AD address and BHE valid delay
tCLAX
6
Address hold
tCLAZ
15
AD address float delay
tCLCH
43
CLKOUT Low time
tCLCK
37
X1 Low time
tCLCL
42
CLKOUT period
tCLCLX
801
LCS inactive delay
Am186™CH HDLC Microcontroller Data Sheet
41
Table 9. Alphabetical Key to Switching Parameter Symbols (Continued)
42
Parameter
Symbol
No.
Description
tCLCSL
811
LCS active delay
tCLCSV
16
MCSx/PCSx active delay
tCLDOX
30
Data hold time
tCLDV
7
Data valid delay
tCLDX
2
Data in hold
tCLHAV
62
HLDA valid delay
tCLRF
821
CLKOUT High to RFSH invalid
tCLRH
27
RD inactive delay
tCLRL
25
RD active delay
tCLRO
61
Reset delay
tCLSH
4
Status and BHE inactive delay
tCLSRY
48
SRDY transition hold time
tCLTMV
54
Timer output delay
tCOLV
402
Column address valid delay
tCSHARYL
881
Chip select to ARDY Low
tCVCTV
20
Control active delay 1
tCVCTX
31
Control inactive delay
tCVDEX
21
DEN/DS inactive delay
tCXCSX
17
MCSx/PCSx hold from command inactive
tDSHDIR
921
DS High to data invalid—read
tDSHDIW
1
98
DS High to data invalid—write
tDSHDX
931
DS High to data bus turn-off time
tDSHLH
41
DS inactive to ALE inactive
tDSLDD
901
DS Low to data driven
tDSLDV
911
DS Low to data valid
tDVCL
1
tDVDSL
971
Data valid to DS Low
Data in setup
tDXDL
19
DEN/DS inactive to DT/R Low
tHVCL
58
HOLD setup
tINVCH
53
Peripheral setup time
tLCRF
861
LCS inactive to RFSH active delay
tLHAV
23
ALE High to address valid
tLHLL
10
ALE width
tLLAX
13
AD address hold from ALE inactive
tLRLL
841
LCS precharge pulse width
tRESIN
57
RES setup time
tRFCY
851
RFSH cycle time
tRHAV
29
RD inactive to AD address active
tRHDX
59
RD High to data hold on AD bus
tRHDZ
941
RD High to data bus turn-off time
tRHLH
28
RD inactive to ALE High
tRLRH
26
RD pulse width
tSRYCL
47
SRDY transition setup time
Am186™CH HDLC Microcontroller Data Sheet
Table 9. Alphabetical Key to Switching Parameter Symbols (Continued)
Parameter
Symbol
No.
Description
tWHDEX
35
WR inactive to DEN inactive
tWHDX
34
Data hold after WR
tWHLH
33
WR inactive to ALE High
tWLWH
32
WR pulse width
DCE
tTCLKH
2
DCE clock High
tTCLKHD
6
DCE clock hold
tTCLKL
3
DCE clock Low
tTCLKO
4
DCE clock to output delay
tTCLKPER
1
DCE clock period
tTCLKR
7
DCE clock rise/fall
tTCLKSU
5
DCE clock setup
tCLKP
1
PCM clock period
tDCD
8
Delay time from CLK High to TXD valid
tDCLT
13
Delay from CLK Low of last bit to TSC invalid
tDCT
11
Delay to TSC valid from CLK
PCM (Slave)
tDFT
12
Delay to TSC valid from FSC
tDTW
17
Delay from last bit CLK Low to TXD weak drive
tDZC
5
Delay time to valid TXD from CLK
tDZF
6
Delay time to valid TXD from FSC
tHCD
10
Hold time from CLK Low to RXD invalid
tHCF
4
Hold time from CLK Low to FSC valid
tHFI
14
Hold time from CLK Low to FSC invalid
tSUDC
9
Setup time from RXD valid to CLK
tSUFC
7
Setup time for FSC High to CLK Low
tSYNSS
15
Time between successive synchronization pulses
tWH
2
PCM clock High
tWL
3
PCM clock Low
tWSYN
16
FSC width invalid
tDTZ
18
Delay from last bit CLK (plus one) High to TXD disable
tDCFH
1
Delay time from CLK High to FSC High
tDCFL
2
Delay time from CLK High to FSC Low
tCLEV
1
CLKOUT Low to SDEN valid
tCLSL
2
CLKOUT Low to SCLK Low
PCM (Master)
SSI
tDVSH
3
Data valid to SCLK High
tSHDX
4
SCLK High to data invalid
tSLDV
5
SCLK Low to data valid
Notes:
1. Specification defined but not in use at this time.
Am186™CH HDLC Microcontroller Data Sheet
43
Table 10.
44
Numerical Key to Switching Parameter Symbols
No.
Parameter
Symbol
Description
1
tDVCL
Data in setup
2
tCLDX
Data in hold
3
tCHSV
Status active delay
4
tCLSH
Status and BHE inactive delay
5
tCLAV
AD address and BHE valid delay
6
tCLAX
Address hold
7
tCLDV
Data valid delay
8
tCHDX
Status hold time
9
tCHLH
ALE active delay
10
tLHLL
ALE width
11
tCHLL
ALE inactive delay
12
tAVLL
AD address valid to ALE Low
13
tLLAX
AD address hold from ALE inactive
14
tAVCH
AD address valid to clock High
15
tCLAZ
AD address float delay
16
tCLCSV
MCSx/PCSx active delay
17
tCXCSX
MCSx/PCSx hold from command inactive
18
tCHCSX
MCSx/PCSx inactive delay
19
tDXDL
DEN/DS inactive to DT/R Low
20
tCVCTV
Control active delay 1
21
tCVDEX
DEN/DS inactive delay
Control active delay 2
22
tCHCTV
23
tLHAV
ALE High to address valid
24
tAZRL
AD address float to RD active
25
tCLRL
RD active delay
26
tRLRH
RD pulse width
27
tCLRH
RD inactive delay
28
tRHLH
RD inactive to ALE High
29
tRHAV
RD inactive to AD address active
30
tCLDOX
Data hold time
31
tCVCTX
Control inactive delay
32
tWLWH
WR pulse width
33
tWHLH
WR inactive to ALE High
34
tWHDX
Data hold after WR
35
tWHDEX
WR inactive to DEN inactive
36
tCKIN
X1 period
37
tCLCK
X1 Low time
38
tCHCK
X1 High time
39
tCKHL
X1 fall time
40
tCKLH
X1 rise time
41
tDSHLH
DS inactive to ALE inactive
42
tCLCL
CLKOUT period
43
tCLCH
CLKOUT Low time
Am186™CH HDLC Microcontroller Data Sheet
Table 10.
Numerical Key to Switching Parameter Symbols (Continued)
No.
Parameter
Symbol
44
tCHCL
CLKOUT High time
45
tCH1CH2
CLKOUT rise time
46
tCL2CL1
CLKOUT fall time
47
tSRYCL
SRDY transition setup time
48
tCLSRY
SRDY transition hold time
49
tARYCH
ARDY resolution transition setup time
50
tCLARX
ARDY active hold time
51
tARYCHL
ARDY inactive holding time
52
tARYLCL
ARDY setup time
53
tINVCH
Peripheral setup time
54
tCLTMV
Timer output delay
55
tCHQS0V
Queue status 0 output delay
56
tCHQS1V
Queue status 1 output delay
57
tRESIN
RES setup time
58
tHVCL
HOLD setup
59
tRHDX
RD High to data hold on AD bus
61
tCLRO
Reset delay
62
tCLHAV
HLDA valid delay
63
tCHCZ
Command lines float delay
64
tCHCV
Command lines valid delay (after float)
65
tAVWL
A address valid to WR Low
A address valid to RD Low
Description
66
tAVRL
67
tCHCSV
CLKOUT High to LCS/UCS valid
68
tCHAV
CLKOUT High to A address valid
69
tCICO
X1 to CLKOUT skew
1
79
tCHRFD
CLKOUT High to RFSH valid
801
tCLCLX
LCS inactive delay
1
tCLCSL
LCS active delay
1
81
tCLRF
CLKOUT High to RFSH invalid
1
84
tLRLL
LCS precharge pulse width
851
tRFCY
RFSH cycle time
1
86
tLCRF
LCS inactive to RFSH active delay
87
tAVBL
A address valid to WHB, WLB Low
82
1
88
tCSHARYL
Chip select to ARDY Low
891
tARYHDV
ARDY assert to data valid
1
tDSLDD
DS Low to data driven
1
tDSLDV
DS Low to data valid
1
92
tDSHDIR
DS High to data invalid—read
931
tDSHDX
DS High to data bus turn-off time
1
tRHDZ
RD High to data bus turn-off time
1
tARYHDSH
ARDY High to DS High
1
96
tARYLDSH
ARDY Low to DS High
971
tDVDSL
Data valid to DS Low
90
91
94
95
Am186™CH HDLC Microcontroller Data Sheet
45
Table 10.
Numerical Key to Switching Parameter Symbols (Continued)
No.
Parameter
Symbol
981
tDSHDIW
Description
DS High to data invalid—write
Column address valid delay
402
tCOLV
403
tCHRAS
Change in RAS delay
404
tCHCAS
Change in CAS delay
DCE
DCE clock period
1
tTCLKPER
2
tTCLKH
DCE clock High
3
tTCLKL
DCE clock Low
4
tTCLKO
DCE clock to output delay
5
tTCLKSU
DCE clock setup
6
tTCLKHD
DCE clock hold
7
tTCLKR
DCE clock rise/fall
1
tCLKP
PCM clock period
2
tWH
PCM clock High
3
tWL
PCM clock Low
4
tHCF
Hold time from CLK Low to FSC valid
5
tDZC
Delay time to valid TXD from CLK
6
tDZF
Delay time to valid TXD from FSC
7
tSUFC
Setup time for FSC High to CLK Low
8
tDCD
Delay time from CLK High to TXD valid
PCM (Slave)
9
tSUDC
Setup time from RXD valid to CLK
10
tHCD
Hold time from CLK Low to RXD invalid
11
tDCT
Delay to TSC valid from CLK
12
tDFT
Delay to TSC valid from FSC
13
tDCLT
Delay from CLK Low of last bit to TSC invalid
14
tHFI
15
tSYNSS
Time between successive synchronization pulses
16
tWSYN
FSC width invalid
17
tDTW
Delay from last bit CLK Low to TXD weak drive
18
tDTZ
Delay from last bit CLK (plus one) High to TXD disable
Hold time from CLK Low to FSC invalid
PCM (Master)
tDCFH
1
Delay time from CLK High to FSC High
tDCFL
2
Delay time from CLK High to FSC Low
1
tCLEV
CLKOUT Low to SDEN valid
2
tCLSL
CLKOUT Low to SCLK Low
3
tDVSH
Data valid to SCLK High
4
tSHDX
SCLK High to data invalid
5
tSLDV
SCLK Low to data valid
SSI
Notes:
1. Specification defined but not in use at this time.
46
Am186™CH HDLC Microcontroller Data Sheet
Switching Characteristics over Commercial and Industrial Operating Ranges
In this section, the following timings and timing
waveforms are shown:
■ External ready (page 57)
■ Read (page 47)
■ System clocks (page 61)
■ Write (page 50)
■ PCM highway (slave) (page 62)
■ Software halt (page 53)
■ DCE interface (page 65)
■ Peripheral (page 54)
■ SSI (page 66)
■ Reset (page 55)
■ DRAM (page 67)
■ Bus hold (page 59)
Table 11. Read Cycle Timing1
Preliminary
Parameter
No.
Symbol
25 MHz
Description
Min
50 MHz
(Commercial Only)
40 MHz
Max
Min
Max
Min
Unit
Max
General Timing Requirements
1
tDVCL
Data in setup
10
—
5
—
5
—
ns
2
tCLDX
Data in hold2
3
—
2
—
2
—
ns
General Timing Responses
3
tCHSV
Status active delay
0
20
0
12
0
10
ns
4
tCLSH
Status and BHE
inactive delay
0
20
0
12
0
10
ns
5
tCLAV
AD address and
BHE valid delay
0
20
0
12
0
10
ns
6
tCLAX
Address hold
0
—
0
—
0
—
ns
8
tCHDX
Status hold time
0
—
0
—
0
—
ns
9
tCHLH
ALE active delay
—
20
—
12
—
10
ns
10
tLHLL
ALE width
tCLCL–10=30
—
tCLCL–5=20
—
tCLCL–5=15
—
ns
11
tCHLL
ALE inactive delay
—
20
—
12
—
10
ns
12
tAVLL
AD address valid to
ALE Low3
0.5 • tCLCH
—
0.5 • tCLCH
—
0.5 • tCLCH
—
ns
13
tLLAX
AD address hold
from ALE inactive3
tCHCL
—
tCHCL
—
tCHCL
—
ns
14
tAVCH
AD address valid to
clock High
0
—
0
—
0
—
ns
15
tCLAZ
AD address float
delay
tCLAX=0
20
tCLAX=0
12
tCLAX=0
10
ns
16
tCLCSV
MCSx/PCSx active
delay
0
20
0
12
0
10
ns
17
tCXCSX
MCSx/PCSx hold
from command
inactive
tCLCH
—
tCLCH
—
tCLCH
—
ns
18
tCHCSX
MCSx/PCSx
inactive delay
0
20
0
12
0
10
ns
19
tDXDL
DEN/DS inactive to
DT/R Low3, 4
–1
—
–1
—
–1
—
ns
20
tCVCTV
Control active
delay 1
0
20
0
12
0
10
ns
Am186™CH HDLC Microcontroller Data Sheet
47
Read Cycle Timing1 (Continued)
Table 11.
Preliminary
Parameter
25 MHz
50 MHz
(Commercial Only)
40 MHz
Unit
No.
Symbol
Description
Min
Max
Min
Max
Min
Max
21
tCVDEX
DEN/DS inactive
delay4
0
20
0
12
0
10
ns
22
tCHCTV
Control active
delay 2
0
20
0
12
0
10
ns
23
tLHAV
ALE High to
address valid
15
—
7.5
—
5
—
ns
Read Cycle Timing Responses
24
tAZRL
AD address float to
RD active
0
—
0
—
0
—
ns
25
tCLRL
RD active delay
0
20
0
10
0
10
ns
26
tRLRH
RD pulse width
2tCLCL–15=65
—
2tCLCL–10=40
—
2tCLCL–10=30
—
ns
27
tCLRH
RD inactive delay
0
20
0
12
0
10
ns
28
tRHLH
RD inactive to ALE
High3
tCLCH–3
—
tCLCH–2
—
tCLCH–2
—
ns
29
tRHAV
RD inactive to AD
address active 3
tCLCL–10=30
—
tCLCL–5=20
—
tCLCL–5=15
—
ns
59
tRHDX
RD High to data
hold on AD Bus2
3
—
2
—
0
—
ns
66
tAVRL
A address valid to
RD Low
1.5tCLCL–15=45
—
1.5tCLCL–10=
27.5
—
1.5tCLCL–10=20
—
ns
67
tCHCSV
CLKOUT High to
LCS/UCS valid
0
20
0
10
0
10
ns
68
tCHAV
CLKOUT High to A
address valid
0
20
0
10
0
10
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
2. If either specification 2 or specification 59 is met with respect to data hold time, then the device functions correctly.
3. Testing is performed with equal loading on referenced pins.
4. The timing of this signal is the same for a read cycle, whether it is configured to be DEN or DS.
48
Am186™CH HDLC Microcontroller Data Sheet
T4
T1
T2
T3
T4
1
14
2
CLKOUT
tw
66
68
A19–A0
6
3
8
S61
23
13
5
12
AD15–AD0
15
59
24
29
Addr.
Data
11
9
10
28
ALE
27
25
26
17
RD
5
4
BHE
67
LCS, UCS
16
18
MCS3–MCS0,
PCS7–PCS0
19
20
21
DEN, DS
22
22
DT/R
3
4
S2–S0
Notes:
1. S6 is not valid for the first fetch until the timing for parameter 3 (status active delay (t CHSV)) is met.
Figure 15. Read Cycle Waveforms
Am186™CH HDLC Microcontroller Data Sheet
49
Table 12.
Write Cycle Timing1
Preliminary
Parameter
No.
Symbol
25 MHz
Description
50 MHz
(Commercial Only)
40 MHz
Min
Max
Min
Max
Min
Max
Unit
General Timing Responses
3
tCHSV
Status active delay
0
20
0
12
0
10
ns
4
tCLSH
Status and BHE
inactive delay
0
20
0
12
0
10
ns
5
tCLAV
AD address and
BHE valid delay
0
20
0
12
0
10
ns
6
tCLAX
Address hold
0
—
0
—
0
—
ns
7
tCLDV
Data valid delay
0
20
0
12
0
10
8
tCHDX
Status hold time
0
—
0
—
0
9
tCHLH
ALE active delay
—
20
—
12
—
10
ns
10
tLHLL
ALE width
tCLCL – 10 = 30
—
tCLCL – 5 = 20
—
tCLCL – 5 = 15
—
ns
11
tCHLL
ALE inactive delay
—
20
—
12
—
10
ns
12
tAVLL
AD address valid
to ALE Low2
0.5 • tCLCH
—
0.5 • tCLCH
—
0.5 • tCLCH
—
ns
13
tLLAX
AD address hold
from ALE inactive
tCHCL
—
tCHCL
—
tCHCL
—
ns
14
tAVCH
AD address valid
to clock High
0
—
0
—
0
—
ns
16
tCLCSV
MCSx/PCSx active
delay
0
20
0
12
0
10
ns
17
tCXCSX
MCSx/PCSx hold
from command
inactive
tCLCH
—
tCLCH
—
tCLCH
—
ns
18
tCHCSX
MCSx/PCSx
inactive delay
0
20
0
12
0
10
ns
19
tDXDL
DEN inactive to
DT/R2, 3
–1
—
–1
—
–1
—
ns
20
tCVCTV
Control active
delay 13,4
0
20
0
12
0
10
ns
21
tCVDEX
DS inactive
delay3,4
0
20
0
12
0
10
ns
23
tLHAV
ALE High to
address valid
15
—
7.5
—
5
—
ns
50
Am186™CH HDLC Microcontroller Data Sheet
ns
ns
Write Cycle Timing1 (Continued)
Table 12.
Preliminary
Parameter
No.
Symbol
25 MHz
Description
50 MHz
(Commercial Only)
40 MHz
Min
Max
Min
Max
Min
Max
Unit
Write Cycle Timing Responses
30
tCLDOX
Data hold time
0
—
0
—
0
—
ns
31
tCVCTX
Control inactive
delay3,4
0
20
0
12
0
10
ns
32
tWLWH
WR pulse width
2tCLCL – 10 = 70
—
2tCLCL – 10 = 40
—
2tCLCL – 10 = 30
—
ns
33
tWHLH
WR inactive to ALE
High2
tCLCH – 2
—
tCLCH – 2
—
tCLCH – 2
—
ns
34
tWHDX
Data hold after WR2
tCLCL – 10 = 30
—
tCLCL – 10 = 15
—
tCLCL – 10 = 10
—
ns
35
tWHDEX
WR inactive to
DEN inactive2,3
tCLCH – 3
—
tCLCH
—
tCLCH
—
ns
65
tAVWL
A address valid to
WR Low
tCLCL + tCHCL –3
—
tCLCL + tCHCL –
1.25
—
tCLCL + tCHCL –
1.25
—
ns
67
tCHCSV
CLKOUT High to
LCS/UCS valid
0
20
0
10
0
10
ns
68
tCHAV
CLKOUT High to A
address valid
0
20
0
10
0
10
ns
87
tAVBL
A address valid to
WHB, WLB Low
tCHCL – 3
20
tCHCL – 1.25
12
tCHCL – 1.25
10
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
2. Testing is performed with equal loading on referenced pins.
3. The timing of this signal is different during a write cycle depending on whether it is configured to be DEN or DS.
4. This parameter applies to the DEN, DS, WR, WHB, and WLB signals.
Am186™CH HDLC Microcontroller Data Sheet
51
T4
T1
T2
T3
T4
14
CLKOUT
tw
87
68
65
A19–A0
6
3
S61
23
12
8
7
34
13
5
AD15–AD0
Addr.
30
Data
11
10
9
33
ALE
31
20
35
17
32
WR
20
31
5
4
WHB, WLB
BHE
67
LCS, UCS
16
18
MCS3–MCS0,
PCS7–PCS0
31
20
19
DEN
20
21
DS
20
DT/R
31
4
3
S2–S0
Notes:
1. S6 is not valid for the first fetch until the timing for parameter 3 (status active delay (tCHSV)) is met.
Figure 16.
52
Write Cycle Waveforms
Am186™CH HDLC Microcontroller Data Sheet
Table 13. Software Halt Cycle Timing1
Preliminary
Parameter
No.
25 MHz
Symbol Description
50 MHz
(Commercial Only)
40 MHz
Unit
Min
Max
Min
Max
Min
Max
3
tCHSV
Status active delay
0
20
0
12
0
10
ns
4
tCLSH
Status inactive
delay
0
20
0
12
0
10
ns
5
tCLAV
AD address invalid
delay
0
20
0
12
0
10
ns
9
tCHLH
ALE active delay
—
20
—
12
—
10
ns
10
tLHLL
ALE width
tCLCL – 10 = 30
—
tCLCL – 5 = 20
—
tCLCL – 5 = 15
—
ns
11
tCHLL
ALE inactive delay
—
20
—
12
—
10
19
tDXDL
DEN inactive to
DT/R Low2
–1
—
–1
—
–1
22
tCHCTV
Control active
delay 23
0
20
0
12
0
10
ns
68
tCHAV
CLKOUT High to A
address invalid
0
20
0
12
0
10
ns
ns
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
2. Testing is performed with equal loading on referenced pins.
3. This parameter applies to the DEN/DS signal.
T4
T1
T2
TI
TI
CLKOUT
68
A19–A0
Invalid Address
5
S6, AD15–AD0
Invalid Address
11
10
9
ALE
22
19
DEN, DS
DT/R
4
3
S2–S0
Figure 17.
Software Halt Cycle Waveforms
Am186™CH HDLC Microcontroller Data Sheet
53
Table 14. Peripheral Timing1,
2
Preliminary
Parameter
25 MHz
Description
50 MHz
(Commercial Only)
40 MHz
Unit
No.
Symbol
Min
Max
Min
Max
Min
Max
53
tINVCH
Peripheral setup time
10
—
5
—
5
—
ns
54
tCLTMV
Timer output delay
—
25
—
15
—
12
ns
55
tCHQS0V
Queue status 0 output delay
—
25
—
15
—
12
ns
56
tCHQS1V
Queue status 1 output delay
—
25
—
15
—
12
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
2. PIO outputs change anywhere from the beginning of T3 to the first half of T4 of the bus cycle in which the PIO data register is
written.
56
53
54
CLKOUT
INT8–INT0, NMI, TMRINx
DRQ0, DRQ1
TMROUT
QS0
QS1
Figure 18.
54
Peripheral Timing Waveforms
Am186™CH HDLC Microcontroller Data Sheet
55
Table 15. Reset Timing1
Preliminary
Parameter
Description
25 MHz
50 MHz
(Commercial Only)
40 MHz
Unit
No.
Symbol
Min
Max
Min
Max
Min
Max
57
tRESIN
RES setup time
10
—
5
—
5
—
ns
61
tCLRO
Reset delay
—
18
—
15
—
12
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
57
RES
CLKOUT
61
RESOUT
Notes:
1. RES must be held Low for 1 ms during power-up to ensure proper device initialization.
2. Diagram is shown for the system PLL in its 2x mode of operation.
3. Diagram assumes that VCC is stable (i.e., 3.3 V ± 0.3 V) during the 1-ms RES active time.
Figure 19. Reset Waveforms
Am186™CH HDLC Microcontroller Data Sheet
55
RES
CLKOUT
All Pinstrap
Pins1,2
AD15–AD01
All Other
Outputs
RESOUT
Notes:
1. The pinstraps and AD bus are sampled during the assertion of RESOUT for system configuration purposes.
2. See Appendix A, “Reset Configuration Pins (Pinstraps),” on page A-7 for a list of all the pinstraps.
Figure 20.
Signals Related to Reset (System PLL in 1x or 2x Mode)
RES
CLKOUT
All Pinstrap
Pins1,2
AD15–AD01
All Other
Outputs
RESOUT
Notes:
1. The pinstraps and AD bus are sampled during the assertion of RESOUT for system configuration purposes.
2. See Appendix A, “Reset Configuration Pins (Pinstraps),” on page A-7 for a list of all the pinstraps.
Figure 21.
56
Signals Related to Reset (System PLL in 4x Mode)
Am186™CH HDLC Microcontroller Data Sheet
Table 16. External Ready Cycle Timing1
Preliminary
Parameter
No.
Symbol
25 MHz
Description
40 MHz
50 MHz
(Commercial Only)
Unit
Min
Max
Min
Max
Min
Max
10
—
5
—
5
—
ns
3
—
2
—
2
—
ns
Ready Timing Requirements
47
48
tSRYCL
tCLSRY
SRDY transition setup time2
2
SRDY transition hold time
3
49
tARYCH
ARDY resolution transition setup time
10
—
5
—
5
—
ns
50
tCLARX
ARDY active hold time2
4
—
3
—
3
—
ns
51
tARYCHL
ARDY inactive holding time
10
—
5
—
5
—
ns
15
—
5
—
5
—
ns
52
tARYLCL
ARDY setup time
2
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
2. This timing must be met to guarantee proper operation.
3. This timing must be met to guarantee recognition at the clock edge.
Case 11
Tw
Tw
Tw
T4
21
T3
Tw
Tw
T4
Case 31
T2
T3
Tw
T4
42
T1
T2
T3
Case 51
T1
T2
T3
Tw
T4
Case
Case
CLKOUT
Note 2
T4
47
SRDY Note 1
Notes:
1. Normally not ready system
48
2. Normally ready system
Figure 22. Synchronous Ready Waveforms
Am186™CH HDLC Microcontroller Data Sheet
57
Case 11
Tw
Tw
Tw
T4
Case 21
T3
Tw
Tw
T4
1
T2
T3
Tw
T4
Case 42
T1
T2
T3
Tw
Case 51
T1
T2
T3
T4
Case 3
T4
50
CLKOUT
49
ARDY1
(Normally Not-Ready System)
ARDY2
(Normally Ready System)
49
51
50
52
Notes:
1. In a normally not ready system, wait states are added after T3 until tARYCH (49) and tCLARX (50) are met.
2. In a normally ready system, a wait state is added if tARYCH (49) and tARYCHL (51) during T2 or tARYLCL (52)
and tCLARX (50) during T3 are met.
Figure 23.
58
Asynchronous Ready Waveforms
Am186™CH HDLC Microcontroller Data Sheet
Table 17. Bus Hold Timing1
Preliminary
Parameter
No.
5
15
18
58
62
63
64
Symbol
tCLAV
tCLAZ
tCHCSX
tHVCL
tCLHAV
tCHCZ
tCHCV
25 MHz
Description
AD address valid delay
AD address float delay
MCSx/PCSx inactive delay
HOLD setup2
HLDA valid delay
Command lines float delay
Command lines valid delay (after float)
Min
0
0
0
10
0
—
—
40 MHz
Max
20
20
20
—
20
20
25
Min
0
0
0
5
0
—
—
Max
12
12
12
—
12
12
12
50 MHz
(Commercial Only)
Min
Max
0
10
0
10
0
10
5
—
0
10
—
10
—
10
Unit
ns
ns
ns
ns
ns
ns
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
2. This timing must be met to guarantee recognition at the next clock.
Case 1
Ti
Ti
Ti
Case 2
T4
Ti
Ti
CLKOUT
58
HOLD
62
HLDA
15
AD15–AD0, DEN
18
MCS3–MCS0, PCS7–PCS0
A19–A0, S6, RD, WR,
BHE, DT/R, S2–S0, WHB,
WLB, UCS, LCS, ALE
63
Figure 24. Entering Bus Hold Waveforms
Am186™CH HDLC Microcontroller Data Sheet
59
Case 1
Ti
Ti
Ti
T1
Case 2
Ti
Ti
T4
T1
CLKOUT
58
HOLD
62
HLDA
5
AD15–AD0, DEN
MCS3–MCS0, PCS7–PCS0
64
A19–A0, S6, RD, WR,
BHE, DT/R, S2–S0, WHB,
WLB, UCS, LCS, ALE
Figure 25.
60
Exiting Bus Hold Waveforms
Am186™CH HDLC Microcontroller Data Sheet
Table 18.
System Clocks Timing1
Preliminary
Parameter
No.
Symbol
25 MHz
Description
Min
50 MHz
(Commercial Only)
40 MHz
Max
Unit
Min
Max
Min
Max
100
125
80
125
ns
CLKIN Requirements for 4x PLL Mode
36
tCKIN
X1 period2
37
tCLCK
X1 Low time (1.5 V)
45
—
35
—
ns
Not Supported
38
tCHCK
X1 High time (1.5 V)
45
—
35
—
ns
39
tCKHL
X1 fall time
(3.5 to 1.0 V)
—
5
—
5
ns
40
tCKLH
X1 rise time
(1.0 to 3.5 V)
—
5
—
5
ns
CLKIN Requirements for 2x PLL Mode
36
tCKIN
X1 period2
80
125
50
125
40
125
ns
37
tCLCK
X1 Low time (1.5 V)
35
—
20
—
15
—
ns
38
tCHCK
X1 High time (1.5 V)
35
—
20
—
15
—
ns
39
tCKHL
X1 fall time
(3.5 to 1.0 V)
—
5
—
5
—
5
ns
40
tCKLH
X1 rise time
(1.0 to 3.5 V)
—
5
—
5
—
5
ns
CLKIN Requirements for 1x PLL Mode
36
tCKIN
X1 period2
40
60
25
60
37
tCLCK
X1 Low time (1.5 V)
15
—
7.5
—
ns
38
tCHCK
X1 High time (1.5 V)
15
—
7.5
—
ns
39
tCKHL
X1 fall time
(3.5 to 1.0 V)
—
5
—
5
ns
40
tCKLH
X1 rise time
(1.0 to 3.5 V)
—
5
—
5
ns
40
—
25
—
20
—
ns
Not Supported
ns
CLKOUT Timing3
42
tCLCL
CLKOUT period
43
tCLCH
CLKOUT Low time
(CL = 50 pF)
0.5tCLCL–2 =18
—
0.5tCLCL–1.25
=11.25
—
0.5tCLCL–1 = 9
—
ns
44
tCHCL
CLKOUT High time
(CL = 50 pF)
0.5tCLCL–2 =18
—
0.5tCLCL–1.25
=11.25
—
0.5tCLCL–1 = 9
—
ns
45
tCH1CH2
CLKOUT rise time
(1.0 to 3.5 V)
—
3
—
3
—
3
ns
46
tCL2CL1
CLKOUT fall time
(3.5 to 1.0 V)
—
3
—
3
—
3
ns
69
tCICO
X1 to CLKOUT skew
—
10
—
10
—
10
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
2. Testing is performed with equal loading on referenced pins.
3. The PLL requires a maximum of 1 ms to achieve lock after all other operating conditions (VCC) are stable, which is normally
achieved by holding RES active for at least 1 ms.
Am186™CH HDLC Microcontroller Data Sheet
61
X2
36
37
38
X1
39
40
46
45
CLKOUT
69
Figure 26.
42
44
System Clocks Waveforms—Active Mode (PLL 1x Mode)
Table 19. PCM Highway Timing (Timing Slave)1,
Parameter
No.
Symbol
43
2
Preliminary
Description
Min
Max
Unit
1
tCLKP
PCM clock period
200
—
ns
2
tWH
PCM clock High
80
—
ns
3
tWL
PCM clock Low
80
—
ns
4
tHCF
Hold time from CLK Low to FSC valid
0
—
ns
5
tDZC
Delay time to valid TXD from CLK
1
25
ns
6
tDZF
Delay time to valid TXD from FSC
1
25
ns
7
tSUFC
Setup time for FSC High to CLK Low
35
—
ns
8
tDCD
Delay time from CLK High to TXD valid
1
25
ns
9
tSUDC
Setup time from RXD valid to CLK
35
—
ns
10
tHCD
Hold time from CLK Low to RXD invalid
5
—
ns
11
tDCT
Delay to TSC valid from CLK
1
25
ns
12
tDFT
Delay to TSC valid from FSC
1
25
ns
Delay from CLK Low of last bit to TSC invalid
1
25
ns
Hold time from CLK Low to FSC invalid
0
—
ns
13
tDCLT
14
tHFI
15
tSYNSS
Time between successive synchronization pulses
16
—
CLK
16
tWSYN
FSC width invalid
8
—
CLK
17
tDTW3
Delay from last bit CLK Low to TXD weak drive
1
25
ns
18
tDTZ
Delay from last bit CLK (plus 1) High to TXD disable
1
25
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
2. TXD becomes valid after the CLK rising edge or FSC enable, whichever is later.
3. During the second half of the last bit transmittal, TXD is driven weak so that other devices can safely drive during this time.
62
Am186™CH HDLC Microcontroller Data Sheet
15
1
16
7
PCM_CLK_x
8
6
4
5
14
1
2
2
18
9
17
10
3
3
4
n
n+1
PCM_FSC_x
PCM_TXD_x
PCM_RXD_x
11
12
13
PCM_TSC_x
Notes:
The PCM_TXD_x outputs three-state. In the signal description and pin list summary tables, PCM_TXD_x is listed as
O-LS-OD (totem pole output/programmable to hold last state of pin/open drain output) because of the following design characteristic:
On the last bit to be transmitted in PCM Highway mode, PCM_TXD_x will be driven normally during the first 1/2 bit time. During
the last 1/2 bit time of the last bit of the transmission, PCM_TXD_x control will be in the hold-last-state condition (LS). In this
condition, the output is driven, but at a much weaker strength. This permits another device (external to the microcontroller) to
start driving during this time without bus contention problems. After this 1/2 bit time of hold-last-state condition, the PCM_TXD_x
pin will be fully three-stated.
In some applications, several PCM Highway devices may have their PCM_TXD pins tied together. The time slot assigners
should be programmed so that only one device is active at any time.
The PCM_TSC_x signal permits external bus drivers, possibly to go external to the board. Each PCM_TSC_x signal is opendrain so that multiple PCM_TSC_x pins can be connected together. For example, two Am186CH microcontrollers could be connected on the same PCM Highway and (with proper configuration of the time slot assigners) could occupy different time slots.
An external bus driver would need to be active for both Am186CH time slots. The open drain on the PCM_TSC_x pins permits
them to be wired together to achieve this.
Figure 27.
PCM Highway Waveforms (Timing Slave)
Am186™CH HDLC Microcontroller Data Sheet
63
Table 20.
PCM Highway Timing (Timing Master)1
Parameter
No.
Symbol
1
tDCFH
2
tDCFL
Preliminary
Description
Unit
Min
Max
Delay time from CLK High to FSC High
0
30
ns
Delay time from CLK High to FSC Low
0
30
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
1
2
PCM_CLK_x
PCM_FSC_x
Figure 28.
64
PCM Highway Waveforms (Timing Master)
Am186™CH HDLC Microcontroller Data Sheet
Table 21. DCE Interface Timing1,
2
Parameter
No.
Symbol
Description
1
tTCLKPER
Preliminary
Unit
Min
Max
DCE clock period
95
—
ns
2
tTCLKH
DCE clock High
40
—
ns
3
tTCLKL
DCE clock Low
40
—
ns
4
tTCLKO
DCE clock to output delay
1
20
ns
5
tTCLKSU
DCE clock setup
15
—
ns
6
tTCLKHD
DCE clock hold
5
—
ns
7
tTCLKR
DCE clock rise/fall
—
10
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
2. Timings are shown with TCLK and RCLK in the default mode without the optional clock inversion.
7
1
DCE_TCLK_x
2
4
DCE_TXD_x
7
3
4
5
6
DCE_CTS_x
Figure 29.
DCE Transmit Waveforms
7
1
DCE_RCLK_x
5
DCE_RXD_x
DCE_RTR_x
2
6
7
3
5
4
4
Figure 30.
DCE Receive Waveforms
Am186™CH HDLC Microcontroller Data Sheet
65
Table 22.
SSI Timing1
Preliminary
Parameter
25 MHz
Description
40 MHz
50 MHz
(Commercial Only)
Unit
No.
Symbol
Min
Max
Min
Max
Min
Max
1
tCLEV
CLKOUT Low to SDEN valid
0
20
0
12
0
10
ns
2
tCLSL
CLKOUT Low to SCLK Low
0
20
0
15
0
12
ns
3
tDVSH
Data valid to SCLK High
10
—
5
—
5
—
ns
4
tSHDX
SCLK High to data invalid
3
—
2
—
2
—
ns
5
tSLDV
SCLK Low to data valid
—
20
—
12
—
10
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
CLKOUT
1
SDEN
2
2
3
SCLK
4
SDATA (RX)
5
SDATA (TX)
Notes:
1. SDEN is configured to be active High.
2. SCLK is configured to be CLKOUT/2.
3. Waveforms are shown for “normal” clock mode (i.e., transmit on negative edge of SCLK and receive on positive edge
of SCLK).
Figure 31.
66
SSI Waveforms
Am186™CH HDLC Microcontroller Data Sheet
Table 23.
DRAM Timing1
Preliminary
Parameter
25 MHz
Description
40 MHz
50 MHz
(Commercial Only)
Unit
No.
Symbol
Min
Max
Min
Max
Min
Max
1
tDVCL
Data in setup
10
—
5
—
5
—
ns
2
tCLDX
Data in hold
3
—
2
—
2
—
ns
5
tCLAV
AD address valid delay
0
20
0
12
0
10
ns
7
tCLDV
Data valid delay
0
20
0
12
0
10
ns
15
tCLAZ
AD address float delay
0
20
0
12
0
10
ns
20
tCVCTV
Control active delay 1
0
20
0
12
0
10
ns
25
tCLRL
RD active delay
0
20
0
12
0
10
ns
27
tCLRH
RD inactive delay
0
20
0
12
0
10
ns
30
tCLDOX
Data hold time
0
—
0
—
0
—
ns
31
tCVCTX
Control inactive delay
0
20
0
12
0
10
ns
68
tCHAV
CLKOUT High to A address valid
0
20
0
12
0
10
ns
402
tCOLV
Column address valid delay
0
20
0
12
0
10
ns
403
tCHRAS
Change in RAS delay
3
20
3
12
3
10
ns
404
tCHCAS
Change in CAS delay
3
20
3
12
3
10
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
Am186™CH HDLC Microcontroller Data Sheet
67
T4
T1
T2
T3
T4
1
2
CLKOUT
5
15
AD15–AD0
Addr.
Data
68
402
A17, A15, A13, A11,
A9, A7, A5, A3, A1
Row
Column
403
403
RAS0, RAS1
404
404
CAS0, CAS1
25
27
RD
Figure 32.
DRAM Read Cycle without Wait States Waveform
T4
T1
T2
TW
T3
T4
1
2
CLKOUT
5
AD15–AD0
15
Addr.
68
A17, A15, A13, A11,
A9, A7, A5, A3, A1
DATA
402
Column
Row
403
403
RAS0, RAS1
404
404
CAS0, RAS1
25
RD
Figure 33.
68
DRAM Read Cycle with Wait States Waveform
Am186™CH HDLC Microcontroller Data Sheet
27
T4
T1
T2
T3
T4
CLKOUT
5
7
AD15–AD0
30
Data
Addr.
402
68
A17, A15, A13, A11,
A9, A7, A5, A3, A1
Row
Column
403
403
RAS0, RAS1
404
404
CAS0, CAS1
20
31
WR
Figure 34. DRAM Write Cycle without Wait States Waveform
T4
T1
T2
TW
T3
T4
CLKOUT
5
7
30
AD15–AD0
68
A17, A15, A13, A11,
A9, A7, A5, A3, A1
Data
Addr.
402
Row
Column
403
403
RAS0, RAS1
404
404
CAS0, CAS1
20
31
WR
Figure 35. DRAM Write Cycle with Wait States Waveform
Am186™CH HDLC Microcontroller Data Sheet
69
T4
T1
T2
TW1
TW2
TW3
T3
T4
CLKOUT
5
AD15–AD0
15
Addr.
68
A17, A15, A13, A11,
A9, A7, A5, A3, A1
402
Row (Invalid)
Column (Invalid)
403
403
RAS0, RAS1
404
404
CAS0, CAS1
25
RD
Figure 36.
70
DRAM Refresh Cycle Waveform
Am186™CH HDLC Microcontroller Data Sheet
27
APPENDIX A—PIN TABLES
This appendix contains pin tables for the Am186CH
HDLC microcontroller. Several different tables are
included with the following characteristics:
■ Power-on reset (POR) pin defaults including pin
numbers and multiplexed functions—Table 24 on
page A-2.
■ Multiplexed
page A-5.
signal
■ Pinstraps and
page A-7.
trade-offs—Table 25
pinstrap
options—Table 26
on
on
■ Programmable I/O pins ordered by PIO pin number
and multiplexed signal name, respectively, including
pin numbers, multiplexed functions, and pin
configurations following system reset—Table 27 on
page A-8 and Table 28 on page A-9.
For pin tables showing pins sorted by pin number and
signal name, respectively, see Table 1, “PQFP Pin
Assignments—Sorted by Pin Number” on page 10 and
Table 2, “PQFP Pin Assignments—Sorted by Signal
Name” on page 11.
For s ign al de sc r ipti ons, se e Tabl e 4, “ Si gna l
Descriptions” on page 13.
In all tables the brackets, [ ], indicate alternate,
multiplexed functions, and braces, { }, indicate reset
configuration pins (pinstraps). The line over a pin name
indicates an active Low. The word pin refers to the
physical wire; the word signal refers to the electrical
signal that flows through it.
■ Pin and signal summary showing signal name and
alternate function, pin number, I/O type, maximum
load values, POR default function, reset state, POR
default operation, hold state, and voltage column—
Table 30 on page A-11.
Am186™CH HDLC Microcontroller Data Sheet
A-1
Table 24.
POR Default
Power-On Reset (POR) Pin Defaults1
Pin
Number
Multiplexed
Signal
Multiplexed
Signal
Multiplexed
Signal
PIO
Pinstrap
30
31
32
36
37
42
43
44
45
49
50
64
65
69
70
84
85
88
89
90
28
34
38
46
51
66
86
92
29
35
39
47
52
67
87
93
19
14
20
94
18
105
17
98
99
97
57
56
55
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PIO33
PIO8
PIO34
—
PIO30
—
PIO29
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
{ADEN}
—
—
—
—
—
{CLKSEL1}
—
—
—
—
Bus Interface Unit
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
ALE
ARDY
BHE
BSIZE8
DEN
DRQ1
DT/R
HLDA
HOLD
RD
S0
S1
S2
A-2
Am186™CH HDLC Microcontroller Data Sheet
Table 24.
POR Default
Pin
Number
54
15
95
96
16
Power-On Reset (POR) Pin Defaults1 (Continued)
Multiplexed
Signal
—
—
—
—
—
S6
SRDY
WHB
WLB
WR
Chip Selects
LCS
131
RAS0
127
CAS1
MCS1
MCS2
128
CAS0
PCS0
5
—
6
—
PCS1
PCS2
7
—
PCS3
8
—
132
—
UCS
Reset/Clocks
CLKOUT
60
—
RES
114
—
RESOUT
58
—
X1
73
—
X2
74
—
Interrupts
INT0
107
—
INT1
109
—
INT2
110
—
INT3
111
—
INT4
112
—
INT5
113
—
NMI
115
—
Synchronous Communications Interfaces
Channel A (DCE)
DCE_RXD_A
118
PCM_RXD_A
DCE_TXD_A
119
PCM_TXD_A
DCE_RCLK_A
117
PCM_CLK_A
DCE_TCLK_A
116
PCM_FSC_A
High-Speed UART
TXD_HU
26
—
Debug Support
QS0
62
—
QS1
63
—
PIOs
PIO0
144
TMRIN1
PIO1
143
TMROUT1
PIO2
10
PCS5
PIO3
9
PCS4
PIO4
126
MCS0
PIO5
129
MCS3
PIO6
147
INT8
PIO7
146
INT7
PIO9
124
DRQ0
PIO10
2
SDEN
Multiplexed
Signal
—
—
—
—
—
Multiplexed
Signal
—
—
—
—
—
PIO
Pinstrap
—
PIO35
—
—
PIO15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PIO13
PIO14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
{ONCE}
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RAS1
PWD
—
—
—
—
—
—
—
—
—
—
—
—
—
Am186™CH HDLC Microcontroller Data Sheet
—
—
—
{CLKSEL2}
{UCSX8}
—
—
—
—
—
A-3
Table 24.
POR Default
PIO11
PIO12
PIO16
PIO17
PIO18
PIO19
PIO20
PIO21
PIO22
PIO23
PIO24
PIO25
PIO26
PIO27
PIO28
PIO31
PIO32
PIO36
PIO37
PIO38
PIO39
PIO40
PIO41
PIO42
PIO43
PIO44
PIO45
PIO46
PIO47
Reserved
RSVD_104
RSVD_103
RSVD_102
RSVD_101
RSVD_81
RSVD_80
RSVD_76
RSVD_75
Power-On Reset (POR) Pin Defaults1 (Continued)
Pin
Number
3
4
25
123
122
145
159
22
150
149
157
156
158
142
141
13
11
138
139
137
136
135
134
153
154
152
151
24
23
Multiplexed
Signal
SCLK
SDATA
RXD_HU
DCE_CTS_A
DCE_RTR_A
INT6
TXD_U
UCLK
—
—
CTS_U
RTR_U
RXD_U
TMRIN0
TMROUT0
PCS7
PCS6
DCE_RXD_B
DCE_TXD_B
DCE_CTS_B
DCE_RTR_B
DCE_RCLK_B
DCE_TCLK_B
—
—
—
—
CTS_HU
RTR_HU
Multiplexed
Signal
—
—
—
PCM_TSC_A
—
—
—
—
—
—
—
—
—
—
—
—
—
PCM_RXD_B
PCM_TXD_B
PCM_TSC_B
—
PCM_CLK_B
PCM_FSC_B
—
—
—
—
—
—
Multiplexed
Signal
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
104
103
102
101
81
80
76
75
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PIO
Notes:
1. For default reset functions and pin states refer to Table 30, “Pin List Summary,” on page A-11.
A-4
Am186™CH HDLC Microcontroller Data Sheet
Pinstrap
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table 25. Multiplexed Signal Trade-Offs
DESIRED FUNCTION
Interface
LOST FUNCTION
Name
Pin
Interface
DRAM
Name
Interface
Name
Interface
Name
Interface
Name
Memory
SRAM
DRAM
LCS
131
RAS0
—
—
—
—
MCS1
127
CAS1
—
—
—
—
PIO
—
—
MCS2
128
CAS0
—
—
—
—
—
RAS1
—
—
—
—
MCS2
—
—
—
—
—
—
MCS1
—
—
—
—
—
—
MCS3
129
CAS0
128
CAS1
127
RAS0
131
LCS
—
—
—
—
—
—
RAS1
129
MCS3
—
—
—
—
—
PIO5
PCM_RXD_A
—
—
—
PCM_TXD_A
—
—
—
—
PCM_CLK_A
—
—
—
—
SRAM
PIO5
Synchronous Communications Interfaces
DCE
Channel
A
DCE
Channel
B
PCM
Channel
A
PCM
Channel
B
LowSpeed
UART
HighSpeed
UART
DCE_RXD_A
118
DCE_TXD_A
119
PCM
Channel
A
DCE_RCLK_A
117
DCE_TCLK_A
116
PCM_FSC_A
—
—
—
—
DCE_CTS_A
123
PCM_TSC_A
—
—
—
PIO17
DCE_RTR_A
122
—
—
—
—
DCE_RXD_B
138
PCM_RXD_B
—
—
—
—
DCE_TXD_B
139
PCM_TXD_B
—
—
—
—
PCM
Channel
B
—
PIO
—
PIO18
PIO
PIO36
PIO37
DCE_RCLK_B
135
PCM_CLK_B
—
—
—
—
PIO40
DCE_TCLK_B
134
PCM_FSC_B
—
—
—
—
PIO41
DCE_CTS_B
137
PCM_TSC_B
—
—
—
—
PIO38
DCE_RTR_B
136
—
—
—
—
—
PIO39
DCE_RXD_A
—
—
—
DCE_TXD_A
—
—
—
DCE_RCLK_A
—
—
DCE_TCLK_A
—
—
PCM_RXD_A
118
PCM_TXD_A
119
PCM_CLK_A
117
PCM_FSC_A
116
PCM_TSC_A
123
PCM_RXD_B
138
PCM_TXD_B
139
PCM_CLK_B
135
DCE
Channel
A
DCE
Channel
B
—
PIO
—
—
—
—
—
—
DCE_CTS_A
—
—
DCE_RXD_B
—
—
—
—
—
PIO17
DCE_TXD_B
—
—
—
—
PIO37
DCE_RCLK_B
—
—
—
—
PIO40
PIO
PIO36
PCM_FSC_B
134
DCE_TCLK_B
—
—
—
—
PIO41
PCM_TSC_B
137
DCE_CTS_B
—
—
—
—
PIO38
RXD_U
158
—
—
—
—
—
—
TXD_U
159
—
—
—
—
—
—
PIO20
RTR_U
156
—
—
—
—
—
—
PIO25
CTS_U
157
—
—
—
—
—
—
RXD_HU
25
—
—
—
—
—
—
RTR_HU
23
—
—
—
—
—
—
PIO47
CTS_HU
24
—
—
—
—
—
—
PIO46
DEN
18
DS
—
—
—
—
—
PIO30
DS
18
Bus
Interface
DEN
—
—
—
—
—
PIO30
PIO0
144
TMRIN1
—
—
PIO1
143
TMROUT1
—
—
PIO2
10
PCS5
—
—
PIO3
9
PCS4
—
—
PIO4
126
MCS0
—
—
PIO5
129
MCS3
PIO
PIO26
PIO24
PIO
PIO16
Miscellaneous
Bus
Interface
PIOs
RAS1
Am186™CH HDLC Microcontroller Data Sheet
—
A-5
Table 25. Multiplexed Signal Trade-Offs (Continued)
DESIRED FUNCTION
Interface
A-6
LOST FUNCTION
Name
Pin
Interface
Name
Interface
Name
Interface
PIO6
147
INT8
PIO7
146
INT7
—
—
PIO8
14
ARDY
—
—
PIO9
124
DRQ0
—
—
PIO10
2
SDEN
—
—
PIO11
3
SCLK
—
—
PIO12
4
SDATA
—
—
PIO13
5
PCS0
—
—
PIO14
6
PCS1
—
—
PIO15
16
WR
—
—
PIO16
25
RXD_HU
—
—
PIO17
123
DCE_CTS_A
PCM_TSC_A
—
PIO18
122
DCE_RTR_A
—
—
PIO19
145
INT6
—
—
PIO20
159
TXD_U
—
—
PIO21
22
UCLK
—
—
PIO22
150
—
—
—
PIO23
149
—
—
—
PIO24
157
CTS_U
—
—
PIO25
156
RTR_U
—
—
PIO26
158
RXD_U
—
—
PIO27
142
TMRIN0
—
—
PIO28
141
TMROUT0
—
—
PIO29
17
DT/R
—
—
PIO30
18
DEN
PIO31
13
PCS7
—
—
PIO32
11
PCS6
—
—
PIO33
19
ALE
—
—
PIO34
20
BHE
—
—
PIO35
15
SRDY
—
—
PIO36
138
DCE_RXD_B
PCM_RXD_B
—
PIO37
139
DCE_TXD_B
PCM_TXD_B
—
PIO38
137
DCE_CTS_B
PCM_TSC_B
—
PIO39
136
DCE_RTR_B
—
—
PIO40
135
DCE_RCLK_B
PCM_CLK_B
—
PIO41
134
DCE_TCLK_B
PCM_FSC_B
—
PIO42
153
—
—
—
PIO43
154
—
—
—
PIO44
152
—
—
—
PIO45
151
—
—
—
PIO46
24
CTS_HU
—
—
PIO47
23
RTR_HU
—
—
PWD
Name
Interface
—
DS
—
Am186™CH HDLC Microcontroller Data Sheet
Name
Table 26.
Signal Name
{ADEN}
Multiplexed
Signal(s)
BHE
PIO34
Reset Configuration Pins (Pinstraps)1
Description
Address Enable: If {ADEN} is held High or left floating during power-on reset, the
address portion of the AD bus (AD15–AD0) is enabled or disabled during LCS, UCS, or
other memory bus cycles based on how the software configures the DA bit setting. In
this case, the memory address is accessed on the A19–A0 pins. There is a weak
internal pullup resistor on {ADEN} so no external pullup is required. This mode of
operation reduces power consumption.
If {ADEN} is held Low on power-on reset, the AD bus drives both addresses and data,
regardless of how software configures the DA bit setting.
{CLKSEL1}
HLDA
{CLKSEL2}
[PCS4]
PIO3
CPU PLL Mode Select 1 determines the PLL mode for the system clock source.
CPU PLL Mode Select 2 is sampled on the rising edge of reset and determines the PLL
mode for the system clock source. This pin has an internal pullup resistor that is active
only during reset. There are four CPU PLL modes that are selected by the values of
{CLKSEL1} and {CLKSEL2} as shown below. (For details on clocks see “Clock
Generation and Control” on page 33.)
CPU PLL Modes
{CLKSEL1}
1
1
0
0
{CLKSEL2}
1
0
1
0
CPU PLL Mode
2X, CPU PLL enabled (default)
4X, CPU PLL enabled
1X, CPU PLL enabled
PLL Bypass
{ONCE}
UCS
ONCE Mode Request asserted Low places the Am186CH HDLC microcontroller into
ONCE mode. Otherwise, the controller operates normally. In ONCE mode, all pins are
three-stated and remain in that state until a subsequent reset occurs. To guarantee that
the controller does not inadvertently enter ONCE mode, {ONCE} has a weak internal
pullup resistor that is active only during a reset. A reset ending ONCE mode should be as
long as a power-on reset so that the PLL will stabilize.
{UCSX8}
[MCS0]
PIO4
Upper Memory Chip Select, 8-Bit Bus asserted Low configures the upper chip select
region for an 8-bit bus size. This pin has a pullup resistor that is active only during reset,
so no external pullup is required to set the bus to 16-bit mode.
Notes:
1. A pinstrap is used to enable or disable features based on the state of the pin during an external reset. The pinstrap must be
held in its desired state for at least 4.5 clock cycles after the deassertion of RES. The pinstraps are sampled in an external
reset only (when RES is asserted), not during an internal watchdog timer-generated reset.
Am186™CH HDLC Microcontroller Data Sheet
A-7
Table 27.
PIO No.
PIO0
PIO1
PIO2
PIO3
PIO4
PIO5
PIO6
PIO7
PIO8
PIO9
PIO10
PIO11
PIO12
PIO13
PIO14
PIO15
PIO16
PIO17
PIO18
PIO19
PIO20
PIO21
PIO22
PIO23
PIO24
PIO25
PIO26
PIO27
PIO28
PIO29
PIO30
PIO31
PIO32
PIO33
PIO34
PIO35
PIO36
PIO37
PIO38
PIO39
PIO40
PIO41
PIO42
PIO43
PIO44
PIO45
PIO46
PIO47
Pin No.
144
143
10
9
126
129
147
146
14
124
2
3
4
5
6
16
25
123
122
145
159
22
150
149
157
156
158
142
141
17
18
13
11
19
20
15
138
139
137
136
135
134
153
154
152
151
24
23
Multiplexed Signal
TMRIN1
TMROUT1
PCS5
PCS4
MCS0
MCS3
INT8
INT7
ARDY
DRQ0
SDEN
SCLK
SDATA
PCS0
PCS1
WR
RXD_HU
DCE_CTS_A
DCE_RTR_A
INT6
TXD_U
UCLK
—
—
CTS_U
RTR_U
RXD_U
TMRIN0
TMROUT0
DT/R
DEN
PCS7
PCS6
ALE
BHE
SRDY
DCE_RXD_B
DCE_TXD_B
DCE_CTS_B
DCE_RTR_B
DCE_RCLK_B
DCE_TCLK_B
—
—
—
—
CTS_HU
RTR_HU
PIOs Sorted by PIO Number
Multiplexed Signal
—
—
—
—
—
RAS1
PWD
—
—
—
—
—
—
—
—
—
—
PCM_TSC_A
—
—
—
—
—
—
—
—
—
—
—
—
DS
—
—
—
—
—
PCM_RXD_B
PCM_TXD_B
PCM_TSC_B
—
PCM_CLK_B
PCM_FSC_B
—
—
—
—
—
—
Multiplexed Signal
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Pin Configuration Following
System Reset1
Input with pullup
Input with pulldown
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Alternate operation2
Input with pulldown
Input with pulldown
Input with pullup
Input with pullup
Alternate operation2
Alternate operation2
Alternate operation2
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pulldown
Input with pulldown
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pulldown
Alternate operation2
Alternate operation2
Input with pullup
Input with pullup
Alternate operation3
Alternate operation2
Alternate operation2
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pulldown
Input with pulldown
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Notes:
1. System reset is defined as a power-on reset (i.e., the RES input pin transitioning from its Low to High state) or a reset due to
a watchdog timer timeout.
2. When used as a PIO, input with pullup option available.
3. When used as a PIO, input with a pulldown option available.
A-8
Am186™CH HDLC Microcontroller Data Sheet
Table 28.
Signal
ALE
ARDY
BHE
CTS_HU
CTS_U
DCE_CTS_A
DCE_CTS_B
DCE_RCLK_B
DCE_RTR_A
DCE_RTR_B
DCE_RXD_B
DCE_TCLK_B
DCE_TXD_B
DEN
DRQ0
DT/R
INT6
INT7
INT8
MCS0
MCS3
PCS0
PCS1
PCS4
PCS5
PCS6
PCS7
PIO22
PIO23
PIO42
PIO43
PIO44
PIO45
RTR_HU
RTR_U
RXD_HU
RXD_U
SCLK
SDATA
SDEN
SRDY
TMRIN0
TMRIN1
TMROUT0
TMROUT1
TXD_U
UCLK
UCLK
WR
PIO No.
Pin No.
PIO33
PIO8
PIO34
PIO46
PIO24
PIO17
PIO38
PIO40
PIO18
PIO39
PIO36
PIO41
PIO37
PIO30
PIO9
PIO29
PIO19
PIO7
PIO6
PIO4
PIO5
PIO13
PIO14
PIO3
PIO2
PIO32
PIO31
—
—
—
—
—
—
PIO47
PIO25
PIO16
PIO26
PIO11
PIO12
PIO10
PIO35
PIO27
PIO0
PIO28
PIO1
PIO20
PIO21
PIO21
PIO15
19
14
20
24
157
123
137
135
122
136
138
134
139
18
124
17
145
146
147
126
129
5
6
9
10
11
13
150
149
153
154
152
151
23
156
25
158
3
4
2
15
142
144
141
143
159
22
22
16
PIOs Sorted by Signal Name
Multiplexed Signal
Multiplexed Signal
—
—
—
—
—
PCM_TSC_A
PCM_TSC_B
PCM_CLK_B
—
—
PCM_RXD_B
PCM_FSC_B
PCM_TXD_B
DS
—
—
—
—
PWD
—
RAS1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Pin Configuration Following
System Reset1
Alternate operation2
Alternate operation3
Alternate operation3
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Alternate operation3
Input with pulldown
Alternate operation3
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Alternate operation3
Alternate operation3
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pulldown
Input with pulldown
Input with pulldown
Input with pulldown
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pulldown
Alternate operation3
Input with pullup
Input with pullup
Input with pulldown
Input with pulldown
Input with pullup
Input with pullup
Input with pullup
Alternate operation3
Notes:
1. System reset is defined as a power-on reset (i.e., the RES input pin transitioning from its Low to High state) or a reset due to
a watchdog timer timeout.
2. When used as a PIO, input with a pulldown option available.
3. When used as a PIO, input with a pullup option available.
Am186™CH HDLC Microcontroller Data Sheet
A-9
Table 29. Pin List Table Definitions
Pin List Table Column Definitions
The following paragraphs describe the individual
columns of information in Table 30, “Pin List Summary,”
on page A-11. The pins are grouped alphabetically by
function.
Type
B
Bidirectional
Note: All maximum delay numbers should be increased by 0.035 ns for every pF of load (up to a maximum of 150 pF) over the maximum load specified in
Table 30.
H
High
LS
Programmable to hold last state of pin
O
Totem pole output
OD
Open drain output
Column #1—Signal Name, [Alternate Function],
{Pinstrap}
This column denotes the primar y and alternate
functions of the pins. Most of the pins that have
alternate functions are configured for these functions
via firmware modifying values in the Peripheral Control
Block. Refer to the Am186™CC/CH/CU
Microcontrollers Register Set Manual, order #21916,
for full documentation of this process.
Brackets, [ ], are used to indicate the alternate,
multiplexed function of a pin (i.e., not power-on reset
default).
Braces, { }, are used to indicate the functionality of a pin
only during a processor reset. These signals are called
pinstraps. To select the desired configuration, the
pinstraps are terminated internally with pullup resistors
or externally with pulldown resistors. Their state is
sampled during a processor reset and latched on the
rising edge of reset. The signals must be held in the
desired state for 4.5 system clock cycles after the
deassertion of reset. Based on the pinstrap’s state at
the time they are latched, certain features of the
Am186CH HDLC microcontroller are enabled or
d i s a bl e d . A l l ex t e r n a l t e r m i n a t i o n s h o u l d b e
implemented with 10-Kohm resistors on these signals.
T h e pi ns tr a p s a r e l i s t e d i n Ta bl e 2 6 , “ R e s e t
Configuration Pins (Pinstraps),” on page A-7.
Column #2—Pin No.
Definition
[]
Pin alternate function
{}
Pinstrap pin
OD-O
Open drain output or totem pole output
PD
Internal pulldown resistor
PU
Internal pullup resistor
STI
STI-OD
TS
Schmitt trigger Input
Schmitt trigger input or open drain output
Three-state output
Column #4—Max Load (pF)
The Max Load column designates the capacitive load
at which the I/O timing for that pin is guaranteed.
Column #5—POR Default Function
The POR Default Function column shows the status of
these pins after a power-on reset. In some cases the
pin is the function outlined in the “Signal Name” column
of the table. The signal name is listed in the POR
Default Function column if the signal is the default
function and not a PIO after a processor reset. In other
cases the pin is a PIO configured as an input.
Column #6—Reset State
The Reset State column indicates the termination
present on the signal at reset (pullup or pulldown) and
indicates whether the signal is a three-stated output or
a Sc hmitt tr igger input. Refer to Table 29 for
abbreviations used in this column.
Column #7—POR Default Operation
The pin number column identifies the pin number of the
individual I/O signal on the package.
The POR Default Operation column describes the type
of input and/or output that is default pin operation.
Refer to Table 29 for abbreviations used in this column.
Column #3—Type
Column #8—Hold State
Definitions of the abbreviations in the Type column are
shown in Table 29.
The Hold State column shows the state of the pin in
hold state. Refer to Table 29 for abbreviations used in
this column.
Column #9—5 V
A "5 V" in the 5-V column indicates 5-V tolerant inputs.
These inputs are not damaged and do not draw excess
power when driven with levels up to VCC + 2.6 volts.
These pins only drive to VCC.
A-10
Am186™CH HDLC Microcontroller Data Sheet
Table 30.
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No.
Type
Pin List Summary
Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State
5V
BUS INTERFACE/GENERAL-PURPOSE DMA REQUEST
A0
30
O
70
A0
TS-PD
O
TS-PD
5V
A1
31
O
70
A1
TS-PD
O
TS-PD
5V
A2
32
O
70
A2
TS-PD
O
TS-PD
5V
A3
36
O
70
A3
TS-PD
O
TS-PD
5V
A4
37
O
70
A4
TS-PD
O
TS-PD
5V
A5
42
O
70
A5
TS-PD
O
TS-PD
5V
A6
43
O
70
A6
TS-PD
O
TS-PD
5V
A7
44
O
70
A7
TS-PD
O
TS-PD
5V
A8
45
O
70
A8
TS-PD
O
TS-PD
5V
A9
49
O
70
A9
TS-PD
O
TS-PD
5V
A10
50
O
70
A10
TS-PD
O
TS-PD
5V
A11
64
O
70
A11
TS-PD
O
TS-PD
5V
A12
65
O
70
A12
TS-PD
O
TS-PD
5V
A13
69
O
70
A13
TS-PD
O
TS-PD
5V
A14
70
O
70
A14
TS-PD
O
TS-PD
5V
A15
84
O
70
A15
TS-PD
O
TS-PD
5V
A16
85
O
70
A16
TS-PD
O
TS-PD
5V
A17
88
O
70
A17
TS-PD
O
TS-PD
5V
A18
89
O
70
A18
TS-PD
O
TS-PD
5V
A19
90
O
70
A19
TS-PD
O
TS-PD
5V
AD0
28
B
70
AD0
TS-PD
B
TS
5V
AD1
34
B
70
AD1
TS-PD
B
TS
5V
AD2
38
B
70
AD2
TS-PD
B
TS
5V
AD3
46
B
70
AD3
TS-PD
B
TS
5V
AD4
51
B
70
AD4
TS-PD
B
TS
5V
AD5
66
B
70
AD5
TS-PD
B
TS
5V
AD6
86
B
70
AD6
TS-PD
B
TS
5V
AD7
92
B
70
AD7
TS-PD
B
TS
5V
AD8
29
B
70
AD8
TS-PD
B
TS
5V
AD9
35
B
70
AD9
TS-PD
B
TS
5V
AD10
39
B
70
AD10
TS-PD
B
TS
5V
AD11
47
B
70
AD11
TS-PD
B
TS
5V
AD12
52
B
70
AD12
TS-PD
B
TS
5V
AD13
67
B
70
AD13
TS-PD
B
TS
5V
AD14
87
B
70
AD14
TS-PD
B
TS
5V
AD15
93
B
70
AD15
TS-PD
B
TS
5V
ALE
[PIO33]
19
O
STI-PD [STI] [O]
50
ALE
TS-PD
O
TS-PD
5V
ARDY
[PIO8]
14
STI-PU
STI-PU [STI] [O]
50
ARDY
STI-PU
STI-PU
STI
5V
Am186™CH HDLC Microcontroller Data Sheet
A-11
Table 30. Pin List Summary (Continued)
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No.
BHE
[PIO34]
{ADEN}
20
BSIZE8
Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State
5V
O
STI-PU [STI] [O]
STI
50
BHE
STI-PU
O
TS-PU
5V
Type
94
O
50
BSIZE8
TS-PU
O
—
—
DEN
[DS]
[PIO30]
18
O
O
STI-PU [STI] [O]
50
DEN
TS-PU
O
TS-PU
5V
[DRQ0]
PIO9
124
STI-PD
STI-PD [STI] [O]
50
PIO9
STI-PD
STI-PD [STI] [O]
—
5V
DRQ1
105
STI-PD
—
DRQ1
STI-PD
STI-PD
—
5V
DT/R
[PIO29]
17
O
STI-PU [STI] [O]
50
DT/R
TS-PU
O
TS-PU
5V
HLDA
{CLKSEL1}
98
O
STI
50
HLDA
STI-PU
O
H
5V
HOLD
99
STI
—
HOLD
STI-PD
STI
H
5V
RD
97
O
70
RD
TS-PU
O
TS-PU
5V
S0
57
O
50
S0
STI-PU
O
TS
5V
S1
56
O
50
S1
TS-PU
O
TS
5V
S2
55
O
50
S2
TS-PU
O
TS
5V
S6
54
O
50
S6
TS-PD
O
TS
5V
SRDY
[PIO35]
15
STI-PU
STI-PU [STI] [O]
50
SRDY
STI-PU
STI-PU
—
5V
WHB
95
O
70
WHB
TS-PU
O
TS-PU
5V
WLB
96
O
70
WLB
TS-PU
O
TS-PU
5V
16
O
STI-PU [STI] [O]
50
WR
STI-PU
O
TS-PU
5V
LCS
[RAS0]
131
O
O
50
LCS
TS-PU
O
TS-PU
5V
[MCS0]
PIO4
{UCSX8}
126
O
STI-PU [STI] [O]
STI
50
PIO4
STI-PU
STI-PU [STI] [O]
TS-PU
5V
MCS1
[CAS1]
127
O
O
50
MCS1
TS-PU
O
TS-PU
5V
MCS2
[CAS0]
128
O
O
50
MCS2
TS-PU
O
TS-PU
5V
[MCS3]
[RAS1]
PIO5
129
O
O
STI-PU [STI] [O]
50
PIO5
STI-PU
STI-PU [STI] [O]
TS-PU
5V
PCS0
[PIO13]
5
O
STI-PU [STI] [O]
50
PCS0
STI-PU
O
TS-PU
5V
PCS1
[PIO14]
6
O
STI-PU [STI] [O]
50
PCS1
STI-PU
O
TS-PU
5V
PCS2
7
O
50
PCS2
TS-PU
O
TS-PU
5V
PCS3
8
O
50
PCS3
TS-PU
O
TS-PU
5V
WR
[PIO15]
CHIP SELECTS
A-12
Am186™CH HDLC Microcontroller Data Sheet
Table 30. Pin List Summary (Continued)
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No.
Type
Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State
5V
[PCS4]
PIO3
{CLKSEL2}
9
O
STI-PU [STI] [O]
STI
50
PIO3
STI-PU
STI-PU [STI] [O]
TS-PU
5V
[PCS5]
PIO2
10
O
STI-PU [STI] [O]
50
PIO2
STI-PU
O
TS-PU
5V
[PCS6]
PIO32
11
O
STI-PU [STI] [O]
50
PIO32
STI-PU
STI-PU [STI] [O]
TS-PU
5V
[PCS7]
PIO31
13
O
STI-PU [STI] [O]
50
PIO31
STI-PU
STI-PU [STI] [O]
TS-PU
5V
UCS
{ONCE}
132
O
STI
50
UCS
STI-PU
O
TS-PU
5V
CLOCKS/RESET/WATCHDOG TIMER
CLKOUT
60
O
70
CLKOUT
—
O
—
—
RES
114
ST
—
RES
STI
STI
—
5V
RESOUT
58
O
50
RESOUT
H
O
—
5V
[UCLK]
PIO21
22
STI
STI-PU [STI] [O]
50
PIO21
STI-PU
STI-PU [STI] [O]
—
5V
X1
73
STI
—
X1
—
STI
—
—
X2
74
O
—
X2
—
O
—
—
PROGRAMMABLE TIMERS
[PWD]
[INT8]
PIO6
147
STI
STI
STI-PU [STI] [O]
50
PIO6
STI-PU
STI-PU [STI] [O]
—
5V
[TMRIN0]
PIO27
142
STI-PU
STI-PU [STI] [O]
50
PIO27
STI-PU
STI-PU [STI] [O]
—
5V
[TMRIN1]
PIO0
144
STI-PU
STI-PU [STI] [O]
50
PIO0
STI-PU
STI-PU [STI] [O]
—
5V
[TMROUT0]
PIO28
141
O
STI-PD [STI] [O]
50
PIO28
STI-PD
STI-PD [STI] [O]
TS
5V
[TMROUT1]
PIO1
143
O
STI-PD [STI] [O]
50
PIO1
STI-PD
STI-PD [STI] [O]
TS
5V
INT0
107
STI
—
INT0
STI-PU
STI
—
5V
INT1
109
STI
—
INT1
STI-PU
STI
—
5V
INT2
110
STI
—
INT2
STI-PU
STI
—
5V
INT3
111
STI
—
INT3
STI-PU
STI
—
5V
INT4
112
STI
—
INT4
STI-PU
STI
—
5V
INT5
113
STI
—
INT5
STI-PU
STI
—
5V
[INT6]
PIO19
145
STI
STI-PU [STI] [O]
50
PIO19
STI-PU
STI-PU [STI] [O]
—
5V
[INT7]
PIO7
146
STI
STI-PU [STI] [O]
50
PIO7
STI-PU
STI-PU [STI] [O]
—
5V
[INT8]
[PWD]
PIO6
147
STI
STI
STI-PU [STI] [O]
50
PIO6
STI-PU
STI-PU [STI] [O]
—
5V
NMI
115
STI
—
NMI
STI-PU
STI
—
5V
INTERRUPTS
Am186™CH HDLC Microcontroller Data Sheet
A-13
Table 30. Pin List Summary (Continued)
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No.
Type
Max
Load
(pF)
POR
Default
Function
POR
Default
Operation
Reset
State
Hold
State
5V
HIGH-LEVEL DATA LINK CONTROL SYNCHRONOUS COMMUNICATIONS INTERFACES
HDLC Channel A
DCE_RXD_A
[PCM_RXD_A]
118
STI
STI
50
DCE_RXD_A
STI-PU
STI
—
5V
DCE_TXD_A
[PCM_TXD_A]
119
O-OD
O-LS-OD
50
DCE_TXD_A
TS-PU
OD-O
—
5V
DCE_RCLK_A
[PCM_CLK_A]
117
STI
STI
—
DCE_RCLK_A
STI-PU
STI
—
5V
DCE_TCLK_A
[PCM_FSC_A]
116
STI
STI
—
DCE_TCLK_A
STI-PU
STI
—
5V
[DCE_CTS_A]
[PCM_TSC_A]
PIO17
123
STI
OD
STI-PU [STI] [O]
50
PIO17
STI-PU
STI-PU [STI] [O]
—
5V
[DCE_RTR_A]
PIO18
122
O
STI-PU [STI] [O]
30
PIO18
STI-PU
STI-PU [STI] [O]
—
5V
[DCE_RXD_B]
[PCM_RXD_B]
PIO36
138
STI
STI
STI-PU [STI] [O]
50
PIO36
STI-PU
STI-PU [STI] [O]
—
5V
[DCE_TXD_B]
[PCM_TXD_B]
PIO37
139
OD-O
O-LS-OD
STI-PU [STI] [O]
50
PIO37
STI-PU
STI-PU [STI] [O]
—
5V
[DCE_RCLK_B]
[PCM_CLK_B]
PIO40
135
STI
STI
STI-PU [STI] [O]
50
PIO40
STI-PU
STI-PU [STI] [O]
—
5V
[DCE_TCLK_B]
[PCM_FSC_B]
PIO41
134
STI
STI
STI-PU [STI] [O]
50
PIO41
STI-PU
STI-PU [STI] [O]
—
5V
[DCE_CTS_B]
[PCM_TSC_B]
PIO38
137
STI
OD
STI-PU [STI] [O]
50
PIO38
STI-PU
STI-PU [STI] [O]
—
5V
[DCE_RTR_B]
PIO39
136
O
STI-PU [STI] [O]
30
PIO39
STI-PU
STI-PU [STI] [O]
—
5V
HDLC Channel B
ASYNCHRONOUS SERIAL PORTS (UART AND HIGH-SPEED UART)
UART
[RXD_U]
PIO26
158
STI
STI-PU [STI] [O]
50
PIO26
STI-PU
STI-PU [STI] [O]
—
5V
[TXD_U]
PIO20
159
O
STI-PU [STI] [O]
50
PIO20
STI-PU
STI-PU [STI] [O]
—
5V
[CTS_U]
PIO24
157
STI
STI-PU [STI] [O]
50
PIO24
STI-PU
STI-PU [STI] [O]
—
5V
[RTR_U]
PIO25
156
O
STI-PU [STI] [O]
30
PIO25
STI-PU
STI-PU [STI] [O]
—
5V
[RXD_HU]
PIO16
25
STI
STI-PU [STI] [O]
50
PIO16
STI-PU
STI-PU [STI] [O]
—
5V
TXD_HU
26
O
30
TXD_HU
TS-PU
O
—
5V
HIGH-SPEED UART
A-14
Am186™CH HDLC Microcontroller Data Sheet
Table 30. Pin List Summary (Continued)
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No.
[CTS_HU]
PIO46
24
[RTR_HU]
PIO47
Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State
5V
STI
STI-PU [STI] [O]
50
PIO46
STI-PU
STI-PU [STI] [O]
—
5V
23
O
STI-PU [STI] [O]
30
PIO47
STI-PU
STI-PU [STI] [O]
—
5V
QS0
62
O
30
QS0
TS-PD
O
—
5V
QS1
63
O
30
QS1
TS-PD
O
—
5V
Type
DEBUG SUPPORT
SYNCHRONOUS SERIAL INTERFACE (SSI)
[SCLK]
PIO11
3
O
STI-PU [STI] [O]
50
PIO11
STI-PU
STI-PU [STI] [O]
—
5V
[SDATA]
PIO12
4
O
STI-PU [STI] [O]
50
PIO12
STI-PU
STI-PU [STI] [O]
—
5V
[SDEN]
PIO10
2
O
STI-PD [STI] [O]
50
PIO10
STI-PD
STI-PD [STI] [O]
—
5V
RSVD_104
104
—
—
—
—
—
—
—
RSVD_103
103
—
—
—
—
—
—
—
RSVD_102
102
—
—
—
—
—
—
—
RSVD_101
101
—
—
—
—
—
—
—
RSVD_81
81
—
—
—
—
—
—
—
RSVD_80
80
—
—
—
—
—
—
—
RSVD_76
76
—
—
—
—
—
—
—
RSVD_75
75
—
—
—
—
—
—
—
VCC
12
—
—
—
—
—
—
—
VCC
27
—
—
—
—
—
—
—
VCC
40
—
—
—
—
—
—
—
VCC
48
—
—
—
—
—
—
—
VCC
59
—
—
—
—
—
—
—
VCC
68
—
—
—
—
—
—
—
VCC
78
—
—
—
—
—
—
—
VCC
82
—
—
—
—
—
—
—
VCC
91
—
—
—
—
—
—
—
VCC
106
—
—
—
—
—
—
—
VCC
120
—
—
—
—
—
—
—
VCC
125
—
—
—
—
—
—
—
VCC
133
—
—
—
—
—
—
—
VCC
148
—
—
—
—
—
—
—
VCC
160
—
—
—
—
—
—
—
VCC
79
—
—
—
—
—
—
—
VCC_A
77
—
—
—
—
—
—
—
VSS
1
—
—
—
—
—
—
—
VSS
21
—
—
—
—
—
—
—
RESERVED PINS
POWER AND GROUND
Am186™CH HDLC Microcontroller Data Sheet
A-15
Table 30. Pin List Summary (Continued)
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No.
Type
VSS
33
VSS
Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State
5V
—
—
—
—
—
—
—
41
—
—
—
—
—
—
—
VSS
53
—
—
—
—
—
—
—
VSS
61
—
—
—
—
—
—
—
VSS
71
—
—
—
—
—
—
—
VSS
83
—
—
—
—
—
—
—
VSS
100
—
—
—
—
—
—
—
VSS
108
—
—
—
—
—
—
—
VSS
121
—
—
—
—
—
—
—
VSS
130
—
—
—
—
—
—
—
VSS
140
—
—
—
—
—
—
—
VSS
155
—
—
—
—
—
—
—
VSS_A
72
—
—
—
—
—
—
—
A-16
Am186™CH HDLC Microcontroller Data Sheet
APPENDIX B—PHYSICAL DIMENSIONS: PQR160, PLASTIC QUAD FLAT PACK (PQFP)
Pin 160
25.35
REF
27.90
28.10
31.00
31.40
Pin 120
Pin 1 I.D.
25.35
REF
27.90
28.10
31.00
31.40
Pin 40
Pin 80
3.20
3.60
0.65 BASIC
3.95
MAX
0.25
Min
SEATING PLANE
16-038-PQR-1
PQR160
12-22-95 lv
Am186™CH HDLC Microcontroller Data Sheet
B-1
B-2
Am186™CH HDLC Microcontroller Data Sheet
APPENDIX C—CUSTOMER SUPPORT
AMD-K6™-2E
Microprocessor
AMD-K6™E
Microprocessor
Am5x86®
Microprocessor
Am486®DX
Microprocessor
ÉlanSC400
Microcontroller
Am386®SX/DX
Microprocessors
Élan™SC310
Microcontroller
ÉlanSC520
Microcontroller
ÉlanSC410
Microcontroller
ÉlanSC300
Microcontroller
Am186CC
Communications
Controller
Am186CH HDLC
Microcontroller
Am186™CU USB
Microcontroller
Am186EM and
Am188™EM
Microcontrollers
80C186 and 80C188
Microcontrollers
Am186EMLV &
Am188EMLV
Microcontrollers
Am186ES and
Am188ES
Microcontrollers
Am186ER and
Am188ER
Microcontrollers
Am186ESLV &
Am188ESLV
Microcontrollers
80L186 and 80L188
Microcontrollers
Am186ED
Microcontroller
Am186EDLV
Microcontroller
— Microprocessors
— 16- and 32-bit microcontrollers
— 16-bit microcontrollers
E86™ Family of Embedded Microprocessors and Microcontrollers
Related AMD Products—E86™ Family Devices
Device
80C186/80C188
80L186/80L188
Am186™EM/Am188™EM
Am186EMLV/Am188EMLV
Am186ES/Am188ES
Am186ESLV/Am188ESLV
Am186ED
Am186EDLV
Am186ER/Am188ER
Am186CC
Am186CH
Am186CU
Élan™SC300
ÉlanSC310
ÉlanSC400
ÉlanSC410
ÉlanSC520
Am386®DX
Am386®SX
Am486®DX
Am5x86®
AMD-K6™E
AMD-K6™-2E
Description
16-bit microcontroller
Low-voltage, 16-bit microcontroller
High-performance, 16-bit embedded microcontroller
High-performance, 16-bit embedded microcontroller
High-performance, 16-bit embedded microcontroller
High-performance, 16-bit embedded microcontroller
High-performance, 80C186- and 80C188-compatible, 16-bit embedded microcontroller
with 8- or 16-bit external data bus
High-performance, 80C186- and 80C188-compatible, low-voltage, 16-bit embedded
microcontroller with 8- or 16-bit external data bus
High-performance, low-voltage, 16-bit embedded microcontroller with 32 Kbyte of
internal RAM
High-performance, 16-bit embedded communications controller
High-performance, 16-bit embedded HDLC microcontroller
High-performance, 16-bit embedded USB microcontroller
High-performance, highly integrated, low-voltage, 32-bit embedded microcontroller
High-performance, single-chip, 32-bit embedded PC/AT microcontroller
Single-chip, low-power, PC/AT-compatible microcontroller
Single-chip, PC/AT-compatible microcontroller
High-performance, 32-bit embedded microcontroller
High-performance, 32-bit embedded microprocessor with 32-bit external data bus
High-performance, 32-bit embedded microprocessor with 16-bit external data bus
High-performance, 32-bit embedded microprocessor with 32-bit external data bus
High-performance, 32-bit embedded microprocessor with 32-bit external data bus
High-performance, 32-bit embedded microprocessor with 64-bit external data bus
High-performance, 32-bit embedded microprocessor with 64-bit external data bus and
3DNow!™ technology
Notes:
1. 186 = 16-bit microcontroller and 80C186-compatible (except where noted otherwise); 188 = 16-bit microcontroller with 8-bit
external data bus and 80C188-compatible (except where noted otherwise); LV = low voltage
Am186™CH HDLC Microcontroller Data Sheet
C-1
Related Documents
T h e f o l l ow i n g d o c u m e n t s p r o v i d e a d d i t i o n a l
infor mation regarding the Am186CH HDLC
microcontroller.
■ Am186™CC/CH/CU Microcontrollers User’s Manual,
order #21914
■ Am186™CC/CH/CU Microcontrollers Register Set
Manual, order #21916
■ Am186™ and Am188™ Family Instruction Set
Manual, order #21267
■ Interfacing an Am186™CC Communications
Controller to an AMD SLAC™ Device Using the
Enhanced SSI, order #21921
Other information of interest includes:
■ E86™ Family Products and Development Tools CD,
order #21058
Am186CC/CH/CU Microcontroller
Customer Development Platform
The Am186CC/CH/CU customer development
platform (CDP) is provided as a test and development
platform for the Am186CC/CH/CU microcontrollers.
The Am186CC/CH/CU CDP ships with the Am186CC
microcontroller. Because this device suppor ts a
superset of the features of the Am186CH HDLC
microcontroller, the development platform can be used
to evaluate the Am186CH device.
The CDP is divided into two major sections: a main
board and a development module. The main board
serves as the primary platform for silicon evaluation
and software development. The board provides
connectors for accessing the major communications
pe r i ph era l s, sw it ch e s to ea s il y c on fi gu r e th e
microcontroller, logic analyzer, and debug headers.
The development module, which attaches to the top of
the main board, provides ready-to-run hardware for
three of the most common communications
requirements:
■ A 10 Mbit/s Ethernet connection
■ An ISDN connection (with both an S/T and a
U interface)
UARTs, PCnet-ISA II (AMD’s single-chip Ethernet
solution), and several other common peripherals. The
CodeKit software comes complete with instructions,
royalty-free distribution rights, and software in both
binary and source code formats.
Third-Party Development Support Products
T h e F u s i o n E 8 6 P r o gr a m o f Pa r t n e r s h i p s f o r
Application Solutions provides the customer with an
array of products designed to meet critical time-tomarket needs. Products and solutions available from
the AMD FusionE86 partners include protocol stacks,
emulators, hardware and software debuggers, boardlevel products, and software development tools, among
others.
In addition, mature development tools and applications
for the x86 platform are widely available in the general
marketplace.
Customer Service
The AMD customer service network includes U.S.
offices, international offices, and a customer training
center. Expert technical assistance is available from
the AMD worldwide staff of field application engineers
and factory support staff to answer E86 and Comm86
family hardware and software development questions.
Note: The support telephone numbers listed below
are subject to change. For current telephone numbers,
refer to www.amd.com/support/literature.
Hotline and World Wide Web Support
For answers to technical questions, AMD provides
e-mail support as well as a toll-free number for direct
access to our corporate applications hotline.
The AMD World Wide Web home page provides the
latest product infor mation, including technical
information and data on upcoming product releases. In
addition, EPD CodeKit software on the Web site
provides tested source code example applications.
Corporate Applications Hotline
(800) 222-9323
Toll-free for U.S. and Canada
44-(0) 1276-803-299
U.K. and Europe hotline
■ Two POTS interfaces
The CDP provides a good starting point for hardware
designers, and software development can begin
immediately without the normal delay that occurs while
waiting for prototypes.
Additional contact information is listed on the back of
this datasheet. For technical support questions on all
E86 and Comm86 products, send e-mail to
[email protected]
The CDP also comes with AMD’s CodeKit software
that provides customers with pre-written driver
software for the major communications peripherals
associated with a typical Am186Cx design. Included
are drivers for the HDLC channels, USB peripheral
controller (for the Am186CU USB microcontroller),
C-2
Am186™CH HDLC Microcontroller Data Sheet
World Wide Web Home Page
To access the AMD home page go to: www.amd.com.
Then follow the Embedded Processors link for
information about E86 and Comm86 products.
Questions, requests, and input concerning AMD’s
WWW pages can be sent via e-mail to
[email protected]
Documentation and Literature
Free information such as data books, user’s manuals,
data sheets, application notes, the E86™ Family
Products and Development Tools CD, order #21058,
and other literature is available with a simple phone
call. Internationally, contact your local AMD sales office
for product literature. Additional contact information is
listed on the back of this data sheet.
Literature Ordering
(800) 222-9323
Toll-free for U.S. and Canada
Am186™CH HDLC Microcontroller Data Sheet
C-3
C-4
Am186™CH HDLC Microcontroller Data Sheet
INDEX
A
B
A19–A0 signals, 13
AD15–AD0 signals, 13
address and data bus (AD15–AD0)
description, 13
address bus (A19–A0)
address bus disable in effect, 29
default operation, 29
ADEN signal, A-7
ALE signal, 13
Am186CH HDLC microcontroller
applications, 31
block diagram (microcontroller), 24
DC characteristics, 37
distinctive characteristics, 1
documentation, C-2
general description, 1
I/O circuitry, 36
logic diagram by default pin function, 7
logic diagram by interface, 6
logic diagrams, 6–7
ordering information, 2
overview (architectural), 24
physical dimensions, B-1
pin assignment tables, 10
pin connection diagram, 8
pin tables (Appendix A), A-1
PQFP package, B-1
related AMD E86 family devices, C-1
signal description table, 13
static operation, 35
applications, 31
32-channel linecard system, 32
architectural overview, 24
ARDY signal, 13
asynchronous communications
asynchronous ready waveforms, 58
asynchronous serial ports (description), 26
baud clock, 35
High-Speed UART clocks, 35
High-Speed UART signal descriptions, 22
UART signal descriptions, 21
BHE signal, 14
block diagram (microcontroller), 24
BSIZE8 signal, 14
bus
address bus description, 13
bus hold timing, 59
bus status pins, 16
entering bus hold waveforms, 59
exiting bus hold waveforms, 60
bus interface
description, 30
signal list, 13
byte write enables, 30
C
capacitance, 38
CAS1–CAS0 signals, 19
characteristics
See DC characteristics.
switching characteristics, 40
chip selects
description, 30
ranges and DRAM configuration, 13, 19
signal descriptions, 19
CLKOUT signal, 17
CLKSEL1 signal, A-7
CLKSEL2 signal, A-7
clock
See also CPU.
CLKOUT signal description, 17
clock generation and control, 33
control, 31
crystal parameters, 34
crystal-driven clock source, 34
external clock source, 35
external interface to support clocks, 34–35
features, 33
High-Speed UART clocks, 35
PLL bypass mode, 35
suggested system clock frequencies, clock modes
and crystal frequencies, 34
system clock, 33
system interfaces and clock control, 28
UART baud clock, 35
Am186™CH HDLC Microcontroller Data Sheet
Index-1
CPU
Am186 embedded CPU, 25
CPU PLL modes, A-7
system clock, 33
system clock timing waveforms, 62
system clocks timing, 61
crystal
crystal-driven clock source, 34
parameters, 34
suggested crystal frequencies, 34
CTS_HU signal, 22
CTS_U signal, 22
customer support
documentation and literature, C-3
hotline and web, C-2
literature ordering, C-3
ordering the microcontroller, 2
third-party development support products, C-2
web home page, C-3
DRAM
chip selects and DRAM configuration, 13
description, 30
read cycle with wait states waveform, 68
read cycle without wait states waveform, 68
refresh cycle waveform, 70
signal descriptions, 19
timing, 67
write cycle with wait states waveform, 69
write cycle without wait states waveform, 69
DRQ1–DRQ0 signals, 14
DS signal, 14
DT/R signal, 14
E
emulation
in-circuit emulator (ICE) support, 31
signals used by emulators, 18
evaluation platform, C-2
D
DC characteristics over commercial and industrial
operating ranges, 37
DCE (data communications equipment)
DCE interface timing, 65
DCE receive waveforms, 65
DCE transmit waveforms, 65
signal descriptions, 22
DCE_CTS_A signal, 23
DCE_CTS_B signal, 23
DCE_RCLK_A signal, 22
DCE_RCLK_B signal, 23
DCE_RTR_A signal, 23
DCE_RTR_B signal, 23
DCE_RXD_A signal, 22
DCE_RXD_B signal, 23
DCE_TCLK_A signal, 23
DCE_TCLK_B signal, 23
DCE_TXD_A signal, 22
DCE_TXD_B signal, 23
debug
debug support signals, 18
DEN signal, 14
derating, 38
DMA (direct memory access)
DMA request signals, 14
general-purpose DMA channels, 27
SmartDMA channels, 26
timing waveforms, 54
documentation, C-3
Index-2
H
halt
See software halt.
HDLC (high-level data link control)
channels and TSAs description, 26
signal descriptions, 22
High-Speed UART
signal descriptions, 22
HLDA signal, 15
HOLD signal, 15
hotline and world wide web support, C-2
I
I/O
See also memory.
I/O circuitry, 36
I/O space, 25
programmable I/O (PIO), 27
ICE (in-circuit emulator) support, 31
INT8–INT0 signals, 20
interrupts
interrupt controller, 27
signal descriptions, 20
L
LCS signal, 19
logic diagram
by default pin function, 7
by interface, 6
Am186™CH HDLC Microcontroller Data Sheet
M
MCS3–MCS0 signals, 19
memory
See also I/O.
memory organization, 25
segment register selection rules, 26
memory and peripheral interface, 28
multiplexed functions
signal trade-offs, A-5
N
NMI signal, 20
O
ONCE signal, A-7
operating ranges, 37
ordering information, 2
output enable, 30
P
package
PQFP physical dimensions, B-1
PCM (pulse-code modulation) highway
signal descriptions, 23
timing (timing slave), 62
waveforms (timing slave), 63
PCM_CLK_A signal, 23
PCM_CLK_B signal, 23
PCM_FSC_A signal, 23
PCM_FSC_B signal, 23
PCM_RXD_A signal, 23
PCM_RXD_B signal, 23
PCM_TSC_A signal, 23
PCM_TSC_B signal, 23
PCM_TXD_A signal, 23
PCM_TXD_B signal, 23
PCS7–PCS0 signals, 19
peripherals
memory and peripheral interface, 28
peripheral timing, 54
peripheral timing waveforms, 54
system interfaces, 27
pins
See also signals.
pin and signal tables, 9
pin assignments sorted by pin number, 10
pin assignments sorted by signal name, 11
pin connection diagram, 8
pin defaults, A-2
pin list summary, A-11
pin tables (Appendix A), A-1
Multiplexed Signal Trade-Offs table, A-5
Pin List Summary table, A-11
PIOs Sorted by PIO Number table, A-8
PIOs Sorted by Signal Name table, A-9
Power-On Reset (POR) Pin Defaults table, A-2
reserved, 18
pinstraps
pinstraps table, A-7
PIO47–PIO0 signals, 21
PIOs (programmable I/Os)
description, 27
signal descriptions, 21
sorted by pin number, A-8
sorted by signal name, A-9
PLL (phase-locked loop)
bypass mode, 35
modes, A-7
PLL bypass (CPU), A-7
system PLL, 33
POR (power-on reset)
pin defaults, A-2
power
power and ground pins, 18
power consumption calculation, 38
power supply operation, 36
supply connections, 36
supply current, 38
typical ICC versus frequency, 38
PQFP package
physical dimensions, B-1
pulldowns, in Pin List Summary table, Type column, A11
pullups, in Pin List Summary table, Type column, A-11
PWD signal, 21
Q
QS1–QS0 signals, 18
Am186™CH HDLC Microcontroller Data Sheet
Index-3
R
RAS1–RAS0 signals, 19
RD signal, 15
read cycle timing, 47
read cycle waveforms, 49
ready
external ready timing, 57
external ready waveforms, 57
RES signal, 17
reserved pins, 18
reset
definition of types, 12
power-on reset pin defaults table, A-2
signals related to reset, 56
timing, 55
waveforms, 55
reset configuration pins
See pinstraps.
RESOUT signal, 17
RSVD_x–RSVD_x pins, 18
RTR_HU signal, 22
RTR_U signal, 22
RXD_HU signal, 22
RXD_U signal, 21
S
S2–S0 signals, 16
S6 signal, 16
SCLK signal, 22
SDATA signal, 22
SDEN signal, 22
serial communications
See also HDLC, UART.
asynchronous serial ports, 26
description, 26
SmartDMA, 26
synchronous serial port, 27
signals
See also pins.
multiplexed signal trade-offs table, A-5
pin and signal tables, 9
pin assignments sorted by signal name, 11
signal descriptions, 13
signals related to reset, 56
SmartDMA
See DMA.
software halt cycle timing, 53
software halt cycle waveforms, 53
SRDY signal, 16
Index-4
SSI (synchronous serial interface)
signal descriptions, 22
synchronous ready waveforms, 57
synchronous serial port, 27
timing, 66
waveforms, 66
static operation, 35
switching characteristics and waveforms
alphabetical key, 41
key to switching waveforms, 40
numerical key to switching parameter symbols, 44
over commercial/industrial operating ranges, 47
parameter symbols, 41
system clock, 33
See CPU.
system interface, 28
T
thermal characteristics, 39
equations, 39
thermal resistance, 39
timers
See also watchdog timer.
programmable timers, 27
signal descriptions, 21
timing
asynchronous ready waveforms, 58
bus hold, 59
DCE interface, 65
DMA, 54
DRAM, 67
external ready cycle, 57
PCM highway, 62–63
peripheral timing, 54
read cycle timing, 47
reset, 55
software halt cycle, 53
SSI, 66
synchronous ready waveforms, 57
system clocks timing, 61
write cycle timing, 50
TMRIN1–TMRIN0 signals, 21
TMROUT1–TMROUT0 signals, 21
TSAs (time slot assigners)
description, 26
TXD_HU signal, 22
TXD_U signal, 21
Am186™CH HDLC Microcontroller Data Sheet
U
UART
asynchronous ready waveforms, 58
asynchronous serial ports (description), 26
baud clock, 35
High-Speed UART clocks, 35
High-Speed UART signal descriptions, 22
signal descriptions, 21
UART and High-Speed UART clocks, 35
UART baud clock, 35
UCLK signal, 17
UCS signal, 19
UCSX8 signal, A-7
V
VCC description, 18
VCC_A description, 18
VSS description, 18
VSS_A description, 18
W
watchdog timer
description, 28
RES and watchdog timer reset, 17
WHB signal, 16
WLB signal, 16
WR signal, 16
write cycle timing, 50
write cycle waveforms, 52
www
home page, C-3
support, C-2
X
X1 signal, 17
X2 signal, 17
Am186™CH HDLC Microcontroller Data Sheet
Index-5
Trademarks
È 2000 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Am5x86 and Am386 are registered trademarks, and AMD-K6, 3DNow!, Am186, Am188, Comm86, E86, Élan, PCnet, SLAC, and SmartDMA
are trademarks of Advanced Micro Devices, Inc.
FusionE86 is a service mark of Advanced Micro Devices, Inc.
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Disclaimer
The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations
or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no
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AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the
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situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make
changes to its products at any time without notice.
© 2000 Advanced Micro Devices, Inc.
All rights reserved.
Am186™CH HDLC Microcontroller Data Sheet