CYM1841B 256K x 32 Static RAM Module Features • High-density 8-megabit SRAM module • 32-bit standard footprint supports densities from 16K x 32 through 1M x 32 • High-speed CMOS SRAMs — Access time of 12 ns • Low active power selects (CS1, CS2, CS3, CS4) are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. Writing to each byte is accomplished when the appropriate Chip Select (CS) and Write Enable (WE) inputs are both LOW. Data on the Input/Output pins (I/O) is written into the memory location specified on the address pins (A0 through A17). Reading the device is accomplished by taking the Chip Select (CS) LOW while Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the data Input/Output pins (I/O). — 5.3W (max.) at 25 ns • SMD technology • TTL-compatible inputs and outputs • Low profile — Max. height of 0.58 in. • Available in ZIP, SIMM, and angled SIMM footprint • 72-pin SIMM version compatible with 1M x 32 (CYM1851) Functional Description The CYM1841B is a high-performance 8-megabit static RAM module organized as 256K words by 32 bits. This module is constructed from two 256K x 16 SRAMs in SOJ packages mounted on an epoxy laminate board with pins. Four chip The data input/output pins stay at the high-impedance state when write enable is LOW or the appropriate chip selects are HIGH. Two pins (PD0 and PD1) are used to identify module memory density in applications where alternate versions of the JEDEC-standard modules can be interchanged. A 72-pin SIMM is offered for compatibility with the 1M x 32 CYM1851. This version is socket upgradable to the CYM1851. Both the 64-pin and 72-pin SIMM modules are available with either tin-lead or 10 micro-inches of gold flash on the edge contacts. PD0 – PD1 – PD2 – PD3 – Logic Block Diagram (1841B) A0 –A17 OE 18 GND GND OPEN (72-pin only) OPEN (72-pin only) WE CS1 CS2 CS3 CS4 8 256K x 16 SRAM 8 256K x 16 SRAM 8 8 Cypress Semiconductor Corporation Document #: 38-05261 Rev. *A • 3901 North First Street • I/O16–I/O23 I/O24 –I/O31 I/O0 –I/O7 I/O8 –I/O15 San Jose, CA 95134 • 408-943-2600 Revised April 24, 2003 CYM1841B Selection Guide 1841B-15 1841B-20 1841B-25 1841B-35 1841B-45 Unit Maximum Access Time 15 20 25 35 45 ns Maximum Operating Current 400 380 380 340 340 mA Maximum Standby Current 80 80 80 80 80 mA Pin Configurations 72-Pin SIMM Top View 64-Pin ZIP/SIMM Top View Document #: 38-05261 Rev. *A PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 I/O7 WE A14 CS1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 CS3 A16 GND I/O16 I/O17 I/O18 I/O19 A10 A11 A12 A13 I/O20 I/O21 I/O22 I/O23 GND 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 GND PD1 I/O8 I/O9 I/O10 I/O11 A0 A1 A2 I/O12 I/O13 I/O14 I/O15 GND A 15 CS2 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 CS4 A17 OE I/O24 I/O25 I/O26 I/O27 A3 A4 A5 VCC A6 I/O28 I/O29 I/O30 I/O31 NC PD3 PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 I/O7 WE A14 CS1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 CS3 A16 GND I/O16 I/O17 I/O18 I/O19 A10 A11 A12 A13 I/O20 I/O21 I/O22 I/O23 GND A19 NC 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 NC PD2 GND PD1 I/O8 I/O9 I/O10 I/O11 A0 A1 A2 I/O12 I/O13 I/O14 I/O15 GND A15 CS2 CS4 A17 OE I/O24 I/O25 I/O26 I/O27 A3 A4 A5 VCC A6 I/O28 I/O29 I/O30 I/O31 A18 NC Page 2 of 9 CYM1841B Maximum Ratings DC Voltage Applied to Outputs in High Z State ..................................................... – 0.5V to +7.0V (Above which the useful life may be impaired. For user guidelines, not tested.) DC Input Voltage ................................................. – 0.5V to +7.0V Storage Temperature ..................................... – 55°C to +125°C Operating Range Ambient Temperature with Power Applied .................................................... – 10°C to +85°C Range Ambient Temperature VCC 0°C to +70°C 5V ± 10% Commercial Supply Voltage to Ground Potential .................– 0.5V to +7.0V Electrical Characteristics Over the Operating Range 1841B-15 Parameter Description Test Conditions Min. Max. 2.4 1841B-20 Min. Max. VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 2.4 VIH Input HIGH Voltage 2.2 VCC 2.2 VCC VIL Input LOW Voltage –0.5 0.8 –0.5 0.8 IIX Input Leakage Current –3 +3 –3 +3 IOZ Output Leakage Current GND < VO < VCC, Output Disabled –2 +2 –2 +2 ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, CS < VIL 400 ISB1 Automatic CS Power-down Current[1] Max. VCC, CS > VIH, Min. Duty Cycle = 100% ISB2 Automatic CS Power-down Current[1] Max. VCC, CS > VCC – 0.2V, VIN > VCC – 0.2V, or VIN < 0.2V Min. Max. Unit 2.4 0.4 GND < VI < VCC 1841B -25, 35, 45 0.4 V 0.4 V 2.2 VCC V –0.5 0.8 V –3 +3 uA –2 +2 uA 380 340 mA 80 80 80 mA 6 6 6 mA Capacitance[2] Parameter Description CIN Input Capacitance[3] COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 16 pF 16 pF AC Test Loads and Waveforms R1 481Ω R1 481Ω 5V ALL INPUT PULSES 3.0V 5V OUTPUT R2 255Ω 30 pF INCLUDING JIG AND SCOPE OUTPUT R2 255Ω 5 pF INCLUDING JIG AND SCOPE (a) Equivalent to: 90% OUTPUT GND 90% 10% 10% < 5ns < 5 ns (b) THÉVENIN EQUIVALENT 167Ω 1.73V Notes: 1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 2. Tested on a sample basis. 3. 20 pF on CS, 70 pF all others. Document #: 38-05261 Rev. *A Page 3 of 9 CYM1841B Switching Characteristics Over the Operating Range[4] 1841B-15 Parameter Description Min. Max. 1841B-20 Min. 1841B-25 Max. Min. Max. Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid 15 tOHA Output Hold from Address Change tACS CS LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z tLZCS CS LOW to Low Z[5] 20 15 3 CS HIGH to High tPD CS HIGH to Power-Down ns 25 3 15 3 7 25 ns 8 ns 8 0 7 0 ns 8 3 8 4 ns ns 20 0 Z[5, 6] tHZCS 25 20 4 ns ns 7 8 8 15 18 18 ns Write Cycle[7] tWC Write Cycle Time 15 20 25 ns tSCS CS LOW to Write End 10 15 20 ns tAW Address Set-up to Write End 10 18 20 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-up to Write Start 2 2 2 ns tPWE WE Pulse Width 12 15 15 ns tSD Data Set-up to Write End 7 8 8 ns tHD Data Hold from Write End 1 2 2 ns tLZWE WE HIGH to Low Z 0 0 0 ns tHZWE WE LOW to High Z[6] Switching Characteristics Over the Operating Range 0 6 0 8 0 Description ns [4] 1841B-35 Parameter 8 Min. 1841B-45 Max. Min. Max. Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid 35 tOHA Data Hold from Address Change tACS CS LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z tHZOE OE LOW to High Z tLZCS CS LOW to Low Z[5] CS HIGH to High tPD CS HIGH to Power-Down Write tWC 3 ns 45 3 35 25 0 15 ns ns 45 ns 30 ns 0 10 Z[5, 6] tHZCS 45 35 ns 15 10 ns ns 20 20 ns 35 45 ns Cycle[7] Write Cycle Time 35 45 ns Notes: 4. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed by design and not 100% tested. 6. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage. 7. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05261 Rev. *A Page 4 of 9 CYM1841B Switching Characteristics Over the Operating Range (continued)[4] 1841B-35 Parameter Description Min. 1841B-45 Max. Min. Max. Unit tSCS CS LOW to Write End 30 40 ns tAW Address Set-Up to Write End 30 40 ns tHA Address Hold from Write End 2 2 ns tSA Address Set-Up to Write Start 2 2 ns tPWE WE Pulse Width 30 35 ns tSD Data Set-Up to Write End 20 25 ns tHD Data Hold from Write End 2 2 ns tLZWE WE HIGH to Low Z 0 0 ns tHZWE WE LOW to High Z [6] 0 15 0 15 ns Switching Waveforms Read Cycle No. 1[8, 9] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2[8, 10] tRC CS tACS OE tHZOE tDOE tHZCS tLZOE HIGH IMPEDANCE DATA OUT HIGH IMPEDANCE DATA VALID tLZCS Notes: 8. WE is HIGH for read cycle. 9. Device is continuously selected, CS = VIL and OE= VIL. 10. Address valid prior to or coincident with CS transition LOW. Document #: 38-05261 Rev. *A Page 5 of 9 CYM1841B Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled)[7] tWC ADDRESS tSCS CS tAW tHA tSA tPWE WE tSD DATA IN tHD DATA VALID tHZWE tLZWE HIGH IMPEDANCE DATA OUT DATA UNDEFINED Write Cycle No. 2 (CS Controlled)[7, 11] tWC ADDRESS tSA tSCS CS tAW tHA tPWE WE tSD DATA IN tHD DATA VALID tHZWE HIGH IMPEDANCE DATA OUT DATA UNDEFINED Truth Table CS WE OE H X X High Z Input/Output Deselect/Power-Down Mode L H L Data Out Read L L X Data In Write L H H High Z Deselect Note: 11. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05261 Rev. *A Page 6 of 9 CYM1841B Ordering Information Speed (ns) 15 20 25 35 45 Ordering Code CYM1841BPM-15C Package Name Package Type PM03 64-Pin Plastic SIMM Module CYM1841BPZ-15C PZ08 64-Pin Plastic ZIP Module CYM1841BP7-15C PM50 72-Pin Plastic SIMM Module CYM1841BPM-20C PM03 64-Pin Plastic SIMM Module CYM1841BPZ-20C PZ08 64-Pin Plastic ZIP Module CYM1841BP7-20C PM50 72-Pin Plastic SIMM Module CYM1841BPM-25C PM03 64-Pin Plastic SIMM Module CYM1841BPZ-25C PZ08 64-Pin Plastic ZIP Module CYM1841BP7-25C PM50 72-Pin Plastic SIMM Module CYM1841BPM-35C PM03 64-Pin Plastic SIMM Module CYM1841BPZ-35C PZ08 64-Pin Plastic ZIP Module CYM1841BP7-35C PM50 72-Pin Plastic SIMM Module CYM1841BPM-45C PM03 64-Pin Plastic SIMM Module CYM1841BPZ-45C PZ08 64-Pin Plastic ZIP Module CYM1841BP7-45C PM50 72-Pin Plastic SIMM Module Document #: 38-05261 Rev. *A Operating Range Commercial Commercial Commercial Commercial Commercial Page 7 of 9 CYM1841B Package Diagrams 64-Pin ZIP Module – PZ08 51-41310-** 64-Pin Plastic SIMM Module – PM03 51-41368-** 72-Pin Plastic SIMM Module – PM50 51-41375-** All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05261 Rev. *A Page 8 of 9 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CYM1841B Document History Page Document Title: CYM1841B 256K x 32 Static RAM Module Document Number: 38-05261 REV. ECN NO. Issue Date Orig. of Change ** 114352 3/22/02 DSG *A 125739 04/28/03 CS Document #: 38-05261 Rev. *A Description of Change Change from Spec number: 38-M-00031 to 38-05261 Changed Iix and Ioz unit to uA from mA and amended incorrected values shown on pages 2, 3 and 4. Page 9 of 9