VK05CFL ELECTRONIC DRIVER FOR CFL APPLICATION TYPE VK05CFL BV 520 V ICrms 0.25A IPeak 1.5A EMITTER SWITCH POWER OUTPUT STAGE INTEGRATED ANTIPARALLEL COLLECTOR SOURCE DIODE ■ INTEGRATED DIAC FUNCTION ■ NOMINAL WORKING FREQUENCY SETTABLE BY EXTERNAL CAPACITOR ■ IGNITION FREQUENCY SET BY LOAD ■ ■ SO-8 DESCRIPTION The VK05CFL is a monolithic device housed in a standard SO-8 package, made by using STMicroelectronics proprietary VIPower M3 Technology. This device is intended both for the low side and the high side driver in half bridge CFL applications. This means that it is possible to realize a complete H-bridge by using two VK05CFL devices: one connected in HSD configuration and the other connected in LSD configuration. In the VK05CFL used in HSD configuration, the diac pin must be connected to source pin. Both diac functionality and discharge circuit for external diac capacitor are integrated. By an external capacitor it is possible to choose the nominal working frequency without influence on the ignition one. BLOCK DIAGRAM Collector diac Diac sec - osc + R 2Vref + - 5Vref Source March 2002 1/14 VK05CFL ABSOLUTE MAXIMUM RATING Symbol VCS Isec Vsec ICM IOSC VOSC Tj T stg Parameter Collector-Source Voltage Input Current (secondary) Input Voltage (secondary) Collector Peak Current Osc Pin Current Osc Pin Voltage Max Operating Junction Temperature Storage Temperature Range Min Typ Max 520 -100 140 Internally limited -1.8 1.8 100 Internally limited -40 150 -55 150 Unit V mA V A mA V °C °C Value 15 52 (*) Unit °C/W °C/W THERMAL DATA Symbol R thj-lead R thj-amb Parameter Thermal Resistance Junction - lead Thermal Resistance Junction - ambient Max Max (*) When mounted on a standard single-sided FR-4 board with 100mm2 of Cu (at least 35µm thick). CONNECTION DIAGRAM Collector Collector Collector Collector 5 4 8 1 sec osc diac Source SO-8 PIN FUNCTIONS Pin Name Collector Source diac sec osc 2/14 Pin Function Collector of the NPN high voltage transistor in the cascode configuration. Low voltage Power MOSFET source in the cascode configuration and GROUND reference. Input of the diac block to start the system up at the beginning. Connection with secondary winding of the voltage transformer, in order to trigger and to supply the device. Output via to charge external capacitor necessary to set the steady state working frequency. VK05CFL ELECTRICAL CHARACTERISTICS (T case=25°C unless otherwise specified) FORWARD Symbol VCS(sat) Parameter Test Conditions Collector-Source Saturation Voltage Vsec=10V; IC=300mA Min Typ 1.4 Max 2.8 Unit Parameter Collector-Source Reverse Voltage Test Conditions IC= -300mA Min Typ -1 Max -1.5 Unit Parameter Osc Output Current Osc Turn-off Voltage Test Conditions Vsec=10V; VOSC=0V Vsec=10V Min Typ 300 1.6 Max Unit µA V Parameter Diac On Threshold Diac Off Threshold Test Conditions Min 28 18 Typ 31 Max 35 Unit Parameter Sec Clamp High Sec Clamp Low Sec Turn-on Voltage Test Conditions Isec=20mA; VOSC=0V Isec= -10mA IC=10mA; VOSC=0V Vsec=10V; VOSC=0V; IC=300mA Min Typ 22 25 4.5 Max Unit 5.5 V V V V REVERSE Symbol VCSr V OSC Symbol IOSC VOSC(th) 2 DIAC Symbol Vdiac(thH) Vdiac(thL) V V SEC Symbol Vsec(clH) Vsec(clL) Vsec(on) Isec(on) Sec On Current 3.5 4 mA 3/14 VK05CFL APPLICATION DESCRIPTION Technology Overview The VK05CFL is made by using STMicroelectronics proprietary VIPower M3-3 technology. This technology allows the integration in the same chip both of the control part and the power stage. The power stage is the “Emitter Switching”. It is made by putting in cascode configuration a bipolar high voltage darlington with a low voltage MOSFET. This configuration provides a good trade-off between the bipolars low ON drop with high breakdown voltage in OFF state, and the MOSFETS high switching speed. The maximum theoretical working frequency is in the range of 300KHz. Circuit description The electrical scheme of the VK05CFL used as a self-oscillating converter to drive fluorescent tubes is shown in Fig. 1. Figure 1: Application schematic PTC R2 diac Collector C7 sec R4 C5 L1s VK05CFL osc Source C10 Bridge + Input Filter diac sec C8 R5 C4 C13 C3 R1 Lp Tube Collector VK05CFL C2 L2s osc Source C11 C6 This topology does not require the saturable transformer to set the working frequency. Two secondary windings are wound on the main ballast choke Lp. These windings have two functions:1) to trigger the ON state and 2) to provide the power supply to the device. A good trade-off for the ratio between the primary winding Lp and the two secondary windings is 10:1; in order to minimize the power dissipated on the resistors R4 - R5 and to guarantee sufficient voltage to supply the device. The steady-state working frequency is set by the two capacitor C5 and C6. They are charged by a current Icap≈200µA. When the voltage on the capacitor reaches an internal fixed value the power stage is turned OFF. By choosing the same value for C5 and C6 the circuit will work with a duty-cycle of 50%. During the start-up, as the resonance frequency is higher than the steady-state frequency, the secondary voltage falls lower than the device sustain voltage before the capacitor C5-6 is charged, switching OFF the device. For this reason the circuit can work at different frequencies during the start-up and steady-state phases. The resistor R2 and the capacitor C8 are needed to bias the internal diac in the low side device in order to start-up the system. In the high side device the diac pin must be connected to the midpoint. R1 is the pull-up resistor and C7 is the snubber capacitor. Input filtering is realized by R4-C10 and R5-C11. It is necessary to have a proper supply voltage on the input pin. 4/14 1 VK05CFL Functional description When the circuit is supplied, the capacitor C8 is charged by the resistor R2 till the voltage across it reaches the internal diac threshold value (~ 30V). The low side switch is turned ON and consequently current will flow from the HV rail to ground through the path formed by C3//C2, C4 and Lp (in case that the pre-heating network is not present: PTC and C13 are not connected). The voltage drop on Lp is “transferred” to the two secondary windings (wound in opposition) in order to confirm the ON state for the low side device and the OFF state for the high side device. As soon as the low side device switches ON, the capacitor C8 is discharged to ground by an internal HV diode to avoid diac restart. In this preliminary phase the tube is OFF and the circuit will oscillate at the Lp-C4 series with (C3//C2) resonance frequency f st – up = 1 ---------------------------2π L c ⋅ C4 we can neglect C3//C2 As this frequency is higher than the steady-state one, the two devices will switch ON-OFF at this frequency, as the voltage on the two secondary windings falls below the voltage needed to keep the device on. As soon as the tube is ignited the resonance frequency is reduced ≈(Lp-C3//C2) and the circuit will work at the steady-state frequency fixed by the two capacitors C5 and C6. It is possible to calculate the steady-state frequency by these formulae: 5 T on = R ⋅ C ⋅ ln --2 (R = internal impedance) 1 --- T = T o n + tsto ra ge + t ( d v ) ⁄ ( d t) 2 1 f = --T Considering the VK05CFL board: R=12KΩ; C5=C6=1.2nF; tstorage≈400nsec; C7=680pF⇒t(dv)/(dt)≈800nsec; the working frequency will be: f≈35KHz. In figure 2 and figure 3, the start-up phase without preheating is reported, while in figure 4 the main waveforms in steady-state are shown. Figure 2: Start-up phase Idevice midpoint 5/14 VK05CFL Figure 3: Start-up phase diac midpoint From figure 4 it can be observed that the value of secondary voltage decreases when the lamp current increases. This happens because increasing the value of the current flowing through the tube, increase the drop on it, consequently decreasing the voltage on the ballast inductor Lp and thereby decreasing also the secondary voltage. By inserting the filters (R4-C10; R5-C11) between the two secondary windings and the devices, it is possible to guarantee a higher voltage on the input pin of the devices for longer time compared to the secondary signal. In this way it is possible to extend the use of the VK05CFL to all the power range eg.5W – 23W. Figure 4: Steady state waveforms VL2s Vmidpoint Vsec Ilamp 6/14 VK05CFL Secondary Filter Design The design of RC network applied on the sec pin of both devices has to be done taking into account the following considerations: 1) The sec filtered voltage must reach the device ON threshold at the end of the negative dV/dt and before the end of the freewheeling diode conduction in order to avoid hard switching or switching ON delay. 2) The filtered voltage must be high enough (greater than 5V) at the end of Ton in order to guarantee the device supply voltage. A good choice for time constant (τ=RC) is in the range:1.5 µs ÷ 3.3 µs. The resistor value has chosen in relation to the power dissipated on it during the start-up phase, the worst condition is verified when the preheating is used. Tube pre-heating If the tube pre-heating is required the classical solution with PTC can be used easily (see application schematic in figure 1). In Figure 5, the lamp current waveform during this phase is shown. Figure 5: Pre-heating phase Ilamp APPLICATION BOARD Please note that this demo can be used for Europe (230Vrms) market as well as for USA (110Vrms) market. In order to use the demoboard for Europe market the following modification must be done: electrolytic capacitors C1 and C12 must be replaced with only one electrolytic capacitor Cx = 3,3µF/400V connected with the positive pin on the D1 catode and the negative pin on the D3 anode. Also different power range CFL can be driven by using this demoboard; on the left side of the component list reported below you find 7/14 VK05CFL component values able to drive CFL in the power range 5W to 15W, the component values written in brackets in the table on the right are referred to the power range 15W to 23W. COMPONENT LIST Reference T1 L0 D0,D1,D2,D3 C1, C12 C2, C3 C4 C5, C6 C7 C8 C10, C11 R0 R1, R2 R4, R5 U1, U2 5W to 15W lamp Value Lp=3,1mH, N1/N2=N1/N3=10 820µH 1N4007 22µF/200V electrolytic Reference T1 L0 D0,D1,D2,D3 (for Europe to replace C1, C12 with Cx=3,3µF/400V) 100nF/250V 2,4nF/400V 1.2nF/63V 470pF/400V 22nF/100V 1.5nF/100V 10Ω 1/2W 1MΩ 1/4W 2.2KΩ 1/4W VK05CFL C2, C3 C4 C5, C6 C7 C8 C10, C11 R0 R1, R2 R4, R5 U1, U2 C1, C12 >15W to 23W lamp Value Lp=2,1mH, N1/N2=N1/N3=10 820µH 1N4007 22µF/200V electrolytic (for Europe Cx=6.8µF/400V) 100nF/250V 2,4nF/400V 1nF/63V 470pF/400V 22nF/100V 1.5nF/100V 10Ω 1/2W 1MΩ 1/4W 1KΩ 1/2W VK05CFL Waveforms below was obtained by using the application demoboard mounted for european market: Device ∆T (Tamb=25 °C) for different power lamps 8/14 Device power dissipation Vs. power lamp Figure 6: Board electrical scheme L0 8 1 D0 D1 C12 C3 8 6 3 R0 2 5 2 3 4 R4 C7 R1 C5 C10 3 220V ~ 7 VK05CFL U1 R2 6 1 C4 R5 110V ~ 8 7 6 5 VK05CFL U2 1 1 D2 D3 C1 C2 T1 2 3 4 2 C11 C8 C6 VK05CFL 9/14 VK05CFL Figure 7: Printed Circuit Board legend (Component side) Figure 8: Printed Circuit Board top foil 10/14 VK05CFL Collector current Vs. collector-source saturation voltage at Tamb=25ºC Collector current Vs. collector-source saturation voltage at Tamb=125ºC Vsec= 15V Vsec= 10V Vsec=15V Vsec=10V Vsec=6V Vsec=6V Freewheeling diode If=f(Vf) characteristic at Tamb=25ºC Freewheeling diode If=f(Vf) characteristic at Tamb=125ºC T = 25°C Bipolar storage time Vs. collector current T = 125°C Test circuit 11/14 VK05CFL SO-8 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. TYP. 1.75 0.1 MAX. 0.068 0.25 a2 0.003 0.009 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 c1 45 (typ.) D 4.8 5 0.188 0.196 E 5.8 6.2 0.228 0.244 e 1.27 e3 3.81 0.050 0.150 F 3.8 4 0.14 L 0.4 1.27 0.015 M 0.6 S L1 12/14 MIN. 0.157 0.050 0.023 8 (max.) 0.8 1.2 0.031 0.047 VK05CFL SO-8 TUBE SHIPMENT (no suffix) B Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) C A 100 2000 532 3.2 6 0.6 All dimensions are in mm. TAPE AND REEL SHIPMENT (suffix “13TR”) REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (± 0.1) P D (± 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) All dimensions are in mm. 12 4 8 1.5 1.5 5.5 4.5 2 End Start Top cover tape No components Components No components 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed 13/14 VK05CFL Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 2002 STMicroelectronics - Printed in ITALY- All Rights Reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 14/14