AD AD5280BRU50

PRELIMINARY TECHNICAL DATA
+15V, I2C Compatible
Digital Potentiometers
a
AD5280/AD5282
Preliminary Technical Data
FEATURES
256 Position
AD5280 – 1-Channel
AD5282 – 2-Channel (Independently Programmable)
Potentiometer Replacement
20K, 50K, 200K Ohm with TC < 50ppm/ºC
Internal Power ON Mid-Scale Preset
+5 to +15V Single-Supply; ±5.5V Dual-Supply Operation
I2C Compatible Interface
A1
W1
B1
A2
W2
O1
B2
OUTPUT
REGISTER
SHDN
R
VDD
RDAC1 REGISTER
VSS
RDAC2 REGISTER
R
R
VL
APPLICATIONS
Multi-Media, Video & Audio
Communications
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage to Current Conversion
Line Impedance Matching
ADDRESS
DECODE
AD5282
PWR ON
RESET
8
SCL
SERIAL INPUT REGISTER
SDA
GND
AD0
GENERAL DESCRIPTION
The AD5280/AD5282 provides a single/dual channel, 256 position
digitally-controlled variable resistor (VR) device. These devices
perform the same electronic adjustment function as a
potentiometer, trimmer or variable resistor. Each VR offers a
completely programmable value of resistance, between the A
terminal and the wiper, or the B terminal and the wiper. The fixed
A-to-B terminal resistance of 20, 50 or 200K ohms has a 1%
channel-to-channel matching tolerance with a nominal temperature
coefficient of 30 ppm/°C.
Wiper Position programming defaults to midscale at system power
ON. Once powered the VR wiper position is programmed by a I2C
compatible 2-wire serial data interface. Both parts have two
programmable logic outputs available to drive digital loads, gates,
LED drivers, analog switches, etc.
AD1
The AD5280/AD5282 are available in ultra compact surface mount
thin TSSOP-14/-16 packages. All parts are guaranteed to operate
over the extended industrial temperature range of -40°C to +85°C.
For 3-wire, SPI compatible interface applications, see
AD5203/AD5204/AD5206/AD7376/AD8400/AD8402/AD8403/
AD5260/AD5262/AD5200/AD5201 products.
ORDERING GUIDE
Model
Kilo
Ohms
Temp
Package
Description
Package
Option
AD5280BRU20
AD5280BRU50
AD5280BRU200
20
50
200
-40/+85°C
-40/+85°C
-40/+85°C
TSSOP-14
TSSOP-14
TSSOP-14
RU-14
RU-14
RU-14
AD5282BRU20
AD5282BRU50
AD5282BRU200
20
50
200
-40/+85°C
-40/+85°C
-40/+85°C
TSSOP-16
TSSOP-16
TSSOP-16
RU-16
RU-16
RU-16
FUNCTIONAL BLOCK DIAGRAMS
A1
W1
B1
O2
O1
The AD5280/AD5282 die size is 75 mil X 120 mil, 9,000 sq. mil.
Contains xxx transistors. Patent Number xxx applies.
SHDN
VDD
RDAC1 REGISTER
VSS
RDAC2 REGISTER
R
R
VL
ADDRESS
DECODE
AD5280
PWR ON
RESET
8
SCL
SERIAL INPUT REGISTER
SDA
GND
AD0
AD1
REV PrE 12 MAR 02
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use; nor for any infringements of patents
or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
©Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
AD5280/AD5282
ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION (VDD = +5V, VSS = -5V, VLOGIC = +5V,
VA = +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)
Parameter
Symbol
Conditions
1
Min
Typ
-1
-1
-30
±0.4
±0.5
Max
Units
+1
+1
30
LSB
LSB
%
ppm/°C
Ω
DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs
Resistor Differential NL2
Resistor Nonlinearity2
Nominal resistor tolerance3
Resistance Temperature Coefficient
Wiper Resistance
R-DNL
R-INL
∆R
RAB/∆T
RW
RWB, VA=NC
RWB, VA=NC
TA = 25°C
VAB = VDD, Wiper = No Connect
IW = VDD /R, VDD = +3V or +5V
30
40
100
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs
Resolution
Integral Nonlinearity4
Integral Nonlinearity4
Differential Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
N
INL
INL
DNL
∆VW/∆T
VWFSE
VWZSE
Code = 80H
Code = FFH
Code = 00H
VA,B,W
CA,B
CW
ICM
f = 1 MHz, measured to GND, Code = 80H
f = 1 MHz, measured to GND, Code = 80H
VA = VB = VW
RAB=20KΩ, 50KΩ
RAB=200KΩ
8
–1
–2
–1
–1
0
±0.5
±0.5
±0.4
5
-0.5
+0.5
Bits
LSB
LSB
LSB
ppm/°C
LSB
LSB
+1
+2
+1
+0
+1
RESISTOR TERMINALS
Voltage Range5
Capacitance6 A, B
Capacitance6 W
Common Mode Leakage
VSS
VDD
V
pF
pF
nA
VLOGIC+0.5
0.3VLOGIC
VLOGIC
0.8
VLOGIC
0.6
±1
V
V
V
V
V
V
µA
pF
45
60
1
DIGITAL INPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance6
VIH
VIL
VIH
VIL
VIH
VIL
IIL
CIL
SDA & SCL
SDA & SCL
AD0 & AD1
AD0 & AD1
VLOGIC = +3V, AD0 & AD1
VLOGIC = +3V, AD0 & AD1
VIN = 0V or +5V
0.7VLOGIC
-0.5
2.4
0
2.1
0
3
DIGITAL Output
O1, O2
O1, O2
SDA
SDA
Three-State Leakage Current
Output Capacitance6
VOH
VOL
VOL
VOL
IOZ
COZ
IOH=0.4mA
IOL=-1.6mA
IOL = -6mA
IOL = -3mA
VIN = 0V or +5V
2.4
0
3
5.5
0.4
0.6
0.4
±1
8
V
V
µA
pF
+5.5
+15
±5.5
V
V
V
V
V
POWER SUPPLIES
Logic Supply
Power Single-Supply Range
Power Dual-Supply Range
VLOGIC
VDD RANGE
VSS = 0V
VDD/SS RANGE
Logic Supply Current
Positive Supply Current
Negative Supply Current
Power Dissipation10
Power Supply Sensitivity
ILOGIC
IDD
ISS
PDISS
PSS
+2.7
+5
±4.5
VLOGIC = +5V
VIH = +5V or VIL = 0V
VIH = +5V or VIL = 0V, VDD = +5V, VSS = -5V
2
20
20
0.2
0.05
10
60
60
0.6
0.015
µA
µA
µA
mW
%/%
REV PrE 12 MAR 02
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final
product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
AD5280/AD5282
ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION (VDD = +5V, VSS = -5V, VLOGIC = +5V,
VA = +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)
Parameter
Symbol
Conditions
Min
BW_20K
BW_50K
BW_200K
THDW
tS
eN_WB
RAB = 20KΩ, Code = 80H
RAB = 50KΩ, Code = 80H
RAB = 200KΩ, Code = 80H
VA =1Vrms + 2V dc, VB = 2V DC, f=1KHz
VA= VDD, VB=0V, ±1 LSB error band
RWB = 10KΩ, f = 1KHz
Typ
1
Max
Units
DYNAMIC CHARACTERISTICS6,9,11
Bandwidth –3dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage
650
142
69
0.005
2
14
kHz
kHz
kHz
%
µs
nV√Hz
INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12)
SCL Clock Frequency
tBUF Bus free time between STOP & START
tHD;STA Hold Time (repeated START)
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time For START Condition
tHD;DAT Data Hold Time
tSU;DAT Data Setup Time
tF Fall Time of both SDA & SCL signals
tR Rise Time of both SDA & SCL signals
tSU;STO Setup time for STOP Condition
fSCL
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
After this period the first clock pulse is generated
0
1.3
0.6
1.3
0.6
0.6
0
100
400
0.9
300
300
0.6
KHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
NOTES:
1.
2.
3.
4.
5.
6.
9.
10.
11.
12.
Typicals represent average readings at +25°C, VDD = +5V, VSS = -5V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the
relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
VAB = VDD, Wiper (VW) = No connect
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V.
DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions.
Resistor terminals A,B,W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value
result in the minimum overall power consumption.
PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation.
All dynamic characteristics use VDD = +5V.
See timing diagram for location of measured values.
REV PrE 12 MAR 02
3
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final
product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
AD5280/AD5282
ABSOLUTE MAXIMUM RATINGS (TA = +25°C, unless
otherwise noted)
TABLE 1: AD5280 PIN Function Descriptions
Pin
Name
Description
VDD to GND ............................................................. -0.3, +15V
VSS to GND .................................................................. 0V, -7V
VDD to VSS ...................................................................... +15V
VA, VB, VW to GND ...................................................VSS, VDD
AX – BX, AX – WX, BX – WX .........................................±20mA
Digital Input Voltage to GND.........................................0V, 7V
Operating Temperature Range ...........................-40°C to +85°C
Thermal Resistance* θJA,
TSSOP-14 ........................................................206°C/W
TSSOP-16 ........................................................180°C/W
Maximum Junction Temperature (TJ MAX) .................... +150°C
Storage Temperature ........................................-65°C to +150°C
Lead Temperature
RU-14, RU-16 (Vapor Phase, 60 sec) ....................... +215°C
RU-14, RU-16 (Infrared, 15 sec) .............................. +220°C
1
2
3
4
A
W
B
VDD
5
SHDN
6
7
8
SCL
SDA
AD0
9
AD1
10
11
GND
VSS
12
13
O2
VL
14
O1
Package Power Dissipation (TJMAX - TA) / θJA
*
AD5280 PIN CONFIGURATION
A
1
14
O1
W
2
13
VL
B
3
12
O2
VDD
4
11
VSS
SHDN
5
10
GND
SCL
6
9
AD1
SDA
7
8
AD0
Resistor terminal A
Wiper terminal W
Resistor terminal B
Positive power supply, specified for
operation from +5 to +15V.
Active Low, Asynchronous connection of
the wiper W to terminal B, and open
circuit of terminal A. RDAC register
contents unchanged.
Serial Clock Input
Serial Data Input/Output
Programmable address bit for multiple
package decoding. Bits AD0 & AD1
provide 4 possible addresses.
Programmable address bit for multiple
package decoding. Bits AD0 & AD1
provide 4 possible addresses.
Common Ground
Negative power supply, specified for
operation from 0 to -5V
Logic Output terminal O2
Logic Supply Voltage, needs to be same
voltage as the digital logic controlling the
AD5280.
Logic Output terminal O1
AD5282 PIN CONFIGURATION
O1
1
16 A2
A1
2
15 W2
W1
3
14 B2
B1
4
13 VL
VDD
5
12 V
SS
SHDN
6
11 GND
SCL
7
10 AD1
SDA
8
9
AD0
4
REV PrE 12 MAR 02
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final
product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
AD5280/AD5282
TABLE 2: AD5282 PIN Function Descriptions
Pin
Name
Description
1
2
3
4
5
O1
A1
W1
B1
VDD
6
SHDN
7
8
Logic Output terminal O1
Resistor terminal A1
Wiper terminal W1
Resistor terminal B1
Positive power supply, specified for
operation from +5 to +15V.
Active Low, Asynchronous connection of
the wiper W to terminal B, and open
circuit of terminal A. RDAC register
contents unchanged.
Serial Clock Input
Serial Data Input/Output
SCL
SDA
9
AD0
10
AD1
11
12
GND
VSS
13
VL
14
15
16
B2
W2
A2
Programmable address bit for multiple
package decoding. Bits AD0 & AD1
provide 4 possible addresses.
Programmable address bit for multiple
package decoding. Bits AD0 & AD1
provide 4 possible addresses.
Common Ground
Negative power supply, specified for
operation from 0 to -5V
Logic Supply Voltage, needs to be same
voltage as the digital logic controlling the
AD5282.
Resistor terminal B2
Wiper terminal W2
Resistor terminal A2
t8
SDA
t1
t8
t6
t9
SCL
t2
t3
P
t4
t5
t7
S
t10
Sr
P
Figure 1. Detail Timing Diagram
Data of AD5280/AD5282 is accepted from the I2C bus in the following serial format:
S
0
1
0
1
1
A
D
1
A
D
0
R/
W
A
A/
B
R
S
S
D
Slave Address Byte
O
1
O
2
X
X
X
A
D
7
D
6
D
5
D
4
Instruction Byte
Where:
S = Start Condition
P = Stop Condition
A = Acknowledge
X = Don’t Care
AD1, AD0 = Package pin programmable address bits
9
1
D
3
D
2
D
1
D
0
A
Data Byte
R/W
W= Read Enable at High and Write Enable at Low
A/B = RDAC sub address select. “Zero” for RDAC1 and “One” for RDAC2
SD = Shutdown, same as SHDN pin operation except inverse logic
O2, O1 = Output logic pin latched values
D7,D6,D5,D4,D3,D2,D1,D0 = Data Bits
9
1
9
1
SCL
SDA
0
1
START BY
MAS TER
0
1
1
AD1
AD0
R/W
A/B
RS
SD
O1
O2
X
X
D7
X
D6
D5
D4
D3
ACK. BY
AD5280
ACK. BY
AD5280
FRAME 1
Slave Address Byte
FRA ME 2
Instruction Byte
D2
D1
D0
ACK. BY
AD5280
FRAME 3
Data B yte
Figure 2. Writing to the RDAC Register
REV PrE 12 MAR 02
P
5
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final
product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
AD5280/AD5282
9
1
1
9
SCL
SDA
0
1
1
1
0
START BY
MASTER
AD1
AD0
R/ W
D7
D6
D5
D4
ACK. BY
AD5280
FRAME 1
Slave Address Byte
D3
D2
D1
D0
NO ACK.
BY MASTER
STO P BY
MASTER
FRAME 2
Data From Select ed
RDAC Regis ter
Figure 3. Reading Data from a Previously Selected RDAC Register
for data 02H and so on. Each LSB data value increase moves the
wiper up the resistor ladder until the last tap point is reached at
19982Ω [RAB–1LSB+RW]. The wiper does not directly connect
to the B terminal. See Figure 4 for a simplified diagram of the
equivalent RDAC circuit.
OPERATION
The AD5280/AD5282 provides a single/dual channel, 256position digitally-controlled variable resistor (VR) device. The
terms VR and RDAC are used interchangeably throughout this
documentation. To program the VR settings, refer to the Digital
Interface section. Both parts have an internal power ON preset
that places the wiper in mid scale during power on, which
simplifies the fault condition recovery at power up. In addition,
the shutdown SHDN pin of AD5280/AD5282 places the RDAC
in a zero power consumption state where terminal A is open
circuited and the wiper W is connected to terminal B, resulting
in only leakage currents being consumed in the VR structure. In
shutdown mode the VR latch settings are maintained, so that,
returning to operational mode from power shutdown, the VR
settings return to their previous resistance values.
The general equation determining the digitally programmed
output resistance between W and B is:
RWB ( D ) =
D
⋅ R AB + R W
256
eqn.1
where D is the decimal equivalent of the binary code which is
loaded in the 8-bit RDAC register, and RAB is the nominal endto-end resistance.
Ax
For example, RAB=20KΩ, when VB = 0V and A–terminal is open
circuit, the following output resistance values RWB will be set for
the following RDAC latch codes. Result will be the same if
terminal A is tied to W:
SHDN
RS
D7
D6
D5
D4
D3
D2
D1
D0
RS
RS
Wx
RDAC
LATCH
&
DECODER
RS
Bx
D
(DEC)
RWB
(Ω)
Output State
256
128
1
0
19982Ω
10060Ω
138Ω
60Ω
Full-Scale (RAB - 1LSB + RW)
Mid-Scale
1 LSB
Zero-Scale (Wiper contact resistance)
Note that in the zero-scale condition a finite wiper resistance of
60Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum current of no more
than 5mA. Otherwise, degradation or possible destruction of the
internal switch contact can occur.
Figure 4. AD5280/AD5282 Equivalent RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between terminals A and B
are available in 20KΩ, 50KΩ, and 200KΩ. The final three
digits of the part number determine the nominal resistance
value, e.g. 20KΩ = 20; 50KΩ = 50; 200KΩ = 200. The
nominal resistance (RAB) of the VR has 256 contact points
accessed by the wiper terminal, plus the B terminal contact. The
eight bit data in the RDAC latch is decoded to select one of the
256 possible settings. Assume a 20KΩ part is used, the wiper's
first connection starts at the B terminal for data 00H. Since there
is a 60Ω wiper contact resistance, such connection yields a
minimum of 60Ω resistance between terminals W and B. The
second connection is the first tap point corresponds to 138Ω
(RWB = RAB/256 + RW = 78Ω+60Ω) for data 01H. The third
connection is the next tap point representing 216Ω (78x2+60)
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
digitally controlled resistance RWA. When these terminals are
used the B–terminal should be let open or tied to the wiper
terminal. Setting the resistance value for RWA starts at a
maximum value of resistance and decreases as the data loaded in
the latch is increased in value. The general equation for this
operation is:
RWA ( D ) =
6
256 − D
⋅ R AB + RW
256
eqn. 2
REV PrE 12 MAR 02
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final
product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
AD5280/AD5282
2 bits are determined by the state of the AD0 and AD1 pins of
the device. AD0 and AD1 allow the user to use up to four of
these devices on one bus.
For example, RAB=20KΩ, when VA = 0V and B–terminal is open
circuit, the following output resistance RWA will be set for the
following RDAC latch codes. Result will be the same if terminal
B is tied to W:
D
(DEC)
RWA
(Ω)
Output State
256
128
1
0
60
10060
19982
20060
Full-Scale
Mid-Scale
1 LSB
Zero-Scale
The 2-wire I2C serial bus protocol operates as follows:
1.
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the Acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/W bit is high, the master will read
from the slave device. On the other hand, if the R/W bit is
low, the master will write to the slave device.
The typical distribution of the nominal resistance RAB from
channel-to-channel matches within ±1%. Device to device
matching is process lot dependent and is possible to have ±30%
variation. Since the resistance element is processed in thin film
technology, the change in RAB with temperature has a 30
ppm/°C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
2.
A Write operation contains an extra Instruction Byte more
than the Read operation. Such Instruction Byte in Write
mode follows the Slave Address Byte. The MSB of the
Instruction Byte labeled A/B is the RDAC sub-address
select. A “low” select RDAC1 and a “high” selects RDAC2
for dual channel AD5282. The 2nd MSB RS is the Midscale reset. A logic high of this bit moves the wiper of a
selected RDAC to the center tap where RWA=RWB. The 3rd
MSB SD is a shutdown bit. A logic high causes the RDAC
open circuit at terminal A while shorting wiper to terminal
B. This operation yields almost a zero Ohm in rheostat
mode or zero volt in potentiometer mode. This SD bit
serves the same function as the SHDN pin except it reacts in
active low. The following two bits are O2 and O1. They are
extra programmable logic output that users can make use of
them by driving other digital loads, logic gates, LED
drivers, and analog switches, etc. The 3 LSBs are DON’T
CARE. See Figure 2.
3.
After acknowledged the Instruction Byte, the last byte in
Write mode is the Data Byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an “Acknowledge” bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL, Figure 1.
4.
In Read mode, the Data Byte goes right after the
acknowledgment of the Slave Address Byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (slight difference with the Write mode, there are
eight data bits followed by a “No Acknowledge” bit).
Similarly, the transitions on the SDA line must occur
during the low period of SCL and remain stable during the
high period of SCL.
5.
When all data bits have been read or written, a STOP
condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In Write mode, the master will pull the SDA
line high during the 10th clock pulse to establish a STOP
The digital potentiometer easily generates output voltages at
wiper-to-B and wiper-to-A to be proportional to the input
voltage at A-to-B. Let’s ignore the effect of the wiper resistance
at the moment. For example connecting A–terminal to +5V and
B–terminal to ground produces an output voltage at the wiperto-B starting at zero volts up to 1 LSB less than +5V. Each LSB
of voltage is equal to the voltage applied across terminal AB
divided by the 256 position of the potentiometer divider. Since
AD5280/AD5282 can be supplied by dual supplies, the general
equation defining the output voltage at VW with respect to
ground for any given input voltage applied to terminals AB is:
VW ( D) =
D
256 − D
VA +
VB
256
256
eqn. 3
where D is decimal equivalent of the binary code which is
loaded in the 8-bit RDAC register.
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent on the ratio
of the internal resistors RWA and RWB and not the absolute values,
therefore, the temperature drift reduces to 5ppm/°C.
DIGITAL INTERFACE
2-WIRE SERIAL BUS
The AD5280/AD5282 are controlled via an I2C compatible
serial bus. The RDACs are connected to this bus as slave
devices.
Referring from Figures 2 and 3, the first byte of
AD5280/AD5282 is a Slave Address Byte. It has a 7-bit slave
address and a R/W bit. The 5 MSBs are 01011 and the following
REV PrE 12 MAR 02
The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high, Figure 2. The
following byte is the Slave Address Byte which consists of
the 7-bit slave address followed by an R/W bit (this bit
determines whether data will be read from or written to the
slave device).
7
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final
product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
AD5280/AD5282
V DD1 = 3.3V
condition, Figure 2. In Read mode, the master will issue a
No Acknowledge for the 9th clock pulse (i.e., the SDA line
remains high). The master will then bring the SDA line low
before the 10th clock pulse which goes high to establish a
STOP condition, Figure 3.
Rp
Rp
Rp
Rp
G
G
S
SDA 1
A repeated Write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. During the Write cycle, each Data byte will
update the RDAC output. For example, after the RDAC has
acknowledged its Slave Address and Instruction Bytes, the
RDAC output will update after these two bytes. If another byte
is written to the RDAC while it is still addressed to a specific
slave device with the same instruction, this byte will update the
output of the selected slave device. If different instructions are
needed, the Write mode has to start with a new Slave Address,
Instruction, and Data Bytes again. Similarly, a repeated Read
function of the RDAC is also allowed.
D
M1
SCL1
SDA 2
D
S
SCL2
M2
5V
AD5282
3.3V
E 2PROM
Figure 6. Level Shift for different potential operation.
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in figure 7. Applies to
digital input pins SDA, SCL, and SHDN.
340 Ω
LOGIC
MULTIPLE DEVICES ON ONE BUS
Figure 5 shows four AD5282 devices on the same serial bus.
Each has a different slave address sine the state of their AD0 and
AD1 pins are different. This allows each RDAC within each
device to be written to or read from independently. The master
device output bus line drivers are open-drain pull downs in a
fully I2C compatible interface.
VSS
Figure 7. ESD Protection of digital pins
A,B,W
+5V
Rp
V DD2 = 5V
Rp
VSS
SDA
Figure 8. ESD Protection of Resistor Terminals
MASTER
SCL
VDD
VDD
VDD
SDA SCL
AD1
SDA SCL
AD1
SDA SCL
AD1
SDA SCL
AD1
AD0
AD0
AD0
AD0
AD5282
AD5282
AD5282
AD5282
Figure 5. Multiple AD5282 Devices on One Bus
LEVEL SHIFT FOR BI-DIRECTIONAL INTERFACE
While most old systems may be operated at one voltage, a new
component may be optimized at another. When two systems
operate the same signal at two different voltages, proper method
of level shifting is needed. For instance, one can use a 3.3V
E2PROM to interface with a 5V digital potentiometer. A level
shift scheme is needed in order to enable a bi-directional
communication so that the setting of the digital potentiometer
can be stored to and retrieved from the E2PROM. Figure 6
shows one of the techniques. M1 and M2 can be N-Ch FETs
2N7002 or low threshold FDV301N if VDD falls below 2.5V.
8
REV PrE 12 MAR 02
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final
product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
AD5280/AD5282
TEST CIRCUITS
Figures 9 to 17 define the test conditions used in product specification
table.
Figure 14. Non-Inverting Gain test circuit
Figure 9. Potentiometer Divider Nonlinearity error test circuit
(INL, DNL)
Figure 15. Gain Vs Frequency test circuit
Figure 10. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)
Figure 16. Incremental ON Resistance Test Circuit
Figure 11. Wiper Resistance test Circuit
Figure 17. Common Mode Leakage current test circuit
Figure 12. Power supply sensitivity test circuit (PSS, PSSR)
Figure 13. Inverting Gain test Circuit
REV PrE 12 MAR 02
9
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final
product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
AD5280/AD5282
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)
10
REV PrE 12 MAR 02
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final
product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com