Discontinued (9/98 - last order; 3/99 last ship) IBM01161601M x 1612/8, 5.0VMMDD35DSU-011010627. IBM0116160P1M x 1612/8, 3.3V, LP, SRMMDD35DSU-011010627. IBM0116160M 1M x 1612/8, 5.0V, LP, SRMMDD35DSU-011010627. IBM011616B1M x 1612/8, 3.3VMMDD35DSU-011010627. IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM Features • 1,048,576 word by 16 bit organization • Single 3.3V ± 0.3V or 5.0V ± 0.5V power supply • Standard Power (SP) and Low Power (LP) • 4096 Refresh Cycles - 64 ms Refresh Rate (SP version) - 256 ms Refresh Rate (LP version) • High Performance: • Low Power Dissipation - Active (max) - 50 mA / 45 mA - Standby: TTL Inputs (max) - 2.0 mA - Standby: CMOS Inputs (max) - 1.0 mA (SP version) - 0.1 mA (LP version) - Self Refresh (LP version only) - 200µA (3.3 Volt) - 300µA (5.0 Volt) • 2 CAS -50 -60 Units tRAC RAS Access Time 50 60 ns tCAC CAS Access Time 13 15 ns tAA Column Address Access Time 25 30 ns tRC Cycle Time 95 110 ns tPC Fast Page Mode Cycle Time 35 40 ns • Fast Page Mode • Read-Modify-Write • RAS Only and CAS before RAS Refresh • Hidden Refresh • Package: TSOP-II 50/44 (400mil x 825mil) SOJ 42/42 (400mil) Description The IBM0116160 is a dynamic RAM organized 1,048,576 words by 16 bits, which has a very low “sleep mode” power consumption option. These devices are fabricated in IBM’s advanced 0.5µm CMOS silicon gate process technology. The circuit and process have been carefully designed to pro- vide high performance, low power dissipation, and high reliability. The devices operate with a single 3.3V ± 0.3V or 5.0V ± 0.5V power supply. The 20 addresses required to access any bit of data are multiplexed (12 are strobed with RAS, 8 are strobed with CAS). Pin Assignments (Top View) Pin Description 50/44 TSOP RAS 42/42 SOJ VCC IO0 IO1 IO2 IO3 VCC IO4 IO5 IO6 IO7 NC 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 VSS IO15 IO14 IO13 IO12 VSS IO11 IO10 IO9 IO8 NC NC NC WE RAS A11 A10 A0 A1 A2 A3 VCC 15 16 17 18 19 20 21 22 23 24 25 36 35 34 33 32 31 30 29 28 27 26 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS VCC IO0 IO1 IO2 IO3 VCC IO4 IO5 IO6 IO7 NC NC WE RAS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 43G9618 SA14-4207-06 Revised 4/97 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS IO15 IO14 IO13 IO12 VSS IO11 IO10 IO9 IO8 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS LCAS / UCAS WE Row Address Strobe L/U Column Address Strobe Read/Write Input A0 - A11 Address Inputs OE Output Enable I/O0 - I/O15 Data Input/Output VCC Power (+3.3V or +5.0V) VSS Ground ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM Ordering Information Part Number SP / LP Self Refresh Power Supply Speed Package Notes IBM0116160T3 -50 SP No 5.0V 50ns 400mil TSOP-II 50/44 1 IBM0116160T3 -60 SP No 5.0V 60ns 400mil TSOP-II 50/44 1 IBM0116160BT3 -50 SP No 3.3V 50ns 400mil TSOP-II 50/44 1 IBM0116160BT3 -60 SP No 3.3V 60ns 400mil TSOP-II 50/44 1 IBM0116160J3 -50 SP No 5.0V 50ns 400mil SOJ 42/42 1 IBM0116160J3 -60 SP No 5.0V 60ns 400mil SOJ 42/42 1 IBM0116160BJ3 -50 SP No 3.3V 50ns 400mil SOJ 42/42 1 IBM0116160BJ3 -60 SP No 3.3V 60ns 400mil SOJ 42/42 1 IBM0116160MT3 -50 LP Yes 5.0V 50ns 400mil TSOP-II 50/44 1 IBM0116160MT3 -60 LP Yes 5.0V 60ns 400mil TSOP-II 50/44 1 IBM0116160PT3 -50 LP Yes 3.3V 50ns 400mil TSOP-II 50/44 1 IBM0116160PT3 -60 LP Yes 3.3V 60ns 400mil TSOP-II 50/44 1 IBM0116160MJ3 -50 LP Yes 5.0V 50ns 400mil SOJ 42/42 1 IBM0116160MJ3 -60 LP Yes 5.0V 60ns 400mil SOJ 42/42 1 IBM0116160PJ3 -50 LP Yes 3.3V 50ns 400mil SOJ 42/42 1 IBM0116160PJ3 -60 LP Yes 3.3V 60ns 400mil SOJ 42/42 1 1. SP = Standard Power version (IBM0116160 and IBM0116160B); LP = Low Power version (IBM0116160M and IBM00116160P) ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 43G9618 SA14-4207-06 Revised 4/97 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM Block Diagram Vss Vcc I/O0 I/O15 16 16 Data In Buffer Data Out Buffer (5.0 Volt version) (to OCDs) Regulator VDD (internal) OE WE & 16 UCAS 16 CAS Clock OR Generator LCAS 8 A0 Column Address Column Decoder and I/O Gate Buffer (8) 16 8 A1 Sense Amplifiers A2 A3 Refresh A4 Controller 256 x 16 A5 A6 Refresh Counter A7 A8 A9 12 Row Address A10 Buffer (12) A11 12 Row Decoder (12) Memory Array 4096 4096 x 256 x 16 12 RAS RAS Clock Generator 43G9618 SA14-4207-06 Revised 4/97 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM Truth Table Function Row Column Address Address RAS LCAS UCAS WE OE Standby H H→X H→X X X X X High Impedance Read: Word L L L H L Row Col Data Out Read: Lower Byte L L H H L Row Col Lower Byte: Data Out Upper Byte: High-Z Read: Upper Byte L H L H L Row Col Lower Byte: High-Z Upper Byte: Data Out Write: Word Early-Write L L L L X Row Col Data In Write: Lower Byte Early-Write L L H L X Row Col Lower Byte: Data In Upper Byte: High-Z Write: Upper Byte Early-Write L H L L X Row Col Lower Byte: High-Z Upper Byte: Data In Read-Modify-Write L L L H→L L→H Row Col Data Out, Data In 1st Cycle L H→L H→L H L Row Col Data Out 2nd Cycle L H→L H→L H L N/A Col Data Out 1st Cycle L H→L H→L L X Row Col Data In 2nd Cycle L H→L H→L L X N/A Col Data In 1st Cycle L H→L H→L H→L L→H Row Col Data Out, Data In 2nd Cycle L H→L H→L H→L L→H N/A Col Data Out, Data In L H H X X Row N/A High Impedance H→L L L H X X N/A High Impedance Read L→H→L L L H L Row Col Data Out Write L→H→L L L L→H X Row Col Data In H→L L L H X X X High Impedance Fast Page Mode Read Fast Page Mode Write Fast Page Mode Read-Modify-Write RAS-Only Refresh CAS-Before-RAS Refresh I/O0 - I/O15 Hidden Refresh Self Refresh (LP version only) ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 43G9618 SA14-4207-06 Revised 4/97 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM Absolute Maximum Ratings Rating Symbol Parameter Units Notes -1.0 to +7.0 V 1 3.3 Volt Device 5.0 Volt Device -0.5 to +4.6 VCC Power Supply Voltage VIN Input Voltage -0.5 to min (VCC+0.5, 4.6) -0.5 to min (VCC+0.5, 7.0) V 1 VOUT Output Voltage -0.5 to min (VCC+0.5, 4.6) -0.5 to min (VCC+0.5, 7.0) V 1 TOPR Operating Temperature 0 to +70 0 to +70 °C 1 TSTG Storage Temperature -55 to +150 -55 to +150 °C 1 PD Power Dissipation 1.0 1.0 W 1 IOUT Short Circuit Output Current 50 50 mA 1 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended DC Operating Conditions (TA= 0 to 70˚C) 3.3 Volt Device Symbol 5.0 Volt Device Parameter Min. Typ. Max. Min. Typ. Max. Units Notes VCC Supply Voltage 3.0 3.3 3.6 4.5 5.0 5.5 V 1 VIH Input High Voltage 2.0 — VCC + 0.5 2.4 — VCC + 0.5 V 1, 2 VIL Input Low Voltage -0.5 — 0.8 -0.5 — 0.8 V 1, 2 1. All voltages referenced to VSS. 2. VIH may overshoot to VCC + 1.2V for pulse widths of ≤ 4.0ns with 3.3 Volt, or VCC + 2.0V for pulse widths of ≤ 4.0ns (or VCC + 1.0V for ≤ 8.0ns) with 5.0 Volt. Additionally, VIL may undershoot to -2.0V for pulse widths ≤ 4.0ns with 3.3 Volt, or to -2.0V for pulse widths ≤ 4.0ns (or -1.0V for ≤ 8.0ns) with 5.0 Volt. Pulse widths measured at 50% points with amplitude measured peak to DC reference. Capacitance (TA= 25°C, VCC= 3.3V ± 0.3V or VCC= 5.0V ± 0.5V) Symbol Parameter Min. Max. Units Notes CI1 Input Capacitance (A0 - A11) — 5 pF 1 CI2 Input Capacitance (RAS, LCAS, UCAS, WE, OE) — 7 pF 1 CO Output Capacitance (I/O0 - I/O15) — 7 pF 1 1. Input capacitance measurements made with rise time shift method with CAS = VIH to disable output. 43G9618 SA14-4207-06 Revised 4/97 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM DC Electrical Characteristics (TA= 0 to +70˚C, VCC= 3.3V ± 0.3V or VCC= 5.0V ± 0.5V) Symbol Parameter Min. Max. -50 — 50 -60 — 45 — 1 Units Notes mA 1, 2, 3 ICC1 Operating Current Average Power Supply Operating Current (RAS, CAS, Address Cycling: tRC = tRC min.) ICC2 Standby Current (TTL) Power Supply Standby Current (RAS = CAS = VIH) RAS Only Refresh Current Average Power Supply Current, RAS Only Mode (RAS Cycling, CAS = VIH: tRC = tRC min) -50 — 50 ICC3 -60 — 45 Fast Page Mode Current Average Power Supply Current (RAS = VIL, CAS, Address Cycling: tPC = tPC min) -50 — 25 ICC4 -60 — 25 Standby Current (CMOS) Power Supply Standby Current (RAS = CAS = VCC - 0.2V) SP version — 1 ICC5 LP version — 0.1 CAS Before RAS Refresh Current Average Power Supply Current, CAS Before RAS Mode (RAS, CAS, Cycling: tRC = tRC min) -50 — 50 ICC6 -60 — 45 3.3V — 200 ICC7 Self Refresh Current, LP version only Average Power Supply Current during Self Refresh CBR cycle with RAS ≥ tRASS (min); CAS held low; WE = VCC - 0.2V; Addresses and DIN = VCC - 0.2V or 0.2V. 5.0V — 300 II(L) Input Leakage Current Input Leakage Current, any input (0.0 ≤ VIN ≤ (VCC + 0.3V)), All Other Pins Not Under Test = 0V -5 +5 µA IO(L) Output Leakage Current (DOUT is disabled, 0.0 ≤ VOUT ≤ VCC) -5 +5 µA VOH Output Level (TTL) Output “H” Level Voltage (IOUT = -2.0mA for 3.3V, or IOUT = -5mA for 5.0V) 2.4 VCC V VOL Output Level (TTL) Output “L” Level Voltage (IOUT = +2.0mA for 3.3V, or IOUT = +4.2mA for 5.0V) 0.0 0.4 V mA mA mA 1, 3 1, 2, 3 mA mA 1, 3 µA 1. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 3. Address can be changed once or less while RAS =VIL. In the case of ICC4, it can be changed once or less when CAS =VIH. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 43G9618 SA14-4207-06 Revised 4/97 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM AC Characteristics (TA= 0 to +70˚C, VCC= 3.3V ± 0.3V or VCC= 5.0V ± 0.5V) 1. An initial pause of 200µs is required after power-up followed by 8 RAS only refresh cycles before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh cycles is required. 2. AC measurements assume tT=5ns. 3. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 4. Valid column addresses are A0 through A7. 5. When both LCAS and UCAS go low at the same time, all 16 bits of data are read/written into the device. LCAS and UCAS cannot be staggered within the same read/write cycle. Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) -50 Symbol -60 Parameter Units Min. Max. Min. Max. Notes tRC Random Read or Write Cycle Time 95 — 110 — ns tRP RAS Precharge Time 30 — 40 — ns tCP CAS Precharge Time 10 — 10 — ns tRAS RAS Pulse Width 50 10K 60 10K ns tCAS CAS Pulse Width 13 10K 15 10K ns tASR Row Address Setup Time 0 — 0 — ns tRAH Row Address Hold Time 10 — 10 — ns tASC Column Address Setup Time 0 — 0 — ns tCAH Column Address Hold Time 10 — 10 — ns tRCD RAS to CAS Delay Time 20 37 20 45 ns 1 tRAD RAS to Column Address Delay Time 15 25 15 30 ns 2 tRSH RAS Hold Time 13 — 15 — ns tCSH CAS Hold Time 50 — 60 — ns tCRP CAS to RAS Precharge Time 5 — 5 — ns tDZO OE Delay Time from DIN 0 — 0 — ns 3 tDZC CAS Delay Time from DIN 0 — 0 — ns 3 Transition Time (Rise and Fall) 3 50 3 50 ns 4 tT 1. Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC. 2. Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA. 3. Either tDZC or tDZO must be satisfied. 4. AC measurements assume tT=5ns. 43G9618 SA14-4207-06 Revised 4/97 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM Write Cycle -50 Symbol -60 Parameter Min. Max. Min. Max. Units Notes 1 tWCS Write Command Set Up Time 0 — 0 — ns tWCH Write Command Hold Time 10 — 15 — ns tWP Write Command Pulse Width 10 — 15 — ns tRWL Write Command to RAS Lead Time 13 — 15 — ns tCWL Write Command to CAS Lead Time 13 — 15 — ns tOED OE to DIN Delay Time 13 — 15 — ns 2 tDS DIN Setup Time 0 — 0 — ns 3 tDH DIN Hold Time 10 — 12 — ns 3 1. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (min), the cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle. If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), tAWD ≥ tAWD (min), and tCPW ≥ tCPW (min)(Fast Page Mode), the cycle is a Read-Modify-Write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions are satisfied, the condition of the data out (at access time) is indeterminate. 2. Either tCDD or tOED must be satisfied. 3. These parameters are referenced to LCAS or UCAS leading edge in early write cycles and to WE leading edge in Read-ModifyWrite cycles. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 43G9618 SA14-4207-06 Revised 4/97 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM Read Cycle -50 Symbol -60 Parameter Min. Max. Min. Max. Units Notes tRAC Access Time from RAS — 50 — 60 ns 1, 2, 3 tCAC Access Time from CAS — 13 — 15 ns 1, 3 tAA Access Time from Address — 25 — 30 ns 2, 3 tOEA Access Time from OE — 13 — 15 ns 3 tRCS Read Command Setup Time 0 — 0 — ns tRCH Read Command Hold Time to CAS 0 — 0 — ns 4 tRRH Read Command Hold Time to RAS 0 — 0 — ns 4 tRAL Column Address to RAS Lead Time 25 — 30 — ns tCAL Column Address to CAS Lead Time 25 — 30 — ns tCLZ CAS to Output in Low-Z 0 — 0 — ns tOH Output Data Hold Time 3 — 3 — ns tOHO Output Data Hold from OE 3 — 3 — ns tOFF Output Buffer Turn-Off Delay — 13 — 15 ns 5 tOEZ Output Buffer Turn-Off Delay from OE — 13 — 15 ns 5 tCDD CAS to DIN Delay Time 13 — 15 — ns 6 3 1. Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC. 2. Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA. 3. Measured with the specified current load and 100pF. 4. Either tRCH or tRRH must be satisfied for a read cycle. 5. tOFF (max) and tOEZ (max) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 6. Either tCDD or tOED must be satisfied. 43G9618 SA14-4207-06 Revised 4/97 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM Read-Modify-Write Cycle -50 Symbol -60 Parameter Units Min. Max. Min. Max. Notes tRWC Read-Modify-Write Cycle Time 128 — 150 — ns tRWD RAS to WE Delay Time 68 — 80 — ns 1 tCWD CAS to WE Delay Time 31 — 35 — ns 1 tAWD Column Address to WE Delay Time 43 — 50 — ns 1 tOEH OE Command Hold Time 13 — 15 — ns 1. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (min), the cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle. If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), tAWD ≥ tAWD (min), and tCPW ≥ tCPW (min)(Fast Page Mode), the cycle is a Read-Modify-Write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions are satisfied, the condition of the data out (at access time) is indeterminate. Fast Page Mode Cycle -50 Symbol -60 Parameter Units Min. Max. Min. Max. Fast Page Mode Cycle Time 35 — 40 — ns tRASP Fast Page Mode RAS Pulse Width 50 200K 60 200K ns tCPA Access Time from CAS Precharge — 28 — 35 ns tCPRH RAS Hold Time from CAS Precharge 30 — 35 — ns tPC Notes 1 1. Measured with the specified current load and 100pF. Fast Page Mode Read-Modify-Write Cycle -50 Symbol -60 Parameter Units Min. Max. Min. Max. tPRWC Fast Page Mode Read-Modify-Write Cycle Time 71 — 80 — ns tCPW WE Delay Time from CAS Precharge 48 — 55 — ns Notes 1 1. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (min), the cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle. If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), tAWD ≥ tAWD (min), and tCPW ≥ tCPW (min)(Fast Page Mode), the cycle is a Read-Modify-Write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions are satisfied, the condition of the data out (at access time) is indeterminate. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 43G9618 SA14-4207-06 Revised 4/97 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM Refresh Cycle -50 Symbol -60 Parameter Units Min. Max. Min. Max. tCSR CAS Setup Time (CAS before RAS Refresh Cycle) 5 — 5 — ns tCHR CAS Hold Time (CAS before RAS Refresh Cycle) 10 — 10 — ns tWRP WE Setup Time (CAS before RAS Refresh Cycle) 10 — 10 — ns tWRH WE Hold Time (CAS before RAS Cycle) 10 — 10 — ns tRPC RAS Precharge to CAS Hold Time 5 — 5 — ns Notes Self Refresh Cycle - Low Power Version Only -50 Symbol -60 Parameter Min. Max. Min. Max. Units Notes tRASS RAS Pulse Width During Self Refresh Cycle 100 — 100 — µs 1 tRPS RAS Precharge Time During Self Refresh Cycle 89 — 104 — ns 1 tCHS CAS Hold Time From RAS Rising During Self Refresh Cycle -50 — -50 — ns 1, 2 tCHD CAS Hold Time From RAS Falling During Self Refresh Cycle 350 — 350 — µs 1, 2 1. When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed in an EVENLY DISTRIBUTED manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR- Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh. 2. If tRASS > tCHD (min) then tCHD applies. If tRASS ≤ tCHD (min) then tCHS applies. Refresh -50 Symbol Min. tREF -60 Parameter Max. Min. Units Notes ms 1 Max. SP version — 64 — 64 LP version — 256 — 256 Refresh Period 1. 4096 cycles. 43G9618 SA14-4207-06 Revised 4/97 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM Read Cycle tRC tRP tRAS VIH RAS VIL tCSH tRCD tCRP tRSH UCAS VIH LCAS VIL tCAS tRAD tRAL tCAL tASR tASC tRAH tCAH VIH Address Row Column VIL tRCH tRCS tRRH VIH WE VIL tAA VIH tOEA OE VIL tDZC tDZO VIH DIN tCDD tOED Hi-Z VIL tCAC tCLZ tOFF tOEZ VOH DOUT Valid Data Out Hi-Z VOL tRAC : “H”: or “L” ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Hi-Z tOH tOHO 43G9618 SA14-4207-06 Revised 4/97 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM Write Cycle (Early Write) tRC tRAS tRP VIH RAS VIL tCSH tRCD tRSH V UCAS IH LCAS V IL tCRP tCAS tRAD tASR tASC tRAH tCAH VIH Address Row Column VIL tWCS VIH tWCH tWP WE VIL VIH OE VIL tDS tDH VIH DIN Valid Data In VIL VOH DOUT Hi-Z VOL : “H” or “L” 43G9618 SA14-4207-06 Revised 4/97 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 13 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM Write Cycle (Delayed Write) tRC tRAS tRP VIH RAS VIL tCSH tRCD tCRP tRSH V UCAS IH LCAS V IL tCAS tRAD tASR tASC tRAH tCAH VIH Address Row Column VIL tCWL tRCS VIH tWP WE VIL tRWL VIH OE tOEH VIL tOED tDZO tDS tDZC VIH DIN tDH Valid Data In Hi-Z VIL tOEZ tCLZ tOEA VOH DOUT VOL Hi-Z : “H” or “L” ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 14 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Hi-Z * * tOEH greater than or equal to tCWL 43G9618 SA14-4207-06 Revised 4/97 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM Read-Modify-Write Cycle tRWC tRP tRAS VIH RAS VIL tCSH tRCD UCAS LCAS tRSH VIH tCRP tCAS tRAD VIL tASC tASR tRAH tCAH VIH Row Address Column VIL tCWD tRWL tAWD tCWL tRWD tWP VIH WE tAA VIL tRCS tOEH VIH OE tOEA VIL tDZC tDS tDH tDZO VIH DIN Hi-Z VIL DIN tCAC tCLZ tOED tOEZ VOH DOUT Hi-Z Hi-Z DOUT VOL * tRAC tOHO : “H” or “L” * tOEH greater than or equal to tCWL 43G9618 SA14-4207-06 Revised 4/97 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 15 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM Fast Page Mode Read Cycle tRASP tRP VIH tCPRH RAS VIL tPC tRCD UCAS LCAS tCP tCP VIH tRSH tCAS tCAS tCRP tCAS VIL tCSH tASR tRAH tASC tCAL tRAL tASC tCAH tCAH tASC tCAH VIH Address Row Column 1 Column 2 Column n VIL tRAD tRCS t RCS tRCH tRCS tRCH tRCH VIH WE VIL tRRH tAA tAA tAA tCPA tOEA tCPA tOEA VIH tOEA OE VIL tOHO tOH tOHO tOH tDZC tDZC tDZO tDZO tDZC tDZO tOED tOHO tOH tCDD tOED tOED VIH DIN VIL tCAC tCAC tRAC tCLZ VOH DOUT DOUT 1 VOL tOFF tOEZ tOEZ tCLZ tCAC tOFF tOFF tOEZ tCLZ DOUT 2 DOUT N : “H” or “L” ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 16 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 43G9618 SA14-4207-06 Revised 4/97 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM Fast Page Mode Write Cycle tRASP tRP VIH RAS VIL tPC tCP tRCD tRSH tCP V UCAS IH LCAS V IL tCRP tCAS tCAS tCSH tASR tRAH tASC tCAH tCAH tASC tASC tCAH VIH Address Row Column 1 Column 2 Column n tCWL tCWL VIL tRAD tCWL tRWL tWCH tWCS tWCH tWCS VIH tWCH tWCS tWP tWP WE tWP VIL VIH OE VIL tDS tDH tDS tDH tDS tDH VIH DIN DIN 1 VIL DIN 2 DIN N VOH DOUT Hi-Z VOL : “H” or “L” 43G9618 SA14-4207-06 Revised 4/97 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 17 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM Fast Page Mode Read-Modify-Write Cycle tRP tRASP VIH RAS VIL tPRWC tRCD tCP VIH UCAS LCAS VIL tCP tCAS tCAS tCSH tASR tRAH tASC tCAS tCWL tCAH tCWL tASC tCRP tRSH tCWL tCAH tASC tRWL tCAH VIH Address VIL Row Column 1 Column 2 tRWD tAWD tRCS tCPW tAWD tRCS tCWD Column n tRCS tCWD tWP tCPW tAWD tCWD tWP tWP VIH WE tCAC VIL tCAC tAA tCAC tAA tAA tRAD tCPA tCPA VIH OE tOEH tOEH VIL tOEA tOEA tDH tDS tDS tDS t DZO tOEA tDH tDH tDZC tOEH tOED tOED tOED VIH DIN DIN 1 VIL tCLZ tOEZ tOHO DIN 2 tOEZ tOHO tCLZ tOEZ tOHO tCLZ VOH DOUT DIN N Hi-Z * VOL tRAC DOUT 1 : “H” or “L” ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 18 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 DOUT 2 DOUT N * tOEH greater than or equal to tCWL 43G9618 SA14-4207-06 Revised 4/97 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM RAS Only Refresh Cycle tRC tRP tRAS VIH RAS VIL tRPC UCAS LCAS tCRP VIH VIL tASR tRAH VIH Address Row VIL VOH Hi-Z DOUT VOL : “H” or “L” NOTE: WE, OE and DIN are “H” or “L” 43G9618 SA14-4207-06 Revised 4/97 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 19 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM CAS Before RAS Refresh Cycle t RC tRAS tRP VIH RAS VIL t RPC tRPC tCSR tCSR tCP UCAS LCAS t CHR VIH VIL tWRH tWRH tWRP tWRP VIH WE VIL VIH OE VIL tOED tCDD VOH DIN Hi-Z VOL tOEZ tOFF DOUT VOH Hi-Z VOL : “H” or “L” NOTE: Address is “H” or “L” ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 20 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 43G9618 SA14-4207-06 Revised 4/97 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM Hidden Refresh Cycle (Read) tRC tRC tRP tRP tRAS tRAS VIH RAS VIL tRCD tRSH tCRP tCHR V UCAS IH LCAS V IL tRAL tRAD tASR tWRH tWRP tASC tRAH tCAH VIH Address Row Column VIL tRRH tRCS VIH WE VIL tAA VIH tOEA OE VIL tDZC tDZO VIH DIN tCDD tOED Hi-Z VIL tCAC tOFF tCLZ tOEZ VOH DOUT Valid Data Out Hi-Z VOL Hi-Z tRAC : “H” or “L” 43G9618 SA14-4207-06 Revised 4/97 tOH tOHO ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 21 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM Hidden Refresh Cycle (Write) tRC tRC tRP tRP tRAS tRAS VIH RAS VIL t RSH tRCD tCHR tCRP VIH UCAS LCAS VIL tASR tASC tRAH tCAH VIH Address Row Column VIL t WRP tWCS VIH tWRH tWCH tWP WE VIL VIH OE VIL t DS tDH VIH DIN Valid Data VIL VOH DOUT Hi-Z VOL : “H” or “L” ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 22 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 43G9618 SA14-4207-06 Revised 4/97 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM Self Refresh Cycle (Sleep Mode) - Low Power version only tRASS tRPS VIH RAS VIL tRPC tCHS tCSR tCP tCHD tCRP UCAS VIH LCAS V IL tWRH tWRP VIH WE VIL tOFF DOUT VOH Hi-Z VOL : “H” or “L” NOTES: 1. Address and OE are “H” or “L” 2. Once RAS (min) is provided and RAS remains low, the DRAM will be in Self Refresh, commonly known as “Sleep Mode.” 3. If tRASS > tCHD (min) then tCHD applies. If tRASS ≤ tCHD (min) then tCHS applies. 43G9618 SA14-4207-06 Revised 4/97 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 23 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM PACKAGE DIMENSIONS (400mil; 50/44 lead; Thin Small Outline Package) 20.95 ± 0.10 11.76 ± 0.20 10.16 ± 0.10 Detail A +0.075 0.125 -0.005 Lead #1 Seating Plane 0.10 0.80 Basic 0.35 + 0.10 - 0.05 0.875 REF 1.20 Max Detail A 1.00 ± 0.05 +0.10 0.05 -0.00 0.25 Basic Gage Plane 0.5 ± 0.1 NOTE: All dimensions are in millimeters; Package diagrams are not drawn to scale. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 24 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 43G9618 SA14-4207-06 Revised 4/97 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM PACKAGE DIMENSIONS (400mil; 42/42 lead; Small Outline J-Lead) 27.305 ± 0.127 9.398 Basic 11.176 ± 0.127 10.16 ± 0.127 3.505 ± 0.254 2.083 min 0.76 min +0.097 0.203 -0.025 Lead #1 I.D. Lead #1 Seating Plane 0.10 1.27 Basic +0.088 0.42 -0.039 +0.123 0.69 -0.03 NOTE: All dimensions are in millimeters; Package diagrams are not drawn to scale. 43G9618 SA14-4207-06 Revised 4/97 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 25 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Discontinued (9/98 - last order; 3/99 last ship) IBM0116160 IBM0116160M IBM0116160B IBM0116160P 1M x 16 12/8 DRAM Revision Log Revision 11/93 09/06/94 Contents Of Modification Initial Release Combine the 3.3 Volt and the 5.0 Volt specifications 1. Iout changed to +2.0 mA and -2.0 mA in DC Electrical Characteristics table. 2. Packaging diagrams modified to clarify lead thickness and standoff height. 3. tRPC min changed from 0 to 5ns. 4. tCHR min changed from 20 to 10ns. 5. Currents in DC Electrical Characteristics table revised. 6. Test Modes and Test Circuit Diagram removed. 7. Rename tODD to tOED. 11/15/95 8. tOED, tCDD, tOEZ, and tOFF min changed from 20 to 15ns, for the 70ns part. 9. tRRH min changed from 5 to 0ns for all speed sorts. 10. tOEH min changed from 20 to 15ns for the 70ns part. 11. tCSR min changed from 10 to 5ns for all speed sorts. 12. tCAHmin changed from 15 to 10ns on 60 and 70ns parts. 13. tOFF max changed from 20 to 15ns for 70ns parts. 14. 400mil 42/42 SOJ package option added 1. The Low Power and Standard Power Specifications were combined. ES# 43G9174 and ES# 43G9618 were combined into ES# 43G9618. 2. Added Die Rev E part numbers. 3. tDH was reduced from 15ns to 12ns for the -60 speed sort. 12/10/95 4. tCHD was added to the Self Refresh Cycle with a value of 350µs for all speed sorts. 5. The Self Refresh timing was changed to allow CAS to go high tCHD after RAS falls entering a Self Refresh. 6. The CBR timing diagram was changed to allow CAS to remain low for back-to-back CBR cycles. 7. WE for the Hidden Refresh Write cycle in the Truth Table was changed from “L” to ” H”. 1. ICC2 was changed from 2mA to 1mA. 2. II(L) and IO(L) were altered from +/- 10uA to +/- 5uA. 09/01/96 3. tT was initially at a max of 30ns. It has been modified to 50ns for all speed sorts. 4. tCPA was decreased from 30ns to 28ns for the -50 speed sort. 5. tRASP max of 125K was raised to 200K for all speed sorts. 6. tRP was changed from 35ns to 30ns for the -50 speed sort. 1. WE for the Hidden Refresh Write cycle in the Truth Table was changed from “H” to “L→H”. 2. tOED was moved from the Common Parameters table to the Write Cycle Parameters Table. 3. tODD in the CAS before RAS timing diagram was renamed tOED. 4. The -70 speed sort and timings were removed. 03/19/97 5. Icc1, Icc3, Icc6 for the -50 speed sort were reduced from 85mA to 50mA. 6. Icc4 for the -50 speed sort was reduced from 75mA to 25mA. 7. Icc1, Icc3, Icc6 for the -60 speed sort were reduced from 75mA to 45mA. 8. Icc4 for the -60 speed sort was reduced from 65mA to 25mA. 04/23/97 1. Icc5 was changed from 200µA to 100µA for the Low Power Die Rev F Parts. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 26 of 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 43G9618 SA14-4207-06 Revised 4/97 Discontinued (9/98 - last order; 3/99 last ship) International Business Machines Corp.1997 Printed in the United States of America All rights reserved IBM and the IBM logo are registered trademarks of the IBM Corporation. This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. For more information contact your IBM Microelectronics sales representative or visit us on World Wide Web at http://www.chips.ibm.com IBM Microelectronics manufacturing is ISO 9000 compliant. SA14-4207-06 Powered by ICminer.com Electronic-Library Service CopyRight 2003