TOSHIBA TLCS-90 Series TMP90CH44 CMOS 8–Bit Microcontrollers TMP90CH44N/TMP90CH44F 1. Outline and Characteristics The TMP90CH44 is a high-speed, high performance 8-bit microcontroller developed for application in the control of various devices. TMP90CH44, CMOS 8-bit microcontroller, integrates an 8-bit CPU, ROM, RAM, A/D converter, multi-function timer/event counter, general-purpose serial interface and slave functions in a single chip, and with which external program memory and data memory can be extended up to 48KB. TMP90CH44N is a device with a 64-pin shrink DIP. TMP90CH44F is a device with a 64-pin flat package. The following are the features of TMP90CH44: (1) (2) (3) Highly efficient instructions: 163 types of basic instructions, including Multiplication, division, 16-bit arithmetic operations, bit manipulation instructions Minimum instruction executing time: 250ns (at 16MHz oscillation frequency) Built-in ROM: 16KB (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) Built-in RAM: 512 bytes Memory expansion External program memory: 48KB External data memory: 48KB Highly accurate 8-bit A/D converter (4 channels) General-purpose serial interface (1 channel) With asynchronous mode and I/O interface mode Multi-function 16-bit timer/event counter (1 channel) 8-bit timer (4 channels) Stepping motor control and pattern generation ports (2 channels) Input/Output ports: 54 pins Slave function Interrupt function: 12 internal, 3 external Micro Direct Memory Access (DMA) function (4 channels) Watchdog timer function Standby function (3 HALT modes) The information contained here is subject to change without notice. The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equipments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA. TOSHIBA CORPORATION 1/18 TMP90CH44 Figure 1. TMP90C844 Block Diagram 2/18 TOSHIBA CORPORATION TMP90CH44 2. Pin Assignment and Functions The assignment of input/output pins for TMP90C844, their name and outline functions are described below. 2.1 Pin Assignment Figure 2.1 (1) shows pin assignment of the TMP90C844N. Figure 2.1 (1). Pin Assignment (Shrink DIP) TOSHIBA CORPORATION 3/18 TMP90CH44 Figure 2.1 (2) shows the pin assignment of TMP90CH44F. Figure 2.1 (2). Pin Assignment (Flat Package) 4/18 TOSHIBA CORPORATION TMP90CH44 2.2 Pin Names and Functions The names of input/output pins and their functions are summarized in Table 2.2. Table 2.2 (1/2) Pin Name No. of pins P00 ~ P07 /AD0 ~ AD7 8 P10 ~ P17 /A8 ~ A15 8 P20 ~ P27 8 /SB0 ~ SB7 (8) /WAIT (1) I/O or tristate I/O /Tristate I/O /Output I/O /Input Function Port 0: Each bit can be set for input or output Address/Data bus: Operates as an 8-bit bidirectional address bus or data bus when using external memory. Port 1: An 8-bit I/O port. Each bit can be set for input or output. Address bus: Operates as an address bus (upper 8 bits) when using external memory. Port 2: Each bit can be set for input or output. Address bus: The upper 8 bits address bus for external memory. Wait: Input pin for connecting a memory or peripheral LSI with delayed access time. P30 ~ P37 8 I/O /SWR (1) /Input Slave write: The strobe signal input to write data from the master processor. Port 3: 8-bit I/O port which allows I/O selection on bit basis (with programmable pull-up resistor). /SRD (1) /Input Slave read: The strobe signal used by the master processor to read data. /SCS (1) /Input Slave chip select: The chip select signal input from the master processor. Command/data: The command/data select signal input from the master processor. C/D (1) Input /STA (1) /Output RxD (1) Input Receiver of serial data Serial clock /SCLK (1) /I/O /TxD (1) /Output Status output: Used to report the slave bus status to the master processor. Transmitter of serial data P40 ~ P47 8 I/O /TO1, 3, 4, 5 (4) /Output Timer outputs 1, 3,4, and 5: Output ports for timer 0, or timer 1, timer 2, timer 3 and timer 4 (2 lines). /TI0, 2, 4, 5 (4) /Input Timer inputs 0, 2, 4, and 5: Input ports for timer 0, or timer 1, timer 2 and timer 4 (2 lines). /INT0 (1) /Input Interrupt request terminal 0: Interrupt request pin 0: Level/rise edge programmable interrupt request pin. /INT1 (1) /Input Interrupt request terminal 1: Interrupt request pin 1: Rise/fall edge programmable interrupt request pin. /INT2 (1) /Input Interrupt request terminal 2: Interrupt request pin 2: Rise edge interrupt request pin. P50 ~ P53 /AN0 ~ AN3 4 Input P56 /RD 1 Output TOSHIBA CORPORATION Port 4: 8-bit I/O port which allows I/O selection on bit basis (with programmable pull-up resistor). Port 50 ~ 53: 1-bit output ports. Analog input: 4 analog inputs to A/D converter. Port 56: A 1-bit output port. Read: Strobe signal output for reading external memory. 5/18 TMP90CH44 Table 2.2 (2/2) Pin name No. of pins I/O or tristate P57 /WR 1 Output P60 ~ P63 I/O 4 /M00 ~ M03 /Output P70 ~ P73 I/O 4 /M10 ~ M13 6/18 Output Function Port 57: A 1-bit output port. Write: Strobe signal output for writing external memory. Port 6: 4 bit I/O port which allows I/O selection on bit basis. Stepping motor control port 0 or pattern generation port 0. Port 7: 4 bit I/O port which allows I/O selection on bit basis. Stepping motor control port 0 or pattern generation port 1. ALE 1 Output Address latch enable CLK 1 Output Clock output: Generates clock pulse at 1/4 frequency of clock oscillation. It is pulled up internally during resetting. EA 1 Input External access: Connects with VCC pin in the TMP90C844 built ROM is used. RESET 1 Input Reset: Initializes the TMP90C844. (pull-up resistance is built-in). X1, X2 2 I/O Crystal oscillator connection pin Input of reference voltage to A/D converter VREF 1 – AGND 1 – GND pin for A/D converter VCC 1 – Power supply (+5V +/- 10%) GND 1 – GND pin (0V) TOSHIBA CORPORATION TMP90CH44 3. Operation (2) The following explains the TMP90CH44 functions and basic operations. The CPU functions and internal I/O functions of the TMP90CH44 are the same as the TMP90C844. Refer to the “TMP90C844” section concerning functions which are not explained in the following. The MP90CH44 contains a 512-byte built-in RAM which is allocated to the addresses FFC0H ~ FFBFH. The CPU can also access some portions of the RAM (192 byte area FF00H ~ FFBFH) using short instruction codes in the direct addressing mode. Addresses of FF18H ~ FF78H this RAM area can be used as the parameter area for micro DMA processing. (This area can freely be used when the micro DMA function is not used.) 3.1 CPU The TMP90CH44 has an internal high performance 8-bit CPU. Refer to the book TLCS 90 Series CPU Core Architecture section concerning the CPU operation. 3.2 Memory Map The TMP90CH44 can provide a maximum 48K byte program and data memory. The program and data memories may be allocated to the address 0000H ~ FFFFH. (1) Built-in ROM The TMP90CH44 has an internal 16K-byte ROM. This ROM is located at addresses 0000H ~ 3FFFH. Program execution starts from address 0000H after a reset operation. Addresses 0008H ~ 0078H in the internal ROM area are used as the interrupt processing entry area. TOSHIBA CORPORATION Built-in RAM (3) Built-in I/O The TMP90CH44 uses 56 bytes of the address space as a built-in I/O area. The area is allocated to the addresses FFC0H ~ FFF7H. The CPU can access the built-in I/O using short instruction codes in the direct addressing mode. Figure 3.2 shows the memory map and the access ranges of the CPU for each addressing mode. 7/18 TMP90CH44 Figure 3.2. Memory Map 8/18 TOSHIBA CORPORATION TMP90CH44 4. Electrical Characteristics TMP90CH44N/TMP90CH44F 4.1 Absolute Maximum Ratings Symbol Parameter VCC Power supply voltage VIN Input voltage Unit -0.5 ~ + 7 V -0.5 ~ VCC + 0.5 V F 500 Power dissipation (Ta = 85°C) PD Rating mW N 600 260 °C TSTG Storage temperature -65 ~ 150 °C TOPR Operating temperature -40 ~ 85 °C TSOLDER Soldering temperature (10s) 4.2 DC Characteristics VCC = 5V ± 10% TA = -20 ~ 70°C (1 ~ 16MHz) Typical values are for TA = 25°C and Vcc = 5V. Symbol Parameter Min Max Unit Test Conditions VIL Input Low Voltage (P0) -0.3 0.8 V – VIL1 P1, P2, P3, P4, P5, P6, P7 -0.3 0.3VCC V – VIL2 RESET, P45 (INTO) -0.3 0.25VCC V – VIL3 EA -0.3 0.3 V – VIL4 X1 -0.3 0.2VCC V – VIH Input High Voltage (P0) 2.2 VCC + 0.3 V – VIH1 P1, P2, P3, P4, P5, P6, P7 0.7VCC VCC + 0.3 V – VIH2 RESET, P45 (INTO) 0.75VCC VCC + 0.3 V – VIH3 EA VCC - 0.3 VCC + 0.3 V – VIH4 X1 0.8VCC VCC + 0.3 V – VOL Output Low Voltage – 0.45 V IOL = 1.6mA VOH VOH1 VOH2 Output High Voltage 2.4 0.75VCC 0.9VCC – V V V IOH = -400µA IOH = -100µA IOH = -20µA IDAR Darlington Drive Current (8 I/O pins) (Note) -0.1 -3.5 mA VEXT = 1.5V REXT = 1.1kΩ µA 0.0 ≤ Vin ≤ VCC ILI Input Leakage Current 0.02 (Typ) ±5 ILO Output Leakage Current 0.05 (Typ) ± 10 µA 0.2 ≤ Vin ≤ VCC - 0.2 Operating Current (RUN) Idle 1 35 (Typ) 1.5 (Typ) 50 5 mA mA tosc = 16MHz STOP (TA = -20 ~ 70°C) STOP (TA = 0 ~ 50°C) 0.2 (Typ) 40 10 µA µA 0.2 ≤ Vin ≤ VCC - 0.2 VSTOP Power Down Voltage (@STOP) 2.0 6.0 V VIL2 = 0.2VCC, VIH2 = 0.8VCC RRST RESET Pull Up Register 50 150 KΩ – 10 pF 0.4 1.0 (Typ) V ICC CIO Pin Capacitance VTH Schmitt width RESET, P45) TOSHIBA CORPORATION – testfreq = 1MHz – 9/18 TMP90CH44 4.3 AC Characteristics VCC = 5V ± 10% TA = -20 ~ 70°C (1 ~ 16MHz) Variable Symbol tOSC 12.5MHz Clock 16MHz Clock Parameter Oscillation cycle ( = x) Unit Min Max Min Max Min Max 80 1000 80 – 62.5 – ns tCYC CLK Period tWH CLK High width 4x 4x 320 – 250 – ns 2x - 40 – 120 – 85 – ns tWL CLK Low width tAL A0 ~ 7 effective address→ALE fall 2x - 40 – 120 – 85 – ns 0.5x - 15 – 25 – 16 – ns tLA ALE fall →A0 ~ 7 hold 0.5x - 15 – 25 – 16 – ns tLL ALE Pulse width x - 40 – 40 – 23 – ns tLC ALE fall RD/WR fall 0.5x - 30 – 10 – 1 – ns tCL RD/WR →ALE rise 0.5x - 20 – 20 – 11 – ns tACL A0 ~ 7 effective address →RD/WR fall x - 25 – 55 – 38 – ns tACH Upper effective address →RD/WR fall 1.5x - 50 – 70 – 44 – ns tCA RD/WR fall →Upper address hold 0.5x - 20 – 20 – 11 – ns tADL A0 ~ 7 effective address →Effective data input – 3.0x - 35 – 205 – 153 ns tADH Upper effective address →Effective data input – 3.5x - 55 – 225 164 164 ns tRD RD fall →Effective data input – 2.0x - 50 – 110 – 75 ns tRR RD Pulse width 2.0x - 40 – 120 – 85 – ns 0 – 0 – 0 – ns x - 15 – 65 – 48 – ns tHR RD rise →Data hold tRAE RD rise→ Address enable tWW WR pulse width 2.0x - 40 – 120 – 85 – ns tDW Effective data→WR rise 2.0x - 50 – 110 – 75 – ns tWD WR rise→Effective data hold 0.5x - 10 – 30 – 21 – ns tACKH Upper address→CLK fall 2.5x - 50 – 150 – 106 – ns tACKL Lower address →CLK fall 2.0x - 50 – 110 – 75 – ns tCKHA CLK fall→Upper address hold 1.5x - 80 – 40 – 13 – ns tCCK RD/WR→CLK fall x - 25 – 55 – 37 – ns tCKHC CLK fall→RD/WR rise x - 60 – 20 – 2 – ns tDCK Valid data CLK fall x - 50 – 30 – 12 – ns tCWA RD/WR fall→Valid WAIT – x - 40 – 40 – 22 ns tAWAL Lower address →Valid WAIT – 2.0x - 70 – 90 – 55 ns tWAH CLK fall →Valid WAIT hold 0 – 0 – 0 – ns tAWAH Upper address →Valid WAIT – 2.5x - 70 – 130 – 86 ns tCPW CLK fall →Port Data Output – x + 200 – 280 – 262 ns tPRC Port Data Input →CLK fall 200 – 200 – 200 – ns tCPR CLK fall →Port Data hold 100 – 100 – 100 – ns AC Measuring Conditions • Output level: High 2.2V/Low 0.8V, CL = 50pF (However, CL = 100pF for AD0 ~ 7, A8 ~ 15, ALE, RD, WR) • Input level: High 2.4V/Low 0.45V (AD0 ~ AD7) High 0.8VCC/Low 0.2VCC (excluding AD0 ~ AD7) 10/18 TOSHIBA CORPORATION TMP90CH44 4.4 A/D Conversion Characteristics VCC = 5V ± 10% TA = -20 ~ 70°C f = 1 ~ 16MHz Symbol Parameter Condition Min Max VREF Analog reference voltage Vcc - 1.5 Vcc Vcc AGND Analog reference voltage Vss Vss Vss VAIN Analog input voltage range Vss – Vcc IREF Error (Quantize error of ± 0.5 LSB not included) Supply current for analog reference voltage – 0.5 1.0 Total error (TA = 25°C, Vcc = VREF = 5.0V) – – 1.0 Total error – – 2.5 Unit V mA LSB 4.5 Zero-Cross Characteristics VCC = 5V ± 10% TA = -20 ~ 70°C f = 1 ~ 16MHz Symbol Parameter VZX Zero-cross detection input AZX Zero-cross accuracy FZX Zero-cross detection input frequency Condition Min Max Unit AC coupling C = 0.1µF 1 1.8 VAC P - P 50/60Hz sine wave – 135 mV – 0.04 1 kHz 4.6 Timer/ Counter Input Clock (TI0, TI2, and TI4) VCC = 5V ± 10% TA = -20 ~ 70°C f = 1 ~ 16MHz Variable Symbol 12.5MHz Clock 16MHz Clock Parameter Unit Min Max Min Max Min Max tVCK Clock cycle 8x + 100 – 740 – 600 – ns tVCKL Low clock pulse width 4x + 40 – 360 – 290 – ns tVCKH High clock pulse width 4x + 40 – 360 – 290 – ns 4.7 Interrupt Operation VCC = 5V ± 10% TA = -20 ~ 70°C f = 1 ~ 16MHz Variable Symbol 12.5MHz Clock 16MHz Clock Parameter Unit Min Max Min Max Min Max 4x – 320 – 250 – ns 4x – 320 – 250 – ns 8x + 100 – 740 – 600 – ns 8x + 100 – 740 – 600 – ns INT0 Low level pulse width tINTAL tINTAH INT0 High level pulse width INT1, INT2 Low level pulse width tINTBL INT1, INT2 High level pulse width tINTBH TOSHIBA CORPORATION 11/18 TMP90CH44 4.8 Serial Channel Timing - I/O Interface Mode (1) SCLK Input Mode VCC = 5V ± 10% TA = -20 ~ 70°C f = 1 ~ 16MHz Variable Symbol 12.5MHz Clock 16MHz Clock Parameter Unit Min Max Min Max Min Max 16x – 1.28 tSCY/2 - 5x - 50 – 190 – 1 – µs – 137 – ns tSCY SCLK cycle tOSS Output Data →rising edge of SCLK tOHS SCLK Rising Edge→output data hold 5x - 100 – 300 – 212 – ns tHSR SCLK Rising Edge→input data hold 0 – 0 – 0 – ns tSRD SCLK Rising Edge→ effective data input – tSCY - 5x -5 0 – 780 – 587 ns (2) SCLK Output Mode Variable Symbol 12.5MHz Clock 16MHz Clock Parameter Unit Min Max Min Max Min Max 16x 8192x 1.28 tSCY - 2x - 50 – 970 655.4 1 512 µs – 725 – ns tSCY SCLK cycle (programmable) tOSS Output data → SCLK rising edge tOHS SCLK rising edge→output data hold 2x - 80 – 80 – 45 – ns tHSR SCLK rising edge→input data hold 0 – 0 – 0 – ns tSRD SCLK rising edge→ effective data input – tSCY - 2x - 150 – 970 – 725 ns 4.9 Slave Bus Interface Timing: RD, WR Bus Mode VCC = 5V ± 10% TA = -20 ~ 70°C f = 1 ~ 16MHz Symbol 12/18 Parameter Min Max Unit TSAR C/D setup →SRD fall 20 – ns THRA SRD rise→ C/D hold 5 – ns TSCR SCS setup →SRD fall 0 – ns THRC SRD rise →SCS hold TWRD SRD pulse width 0 – ns 120 – ns ns TARD SRD fall →effective data output – 80 TVRB SRD rise →effective data hold 10 85 ns TSAW C/D setup →SWR fall 20 – ns THWA SWR rise →C/D hold 5 – ns TSCW SCR setup →SWR fall 0 – ns ns THWC SWR rise →SCS hold 0 – TWWR SWR pulse width 120 – ns TSBW effective data input →SWR rise 80 – ns THWB SWR rise →effective data hold 10 – ns TOSHIBA CORPORATION TMP90CH44 Slave Bus Interface Timing: DS, R/W Bus Mode Symbol Parameter Min Max Unit TSAD C/D setup →DS fall 20 – ns THDA DSrise→ C/D hold 5 – ns TSCD SCS setup →DS fall 0 – ns THDC DS rise →SCS hold 0 – ns TSAD SCS setup →DS fall 20 – ns THDA DS rise →R/W hold TWDS DS pulse width 5 – ns 120 – ns ns TADS DS fall →effective data output – 80 TVDB DS rise →effective data hold 10 85 ns TSBD Effective data input → DS rise 80 – ns THDB DS rise →effective data hold 10 – ns STA Change Timing X = 1/fosc Variable Symbol 16MHz Clock Parameter Unit Min Max Min Max tRPH STA fall after Output Buffer is read – 2x + 50 – 175 ns tWPH STA rise after Input Buffer is written – 2x + 50 – 175 ns TOSHIBA CORPORATION 13/18 TMP90CH44 4.10 Timing Chart 14/18 TOSHIBA CORPORATION TMP90CH44 4.11 Timing Chart for I/O Interface Mode 4.12 Timing Chart for Slave Bus Interface: RD, WR Bus Mode (1) Read Operation TOSHIBA CORPORATION 15/18 TMP90CH44 (2) Write Operation 16/18 TOSHIBA CORPORATION TMP90CH44 4.13 Timing Chart for Slave Bus Interface: DS, R/W Bus Mode (1) Read Operation TOSHIBA CORPORATION 17/18 TMP90CH44 (2) Write Operation 18/18 TOSHIBA CORPORATION