TOSHIBA TLCS-90 Series TMP90PM36 CMOS 8–Bit Microcontrollers TMP90PM36F/TMP90PM36T 1. Outline and Characteristics The TMP90PM36 is a system evaluation LSI having a Parts No. TMP90PM36F TMP90PM36T built-in One-Time PROM (16K byte) for TMP90CM36. A programming and verification for the internal PROM is acheived by using a general EPROM programmer with an adapter socket. The function of this device is exactly the same as the TMP90CM36 by programming to internal PROM: ROM RAM OTP 32968 x 8bit 1024 x 8bit Package 80-FP 84-QFJ (PLCC) Adapter Socket No. Under Development The information contained here is subject to change without notice. The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equipments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA. TOSHIBA CORPORATION 1/22 TMP90PM36 Figure 1. TMP90PM36 Block Diagram 2/22 TOSHIBA CORPORATION TMP90PM36 2. Pin Assignment and Functions The assignment of input/output pins for TMP90PM36, their names and functions are described below. 2.1 Pin Assignment Figure 2.1 (1) shows pin assignment of the TMP90PM36F. Figure 2.1 (1). Pin Assignments (Flat Package) TOSHIBA CORPORATION 3/22 TMP90PM36 Figure 2.1 (2) shows the pin assignment of TMP90PM36. Figure 2.1 (2). Pin Assignments (QFJ (PLCC) Package) 4/22 TOSHIBA CORPORATION TMP90PM36 2.2 Pin Names and Functions The TMP90PM36 has MCU mode and PROM mode. (1) MCU Mode (The TMP90CM36 is pin compatible). Table 2.2 (1/4) TOSHIBA CORPORATION 5/22 TMP90PM36 Table 2.2 (2/4) 6/22 TOSHIBA CORPORATION TMP90PM36 Table 2.2 (3/4) TOSHIBA CORPORATION 7/22 TMP90PM36 Table 2.2 (4/4) 8/22 TOSHIBA CORPORATION TMP90PM36 (2) PROM Mode Pin Functions Pin Disposal Table 2.2 (2) PROM Mode Name and Function, Pin Disposal TOSHIBA CORPORATION 9/22 TMP90PM36 3. Operation 3.1 MCU Mode The TMP90PM36 is the OTP version of the TMP90CM36 that is replaced an internal ROM from Mask ROM to EPROM. Refer to the TMP90PM36 except for the functions which are not described in this section. The following is an explanation of the hardware configuration and operation in relation to the TMP90CM36. The TMP90PM36 has an MCU mode and a PROM mode. (1) Mode Setting and Function The MCU mode is set by opening the CLK pin (Output status). In the MCU mode, the operation is the same as that of TMP90CM36. (2) Memory Map Figure 3.1 show the memory map of TMP90PM36 and TMP90CM36. Figure 3.1. TMP90PM36 and TMP90CM36 Memory Map 10/22 TOSHIBA CORPORATION TMP90PM36 grammer with the adapter socket. The device selection (ROM Type) should be “TC571000D” with the following conditions. 3.2 PROM Mode (1) Mode Setting and Function PROM mode is set by setting the RESET and CLK pins to the “L” level. The programming and verification for the internal PROM is acheived by using a general EPROM pro- Size: 1M bit (128K x 8bit), VPP: 12.75V± 0.25V, TPW: 0.1ms VCC: 6.25± 0.25V Figure 3.2 shows the setting of pins in PROM mode. Figure 3.2. PROM Mode Pin Setting TOSHIBA CORPORATION 11/22 TMP90PM36 (2) Programming Flow Chart Then, verify the data and increment the address. The verification for all data is done under the condition of VPP = VCC = 5V after all data were written. Figure 3.3 shows the programming flowchart. The programming mode is set by applying 12.75V (programming voltage) to the VPP pin when the following pins are set as follows. (3) (VCC: 6.25V) (RESET: “L” level) (CLK: “L” level) *These conditions can be obtained by using adapter socket. After the address and data have been fixed, a data on the Data Bus is programmed when the PGM pin is set to “Low” (0.1ms plus is required). General programming procedure of an EPROM programmer is as follows. • Write data to a specified address for 0.1ms. • Verify the data. If the read-out data does not match the expected data, another writing is performed until the correct data is written (Max. 25 times). 12/22 The Security Bit The TMP90PM36 has the Security Bit in PROM cell. If the Security Bit is programmed to “0”, the content of the PROM is disable to read in PROM mode. How to program the Security Bit In the PROM Mode (1) Connect P40 pin to VCC (2) Set A0 ~ A16 to “0” respectively (3) Set the 8-bit data to “FEH” TOSHIBA CORPORATION TMP90PM36 (4) Programming Flowchart Figure 3.3. Programming Flowchart TOSHIBA CORPORATION 13/22 TMP90PM36 4. Electrical Characteristics (Preliminary) TMP90PM36F/TMP90PM36T 4.1 Absolute Maximum Ratings Symbol Item Rating VCC Power supply voltage VIN Input voltage ∑IOL Output current (Total) 100 ∑IOL Output current (Total) -70 PD TSOLDER Unit -0.5 ~ + 7 V -0.5 ~ VCC + 0.5 V mA F 500 Power dissipation (Ta = 85°C) mW T 600 Soldering temperature (10s) °C 260 TSTG Storage temperature -65 ~ 150 °C TOPR Operating temperature -40 ~ 85 °C 4.2 DC Characteristics VCC = 5V ± 10% TA = -20 ~ 70°C (1 ~ 16MHz) Typical values are for TA = 25°C and Vcc = 5V. Symbol Min Max Unit Test Conditions VIL Input Low Voltage (P0) -0.3 0.8 V – VIL1 P1, P2, P3, P4, P5, P6, P7 -0.3 0.3VCC V – VIL2 RESET, P81 (INT0), P82 (STBY) -0.3 0.25VCC V – VIL3 EA -0.3 0.3 V – VIL4 X1 -0.3 0.2VCC V – VIH Input High Voltage (P0) 2.2 VCC + 0.3 V – VIH1 P1, P2, P3, P4, P5, P6, P7 0.7VCC VCC + 0.3 V – VIH2 RESET, P81 (INT0), P82 (STBY) 0.75VCC VCC + 0.3 V – VIH3 EA VCC -0 .3 VCC + 0.3 V – VIH4 X1 0.8VCC VCC + 0.3 V VOL Output Low Voltage – 0.45 V IOL = 1.6mA VOH VOH1 VOH2 Output High Voltage 2.4 0.75VCC 0.9VCC – – – V V V IOH = -400µA IOH = -100µA IOH = -20µA IDAR Darlington Drive Current (8 I/O pins max) -1.0 -3.5 mA VEXT = 1.5V REXT = 1.1kΩ µA 0.0 ≤ Vin ≤ VCC – ILI Input Leakage Current 0.02 (Typ) ±5 ILO Output Leakage Current 0.05 (Typ) ± 10 µA 0.2 ≤ Vin ≤ VCC - 0.2 Operating Current (RUN) Idle 35 (Typ) 1.5 (Typ) 50 5 mA mA tosc = 16MHz STOP (TA = -20 ~ 70°C) STOP (TA = 0 ~ 50°C) 0.2 (Typ) 40 10 µA µA 0.2 ≤ Vin ≤ VCC - 0.2 VSTOP Power Down Voltage (@STOP) (RAM back Up) 2.0 6.0 V VIL2 = 0.2VCC, VIH2 = 0.8VCC RRST RESET Pull Up Register 50 150 KΩ CIO Pin Capacitance – 10 pF VTH Schmitt width RESET, P81, P82) 0.4 1.0 (Typ) V ICC 14/22 Item – testfreq = 1MHz – TOSHIBA CORPORATION TMP90PM36 4.3 AC Characteristics VCC = 5V ± 10% TA = -20 ~ 70°C (1 ~ 16MHz) Variable Symbol 12.5MHz Clock 16MHz Clock Parameter Unit Min Max Min Max Min Max 62.5 1000 80 – 62.5 – tOSC Oscillation cycle ( = x) tCYC CLK Period tWH CLK High width tWL CLK Low width tAL A0 ~ 7 effective address→ALE fall tLA ALE fall →A0 ~ 7 hold 0.5x - 15 ns 4x 4x 320 – 250 – ns 2x - 40 – 120 – 85 – ns 2x - 40 – 120 – 85 – ns 0.5x - 15 – 25 – 16 – ns – 25 – 16 – ns tLL ALE Pulse width x - 40 – 40 – 23 – ns tLC ALE fall→ RD/WR fall 0.5x - 30 – 10 – 1 – ns tCL RD/WR →ALE rise 0.5x - 20 – 20 – 11 – ns tACL A0 ~ 7 effective address →RD/WR fall x - 25 – 55 – 38 – ns tACH Upper effective address →RD/WR fall 1.5x - 50 – 70 – 44 – ns tCA RD/WR fall →Upper address hold 0.5x - 20 – 20 – 11 – ns tADL A0 ~ 7 effective address →Effective data input – 3.0x - 35 – 205 – 153 ns tADH Upper effective address →Effective data input – 3.5x - 55 – 225 – 164 ns tRD RD fall →Effective data input – 2.0x - 50 – 110 – 75 ns tRR RD Pulse width 2.0x - 40 – 120 – 85 – ns 0 – 0 – 0 – ns x - 15 – 65 – 48 – ns tHR RD rise →Data hold tRAE RD rise→ Address enable tWW WR pulse width 2.0x - 40 – 120 – 85 – ns tDW Effective data→WR rise 2.0x - 50 – 110 – 75 – ns tWD WR rise→Effective data hold 0.5x - 10 – 30 – 21 – ns tACKH Upper address→CLK fall 2.5x - 50 – 150 – 106 – ns tACKL Lower address →CLK fall 2.0x - 50 – 110 – 75 – ns tCKHA CLK fall→Upper address hold 1.5x - 80 – 40 – 13 – ns tCCK RD/WR→CLK fall x - 25 – 55 – 37 – ns tCKHC CLK fall→RD/WR rise x - 60 – 20 – 2 – ns tDCK Valid data CLK fall x - 50 – 30 – 12 – ns tCWA RD/WR fall→Valid WAIT – x - 40 – 40 - 22 ns tAWAL Lower address →Valid WAIT – 2.0x - 70 – 90 - 55 ns tWAH CLK fall →Valid WAIT hold 0 – 0 – 0 – ns tAWAH Upper address →Valid WAIT – 2.5x - 70 - 130 – 86 ns tCPW CLK fall →Port Data Output – x + 200 - 280 – 262 ns tPRC Port Data Input →CLK fall 200 – 200 200 – ns tCPR CLK fall →Port Data hold 100 – 100 100 – ns AC Measuring Conditions • Output level: High 2.2V/Low 0.8V, CL = 50pF (However, CL = 100pF for AD0 ~ 7, A8 ~ 15, ALE, RD, WR) • Input level: High 2.4V/Low 0.45V (AD0 ~ AD7) High 0.8VCC/Low 0.2VCC (excluding AD0 ~ AD7) High 0.8VCC/Low 0.2VCC (excluding AD0 ~ AD7) TOSHIBA CORPORATION 15/22 TMP90PM36 4.4 A/D Conversion Characteristics VCC = 5V ± 10% TA = -20 ~ 70°C f = 1 ~ 16MHz Symbol Parameter Condition Min Max VREF Analog reference voltage Vcc - 1.5 Vcc Vcc AGND Analog reference voltage Vss Vss Vss VAIN Analog input voltage range Vss – Vcc IREF Analog reference voltage power supply current – 0.5 1.0 Total error (TA = 25°C, Vcc = VREF = 5.0V) – – 1.0 Total error – – 2.5 Error (Quantize error of ± 0.5 LSB not included) Unit V mA LSB 4.5 Timer/Counter Input Clock (TI2, TI4) VCC = 5V ± 10% TA = -20 ~ 70°C f = 1 ~ 16MHz Variable Symbol 12.5MHz Clock 16MHz Clock Item Unit Min Max Min Max Min Max tVCK Clock cycle 8x + 100 – 740 – 600 – ns tVCKL Low clock pulse width 4x + 40 – 360 – 290 – ns tVCKH High clock pulse width 4x + 40 – 360 – 290 – ns 4.6 Interrupt Operation VCC = 5V ± 10% TA = -20 ~ 70°C f = 1 ~ 16MHz Variable Symbol 12.5MHz Clock 16MHz Clock Item Unit Min Max Min Max Min Max 4x – 320 – 250 – ns 4x – 320 – 250 – ns 8x + 100 – 740 – 600 – ns 8x + 100 – 740 – 600 – ns INT0 Low level pulse width tINTAL tINTAH INT0 High level pulse width INT1, INT2 Low level pulse width tINTBL INT1, INT2 High level pulse width tINTBH 16/22 TOSHIBA CORPORATION TMP90PM36 4.7 D/A Conversion Characteristics (VCC = 5V, VSS = AVSS = 0V) VCC = 5V ± 10% TA = -20 ~ 70°C f = 1 ~ 16MHz Symbol Item – Analysis ability Min Typ Max Unit – – 8 Bits – Absoluteness accuracy (VCC = AVCC = 5V) – – 1.0 % tSU Establishment time – – 3 µs RO kΩ Output resistance 1 2 4 VAVSS Analog power supply voltage – 0 – V VDAVREF Analog power supply voltage 4 – VCC V IDAVREF Reference power supply input current 0 2.5 5 mA 4.8 Serial Channel SIO1 Timing - I/O Interface Mode (1) SCLK1 Input Mode VCC = 5V ± 10% TA = -20 ~ 70°C f = 1 ~ 16MHz Variable Symbol 12.5MHz Clock 16MHz Clock Item tSCY SCLK1 cycle Unit Min Max Min Max Min Max 16x – 1.28 – 1 – µs ns tOSS Output data →Rising edge of SCLK tSCY/2 - 5x - 50 – 190 – 137 – tOHS SCLK1 rising edge→Output data hold 5x - 100 – 300 – 212 – ns tHSR SCLK1 rising edge→Input data hold 0 – 0 – 0 – ns tSRD SCLK1 rising edge→ Effective data input – tSCY - 5x - 100 – 780 – 587 ns (2) SCLK1 Output Mode Variable Symbol 12.5MHz Clock 16MHz Clock Parameter tSCY SCLK cycle (programmable) Unit Min Max Min Max Min Max 16x 8192x 1.28 655.4 1 512 µs tOSS Output data setup→SCLK rising edge tSCY - 2x - 50 – 970 – 725 – ns tOHS SCLK rising edge→Output data hold 2x - 80 – 80 – 45 – ns tHSR SCLK rising edge→Input data hold 0 – 0 – 0 – ns tSRD SCLK rising edge→ Effective data input – tSCY - 2x - 150 – 970 – 725 ns TOSHIBA CORPORATION 17/22 TMP90PM36 4.9 Serial Channel SIO2 Timing VCC = 5V ± 10% TA = -20 ~ 70°C f = 1 ~ 16MHz 16MHz Clock Symbol Parameter tSCR Serial port clock cycle time tSCL SCLK2 Low width tSCH SCLK2 High width tSKDO tSRD tHSR Variable Condition SCLK2 → TXD2 (Output data) Unit Min Max Min Max Internal 500 16000 8x 256x External 1000 – 600 – Internal 200 300 4x - 50 4x + 50 External 980 1020 16x - 20 16x + 20 Internal 200 300 4x - 50 4x + 50 External 980 1020 16x - 20 16x + 20 Internal 112.5 – x + 50 – delay time External 475 – 6x + 100 – Internal 377.5 – 7x - 60 – data valid External 1150 – 20x - 100 – Internal 162.5 – x - 100 – External 475 – 6x + 100 – SCLK2 Rising edge to input Input data hold after SCLK2 rising edge ns ns ns ns ns ns 4.10 Read Operation (PROM mode) DC Characteristic, AC Characteristic TA = -20 ~ 70°C VCC = 5V ± 10% Symbol Parameter VPP VIH1 VIL1 VPP read voltage Input high voltage (A0 ~ A15, CE, OE, PGM) Input low voltage (A0 ~ A15, CE, OE, PGM) tACC Address to output delay Condition Min Max Unit – – – 4.5 0.7 x VCC -0.3 5.5 V + 0.3 0.3 x VCC V V V CL = 50PF 2.25TCYC + α – ns TCYC = 250ns (16MHz Clock) α = 100ns 4.11 Read Operation (PROM mode) DC Characteristic, AC Characteristic TA = 25±5°C VCC = 6.25V ± 0.25V Symbol Parameter VPP VIH VIL VPP VIH VIL VIL Programming Algorithm Input high voltage (D0 ~ D7) Input low voltage (D0 ~ D7) Input high voltage (A0 ~ A15, CE, OE, PGM) Input low voltage (A0 ~ A15, CE, OE, PGM) VCC supply current VPP supply current tPW CE program pulse width 18/22 Condition Min Typ Max Unit – – – – – tOSC = 12.75MHz VPP = 13.00V 12.50 0.2VCC + 1.1 -0.3 0.7VCC -0.3 – – 12.75 13.00 VCC + 0.3 0.2VCC - 0.1 VCC + 0.3 0.3VCC 50 50 V V V V V mA mA CL = 50PF 0.095 0.1 0.105 ms TOSHIBA CORPORATION TMP90PM36 4.12 Timing Chart TOSHIBA CORPORATION 19/22 TMP90PM36 4.13 Serial Channel SIO1 I/O Interface Mode Timing Chart 20/22 TOSHIBA CORPORATION TMP90PM36 4.14 Serial Channel SIO2 Timing Chart 4.15 Read Operation Timing Chart (PROM mode) TOSHIBA CORPORATION 21/22 TMP90PM36 4.16 Program OperationTiming Chart (PROM mode) High Speed Program Formula 22/22 TOSHIBA CORPORATION