ETC CS8122/D

CS8122
2.0% 5.0 V, 750 mA Low
Dropout Linear Regulator
with Delayed RESET
The CS8122 is a precision 5.0 V linear regulator capable of sourcing
in excess of 750 mA. The RESET’s delay time is externally
programmed using a discrete RC network. During power up, or when
the output goes out of regulation, the RESET lead remains in the low
state for the duration of the delay. This function is independent of the
input voltage and will function correctly as long as the output voltage
remains at or above 1.0 V. Hysteresis is included in the Delay and the
RESET comparators to improve noise immunity. A latching discharge
circuit is used to discharge the delay capacitor when it is triggered by a
brief fault condition.
The regulator is protected against a variety of fault conditions: i.e.
reverse battery, overvoltage, short circuit and thermal runaway
conditions. The regulator is protected against voltage transients ranging
from –50 V to +40 V. Short circuit current is limited to 1.2 A (typ).
The CS8122 is an improved replacement for the CS8126 and
features a tighter tolerance on its output voltage (2.0% vs. 4.0%).
The CS8122 is packaged in a 5 lead TO–220 with copper tab. The
copper tab can be connected to a heat sink if necessary.
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TO–220
FIVE LEAD
T SUFFIX
CASE 314D
1
TO–220
FIVE LEAD
TVA SUFFIX
CASE 314K
1
TO–220
FIVE LEAD
THA SUFFIX
CASE 314A
1
Features
• 5.0 V ±2.0% Regulated Output
• Low Dropout Voltage (0.6 V @ 0.5 A)
• 750 mA Output Current Capability
• Externally Programmed RESET Delay
• Fault Protection
– Reverse Battery
– 60 V Load Dump
– –50 V Reverse Transient
– Short Circuit
– Thermal Shutdown
5
5
PIN CONNECTIONS AND
MARKING INDIAGRAM
CS8122
AWLYWW
Pin 1. VIN
2. VOUT
3. GND
4. Delay
5. RESET
1
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping
CS8122YT5
TO–220*
STRAIGHT
50 Units/Rail
CS8122YTVA5
TO–220*
VERTICAL
50 Units/Rail
CS8122YTHA5
TO–220*
HORIZONTAL
50 Units/Rail
*Five lead.
 Semiconductor Components Industries, LLC, 2001
March, 2001 – Rev. 5
1
Publication Order Number:
CS8122/D
CS8122
VIN
Over Voltage
Shutdown
VOUT
Regulated Supply
for Circuit Bias
Pre–Regulator
Bandgap
Reference
–
+
Charge
Current
Generator
Delay
Error
Amplifier
Anti–Saturation
and
Current Limit
VOUT
(SENSE)
Thermal
Shutdown
Latching Discharge
–
Q
S
+
R
–
+
VDISC
RESET
Delay
Comparator
+
–
GND
Figure 1. Block Diagram
ABSOLUTE MAXIMUM RATINGS*
Rating
Value
Unit
–0.5 to 26
V
Internally Limited
–
–50, 60
V
Internally Limited
–
4.0
kV
Junction Temperature
–55 to +150
°C
Storage Temperature Range
–55 to +150
°C
260 peak
°C
Input Operating Range
Power Dissipation
Peak Transient Voltage (46 V Load Dump @ VIN = 14 V)
Output Current
Electrostatic Discharge (Human Body Model)
Lead Temperature Soldering:
Wave Solder (through hole styles only) (Note 1.)
1. 10 second maximum.
*The maximum package power dissipation must be observed.
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CS8122
ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ 125°C, –40 ≤ TJ ≤ 150°C, 6.0 ≤ VIN ≤ 26 V, 5.0 mA ≤ IOUT ≤ 500 mA,
RRESET = 4.7 kΩ to VCC unless otherwise noted.) Note 2.
Characteristic
Test Conditions
Min
Typ
Max
Unit
–
4.9
5.0
5.1
V
Output Stage (VOUT)
Output Voltage
Dropout Voltage
IOUT = 500 mA
–
0.35
0.60
V
Supply Current
IOUT ≤ 10 mA
IOUT ≤ 100 mA
IOUT ≤ 500 mA
–
–
–
2.0
6.0
55
7.0
12
100
mA
mA
mA
Line Regulation
6.0 V ≤ VIN ≤ 26 V, IOUT = 50 mA
–
5.0
50
mV
Load Regulation
50 mA ≤ IOUT ≤ 500 mA, VIN = 14 V
–
10
50
mV
Ripple Rejection
f = 120 Hz, 7.0 ≤ VIN ≤ 17 V, IOUT = 250 mA
54
75
–
dB
Current Limit
–
0.75
1.20
–
A
Overvoltage Shutdown
–
32
–
40
V
Maximum Line Transient
VOUT ≤ 5.5 V
60
95
–
V
Reverse Polarity Input Voltage DC
VOUT ≥ –0.6 V, 10 Ω Load
–15
–30
–
V
Reverse Polarity Input Voltage Transient
1.0% Duty Cycle, T < 100 ms, 10 Ω Load
–50
–80
–
V
Thermal Shutdown
Guaranteed by Design
150
180
210
°C
Delay Charge Current
VDELAY = 2.0 V
5.0
10
15
µA
RESET Threshold
VOUT Increasing, VRT(ON)
VOUT Decreasing, VRT(OFF)
4.65
4.50
4.90
4.70
VOUT – 0.01
VOUT – 0.16
V
V
RESET Hysteresis
VRH = VRT(ON) – VRT(OFF)
150
200
250
mV
Delay Threshold
Charge, VDC(HI)
Discharge, VDC(L)
3.25
2.85
3.50
3.10
3.75
3.35
V
V
200
400
800
mV
RESET and Delay Functions
Delay Hysteresis
–
RESET Output Voltage Low
1.0 V < VOUT < VRT(L), 3.0 kΩ to VOUT
–
0.1
0.4
V
RESET Output Leakage
VOUT > VRT(H)
0
–
10
µA
Delay Capacitor Discharge Voltage
Discharge Latched “ON”, VOUT > VRT
–
0.2
0.5
V
Delay Time
CDELAY = 0.1 µF
16
32
48
ms
2. To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable.
CDelay VDelay Threshold Charge
DelayTime CDelay 3.5 105(typ)
ICharge
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3
CS8122
PACKAGE LEAD DESCRIPTION
PACKAGE LEAD #
TO–220
5 LEAD
LEAD SYMBOL
1
VIN
2
VOUT
Regulated 5.0 V output.
3
GND
Ground Connection.
4
Delay
Timing capacitor for RESET function.
5
RESET
FUNCTION
Unregulated supply voltage to IC.
CMOS/TTL compatible output lead. RESET goes low whenever VOUT drops below 6.0% of it’s regulated value.
TYPICAL PERFORMANCE CHARACTERISTICS
120
RLOAD = 25 Ω
45
Quiescent Current. (mA)
Quiescent Current (mA)
55
50
40
35
30
125°C
25
20
15
25°C
RLOAD = 6.67 Ω
100
10
80
60
RLOAD = 10 Ω
40
RLOAD = 25 Ω
20
–40°C
5
0
Room Temp
RLOAD = NO LOAD
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
VIN (V)
4.5
4.5
4.0
4.0
3.5
3.5
3.0
125°C
2.5
2.0
8
9
10
RLOAD = 6.67 Ω
3.0
RLOAD =
NO LOAD
2.5
2.0
1.5
1.5
1.0
25°C
0.5
0
7
Room Temp
5.0
VOUT (V)
VOUT (V)
5.5
RLOAD = 25 Ω
5.0
6
Figure 3. Quiescent Current vs. Input
Voltage Over Load Resistance
Figure 2. Quiescent Current vs. Input Voltage
Over Temperature
5.5
5
VIN (V)
0
1
2
3
1.0
–40°C
RLOAD = 10 Ω
0.5
4
5
6
7
8
9
0
10
0
1
2
3
4
5
6
7
8
9
VIN (V)
VIN (V)
Figure 4. Output Voltage vs. Input Voltage
Over Temperature
Figure 5. VOUT vs. VIN Over RLOAD
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10
CS8122
TYPICAL PERFORMANCE CHARACTERISTICS
100
6
80
4
VIN = 6–26 V
40
20
TEMP = 25°C
TEMP = –40°C
0
–20
–40
TEMP = 125°C
–60
0
–2
–6
–8
–10
–12
–100
–14
100
200
300
400
TEMP = 25°C
–4
–80
0
TEMP = –40°C
2
Load Regulation (mV)
Line Reg. (mV)
60
500
600
700
TEMP = 125°C
VIN = 14 V
0
800
100
200
100
800
90
700
80
Quiescent Current (mA)
Dropout Voltage (mV)
900
25°C
600
500
125°C
300
–40°C
200
100
0
400
500
70
25°C
125°C
60
50
40
30
20
–40°C
10
0
0
100
200
300
400
500
600
700
800
0
100
200
300
800
CO = 47/68 µF
101
ESR (ohms)
60
50
Stable Region
100
10–1
COUT = 10 µF, ESR = 1.0 Ω
30
700
102
70
40
600
103
COUT = 10 µF, ESR = 1.0 & 0.1 µF,
ESR = 0
80
500
Figure 9. Quiescent Current vs. Output Current
IOUT = 250 mA
90
400
Output Current (mA)
Figure 8. Dropout Voltage vs. Output Current
Rejection (dB)
800
700
VIN = 14 V
Output Current (mA)
CO = 47 µF
10–2
20
COUT = 10 µF, ESR = 1.0 Ω
10
0
600
Figure 7. Load Regulation vs. Output Current
Figure 6. Line Regulation vs. Output Current
400
300
Output Current (mA)
Output Current (mA)
100
101
102
103
104
105
106
CO = 68 µF
10–3
107
10–4
108
100
Frequency (Hz)
101
102
Output Current (mA)
Figure 11. Output Capacitor ESR
Figure 10. Ripple Rejection
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5
103
CS8122
VOUT
(1) = No Delay Capacitor
(2) = With Delay Capacitor
(3) = Max: RESET Voltage (1.0 V)
VRH
VRT(ON)
VRT(OFF)
RESET
(1)
(3)
(2)
VRL
tDELAY
DELAY
VDH
VDC(HI)
VDC(LO)
(2)
VDIS
Figure 12. RESET Circuit Waveform
CIRCUIT DESCRIPTION
The CS8122 RESET function, has hysteresis on both the
reset and delay comparators, a latching Delay capacitor
discharge circuit, and operates down to 1.0 V.
The RESET circuit output is an open collector type with
ON and OFF parameters as specified. The RESET output
NPN transistor is controlled by the two circuits described
(see Block Diagram on page 2).
delay capacitor). The discharge current is latched ON when
the output voltage is below VRT(OFF). The Delay capacitor
is fully discharged anytime the output voltage falls out of
regulation, even for a short period of time. This feature
ensures that a controlled RESET pulse is generated
following detection of an error condition. The circuit allows
the RESET output transistor to go to the OFF (open) state
only when the voltage on the Delay lead is higher than
VDC(HI).
Low Voltage Inhibit Circuit
The Low Voltage Inhibit Circuit monitors output voltage,
and when output voltage is below the specified minimum,
causes the RESET output transistor to be in the ON
(saturation) state. When the output voltage is above the
specified level, this circuit permits the RESET output
transistor to go into the OFF state if allowed by the RESET
Delay circuit.
VOUT
VIN
CIN*
100 nF
CS8122
RRST
4.7 kΩ
RESET
Delay
GND
CDelay
0.1 µF
Reset Delay Circuit
The Reset Delay Circuit provides a programmable (by
external capacitor) delay on the RESET output lead. The
Delay lead provides source current to the external delay
capacitor only when the Low Voltage Inhibit circuit
indicates that output voltage is above VRT(ON). Otherwise,
the Delay lead sinks current to ground (used to discharge the
*CIN is required if regulator is far from the power source filter.
**COUT is required for stability.
Figure 13. Test Circuit
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6
COUT**
10 µF
CS8122
APPLICATION NOTES
STABILITY CONSIDERATIONS
Once the minimum capacitor value with the maximum
ESR is found, a safety factor should be added to allow for the
tolerance of the capacitor and any variations in regulator
performance. Most good quality aluminum electrolytic
capacitors have a tolerance of ± 20% so the minimum value
found should be increased by at least 50% to allow for this
tolerance plus the variation which will occur at low
temperatures. The ESR of the capacitor should be less than
50% of the maximum allowable ESR found in step 3 above.
The output or compensation capacitor, COUT, helps
determine three main characteristics of a linear regulator:
start–up delay, load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (–25°C to –40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturers data sheet usually provides this information.
The value for the output capacitor COUT shown in Figure
13 should work for most applications, however it is not
necessarily the optimized solution.
To determine an acceptable value for COUT for a particular
application, start with a tantalum capacitor of the
recommended value and work towards a less expensive
alternative part.
Step 1: Place the completed circuit with a tantalum
capacitor of the recommended value in an environmental
chamber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade box
outside the chamber, the small resistance added by the
longer leads is negligible.
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load while
observing the output for any oscillations. If no oscillations
are observed, the capacitor is large enough to ensure a stable
design under steady state conditions.
Step 3: Increase the ESR of the capacitor from zero using
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that cause
the greatest oscillation. This represents the worst case load
conditions for the regulator at low temperature.
Step 4: Maintain the worst case load conditions set in
step 3 and vary the input voltage until the oscillations
increase. This point represents the worst case input voltage
conditions.
Step 5: If the capacitor is adequate, repeat steps 3 and 4
with the next smaller valued capacitor. A smaller capacitor
will usually cost less and occupy less board space. If the
output oscillates within the range of expected operating
conditions, repeat steps 3 and 4 with the next larger standard
capacitor value.
Step 6: Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
Step 7: Raise the temperature to the highest specified
operating temperature. Vary the load current as instructed in
step 5 to test for any oscillations.
CALCULATING POWER DISSIPATION IN A SINGLE
OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output
regulator (Figure 14) is:
PD(max) VIN(max) VOUT(min)IOUT(max) VIN(max)IQ
(1)
where:
VIN(max) is the maximum input voltage,
VOUT(min) is the minimum output voltage,
IOUT(max) is the maximum output current for the
application, and
IQ is the quiescent current the regulator consumes at
IOUT(max).
Once the value of PD(max) is known, the maximum
permissible value of RΘJA can be calculated:
RJA 150°C TA
PD
(2)
The value of RΘJA can then be compared with those in the
package section of the data sheet. Those packages with
RΘJA’s less than the calculated value in equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
IIN
VIN
SMART
REGULATOR
IOUT
Control
Features
IQ
Figure 14. Single Output Regulator With Key
Performance Parameters Labeled
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VOUT
CS8122
HEAT SINKS
where:
RΘJC = the junction–to–case thermal resistance,
RΘCS = the case–to–heatsink thermal resistance, and
RΘSA = the heatsink–to–ambient thermal resistance.
RΘJC appears in the package section of the data sheet. Like
RΘJA, it too is a function of package type. RΘCS and RΘSA
are functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heat sink manufacturers.
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RΘJA.
RJA RJC RCS RSA
(3)
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CS8122
PACKAGE DIMENSIONS
TO–220
FIVE LEAD
T SUFFIX
CASE 314D–04
ISSUE E
–T–
–Q–
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 10.92 (0.043) MAXIMUM.
C
B
E
A
U
L
K
J
H
G
D
DIM
A
B
C
D
E
G
H
J
K
L
Q
U
1234 5
5 PL
0.356 (0.014)
M
T Q
M
INCHES
MIN
MAX
0.572
0.613
0.390
0.415
0.170
0.180
0.025
0.038
0.048
0.055
0.067 BSC
0.087
0.112
0.015
0.025
0.990
1.045
0.320
0.365
0.140
0.153
0.105
0.117
MILLIMETERS
MIN
MAX
14.529 15.570
9.906 10.541
4.318
4.572
0.635
0.965
1.219
1.397
1.702 BSC
2.210
2.845
0.381
0.635
25.146 26.543
8.128
9.271
3.556
3.886
2.667
2.972
TO–220
FIVE LEAD
TVA SUFFIX
CASE 314K–01
ISSUE O
–T–
SEATING
PLANE
C
B
–Q–
E
W
A
U
F
L
1
2
3
4
K
5
M
D
0.356 (0.014)
M
J
5 PL
T Q
M
G
S
R
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NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 10.92 (0.043) MAXIMUM.
DIM
A
B
C
D
E
F
G
J
K
L
M
Q
R
S
U
W
INCHES
MIN
MAX
0.560
0.590
0.385
0.415
0.160
0.190
0.027
0.037
0.045
0.055
0.530
0.545
0.067 BSC
0.014
0.022
0.785
0.800
0.321
0.337
0.063
0.078
0.146
0.156
0.271
0.321
0.146
0.196
0.460
0.475
5°
MILLIMETERS
MIN
MAX
14.22
14.99
9.78
10.54
4.06
4.83
0.69
0.94
1.14
1.40
13.46
13.84
1.70 BSC
0.36
0.56
19.94
20.32
8.15
8.56
1.60
1.98
3.71
3.96
6.88
8.15
3.71
4.98
11.68
12.07
5°
CS8122
TO–220
FIVE LEAD
THA SUFFIX
CASE 314A–03
ISSUE E
–T–
B
–P–
Q
C
E
OPTIONAL
CHAMFER
A
U
F
L
G
5X
K
5X
S
D
0.014 (0.356)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 0.043 (1.092) MAXIMUM.
SEATING
PLANE
M
T P
M
J
DIM
A
B
C
D
E
F
G
J
K
L
Q
S
U
INCHES
MIN
MAX
0.572
0.613
0.390
0.415
0.170
0.180
0.025
0.038
0.048
0.055
0.570
0.585
0.067 BSC
0.015
0.025
0.730
0.745
0.320
0.365
0.140
0.153
0.210
0.260
0.468
0.505
PACKAGE THERMAL DATA
Parameter
TO–220
FIVE LEAD
Unit
RΘJC
Typical
2.1
°C/W
RΘJA
Typical
50
°C/W
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MILLIMETERS
MIN
MAX
14.529 15.570
9.906 10.541
4.318
4.572
0.635
0.965
1.219
1.397
14.478 14.859
1.702 BSC
0.381
0.635
18.542 18.923
8.128
9.271
3.556
3.886
5.334
6.604
11.888 12.827
CS8122
Notes
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CS8122
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
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attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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http://onsemi.com
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