SONY CXK77Q36162GB 25/27/3 Preliminary 16Mb DDR1 HSTL High Speed Synchronous SRAM (512K x 36) Description The CXK77Q36162GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 524,288 words by 36 bits. This synchronous SRAM integrates input registers, high speed RAM, output registers, and a two-deep write buffer onto a single monolithic IC. Single Data Rate (SDR) and Double Data Rate (DDR) Register - Register (R-R) Read operations and Late Write (LW) Write operations are supported, providing a flexible, high-performance user interface. Continue operations are supported, providing burst capability. Positive and negative output clocks are provided for applications requiring sourcesynchronous operation. All address and control input signals except the G output enable signal are registered on the rising edge of the CK differential input clock. All commands are input via the B(1:3) control signals. During SDR read operations, output data is driven valid once, from the rising edge of CK, one full clock cycle after the address is registered. During DDR read operations, output data is driven valid twice, first from the rising edge of CK and then from the falling edge of CK, beginning one full clock cycle after the address is registered. In both cases, output data transitions are closely aligned with output clock transitions. During SDR write operations, input data is registered once, on the rising edge of CK, one full clock cycle after the address is registered. During DDR write operations, input data is registered twice, first on the rising edge of CK and then on the falling edge of CK, beginning one full clock cycle after the address is registered. Output drivers are series terminated, and output impedance is programmable via the ZQ input pin. By connecting an external control resistor RQ between ZQ and VSS, the impedance of all data and clock output drivers can be precisely controlled. 400 MHz operation (800 Mbps) is obtained from a single 2.5V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol. Features • 3 Speed Bins Cycle Time / Access Time Data Rate -25 2.5ns / 1.8ns 800 Mbps -27 2.7ns / 1.9ns 740 Mbps -3 3.0ns / 2.0ns 666 Mbps • Single 2.5V power supply (VDD): 2.5V ± 5% • Dedicated output supply voltage (VDDQ): 1.5V ± 0.1V • HSTL-compatible I/O interface with dedicated input reference voltage (VREF): 0.75V typical • DDR1 functional compatibility • Register - Register (R-R) read protocol • Late Write (LW) write protocol • Single Data Rate (SDR) and Double Data Rate (DDR) data transfers • Burst capability via Continue commands • Linear or interleaved burst order, selectable via dedicated mode pin (LBO) • Full read/write coherency • Two cycle deselect • Differential input clocks (CK/CK) • Positive and negative output clocks (CQ/CQ) - one pair per 18 bits of output data (DQ) • Asynchronous output enable (G) • Programmable output driver impedance • JTAG boundary scan (subset of IEEE standard 1149.1) • 153 pin (9x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package 16Mb DDR1, rev 1.0 1 / 24 July 3, 2002 SONY® Preliminary CXK77Q36162GB Pin Assignment (Top View) 1 2 3 4 5 6 7 8 9 A VSS VDDQ SA SA ZQ SA SA VDDQ V SS B DQ DQ SA V SS B1 V SS SA DQ DQ C VSS VDDQ SA SA G SA SA VDDQ V SS D DQ DQ SA V SS VDD V SS SA DQ DQ E VSS VDDQ VSS VDD VREF VDD V SS VDDQ V SS F DQ CQ DQ VDD VDD VDD DQ CQ DQ G VSS VDDQ VSS V SS CK V SS V SS VDDQ V SS H DQ DQ DQ VDD CK VDD DQ DQ DQ J VSS VDDQ VSS VDD VDD VDD V SS VDDQ V SS K DQ DQ DQ V SS B2 V SS DQ DQ DQ L VSS VDDQ VSS LBO B3 NC (1) V SS VDDQ V SS M DQ CQ DQ VDD VDD VDD DQ CQ DQ N VSS VDDQ VSS VDD VREF VDD V SS VDDQ V SS P DQ DQ NC (x18) V SS VDD V SS SA DQ DQ R VSS VDDQ VDD SA SA1 SA VDD VDDQ V SS T DQ DQ SA V SS SA0 V SS SA DQ DQ U VSS VDDQ TMS TDI TCK TDO RSVD (2) VDDQ V SS Notes: 1. Pad Location 6L is a true no-connect. However, it may be defined as a mode pin in future versions of DDR SRAMs. 2. Pad Location 7U must be left unconnected. It is used by Sony for internal test purposes. 16Mb DDR1, rev 1.0 2 / 24 July 3, 2002 SONY® CXK77Q36162GB Preliminary Pin Description Symbol Type Description SA Input Synchronous Address Inputs - Registered on the rising edge of CK. SA1, SA0 Input Synchronous Address Inputs (1:0) - Registered on the rising edge of CK. Initialize burst counter. DQ I/O Synchronous Data Inputs / Outputs - Registered on the rising edge of CK during SDR Write operations. Registered on the rising and falling edges of CK during DDR Write operations. Driven from the rising edge of CK during SDR Read operations. Driven from the rising and falling edges of CK during DDR Read operations. CK, CK Input Differential Input Clocks CQ, CQ I/O Output Clocks B1, B2, B3 Input Synchronous Control Inputs (1:3) - Registered on the rising edge of CK. Specify the type of operation (SDR Read, SDR Write, DDR Read, DDR Write, Continue, or Deselect) to be executed by the SRAM. See the Clock Truth Table and State Diagram sections for further information. G Input Asynchronous Output Enable Input - Deasserted (high) disables the data output drivers. LBO Input Burst Order Select Input - This mode pin must be tied “high” or “low” at power-up. LBO = 0 selects Linear burst order LBO = 1 selects Interleaved burst order ZQ Input Output Impedance Control Resistor Input - This pin must be connected to VSS through an external resistor RQ to program data and clock output driver impedance. See the Programmable Output Driver Impedance section for further information. VDD 2.5V Core Power Supply - Core supply voltage. VDDQ Output Power Supply - Output buffer supply voltage. VREF Input Reference Voltage - Input buffer threshold voltage. VSS Ground TCK Input JTAG Clock TMS Input JTAG Mode Select - Weakly pulled “high” internally. TDI Input JTAG Data In - Weakly pulled “high” internally. TDO Output JTAG Data Out RSVD Reserved - This pin is used for Sony test purposes only. It must be left unconnected. NC No Connect - These pins are true no-connects, i.e. there is no internal chip connection to these pins. They can be left unconnected or tied directly to VDD, VDDQ, or VSS. 16Mb DDR1, rev 1.0 3 / 24 July 3, 2002 SONY® Preliminary CXK77Q36162GB Clock Truth Table CK B1 B2 B3 (tn) (tn) (tn) Previous Operation Current Operation 0→1 0 1 1 --- Single Data Rate Read Load New Address 0→1 0 1 0 --- Double Data Rate Read Load New Address 0→1 0 0 1 --- Single Data Rate Write Load New Address Flush Write Buffer 0→1 0 0 0 --- Double Data Rate Write Load New Address Flush Write Buffer 0→1 1 1 X SDR Read Single Data Rate Read Continue Increment Address by One 0→1 1 1 X DDR Read Double Data Rate Read Continue Increment Address by Two 0→1 1 1 X SDR Write Single Data Rate Write Continue Increment Address by One Flush Write Buffer 0→1 1 1 X DDR Write Double Data Rate Write Continue Increment Address by Two Flush Write Buffer 0→1 1 0 X not Deselect Deselect 0→1 1 X X Deselect DQ (tn+½) DQ (tn) DQ (tn+1) Q1(tn) X X Q1(tn) X X Deselect (Continue) X D1(tn) Q1(tn-1) D2(tn) Q2(tn) Q2(tn-1) Q3(tn) D1(tn-1) D1(tn-1) Q2(tn) D1(tn) X Q1(tn-1) DQ (tn+1½) Q4(tn) D2(tn) D2(tn-1) D3(tn) D4(tn) X Hi - Z Hi - Z Hi - Z State Diagram B2.B3 SDR Read B1.B2 B1 Increment Address By One B1.B2 B1.B2 B2.B3 B1 SDR Write Flush WB Load New Address B1.B2 Increment Address By One Deselect Flush WB B1 B1 DDR Read B2.B3 B1.B2 B1 Increment Address By Two B1.B2 B1.B2 B1 B2.B3 16Mb DDR1, rev 1.0 DDR Write Flush WB B1.B2 4 / 24 Increment Address By Two Power Up July 3, 2002 SONY® Preliminary CXK77Q36162GB •Continue Operations These devices support Continue (Burst) operations via the synchronous B(1:3) control input signals. They have the ability to burst transfer a maximum of four (4) distinct pieces of data per single external address input, regardless whether the data transfers are SDR or DDR. SDR Read and Write operations transfer one (1) piece of data. Consequently, one (1), two (2), or three (3) Continue operations may be initiated immediately after an SDR Read or Write operation to burst transfer two (2), three (3), or four (4) distinct pieces of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial external (base) address. DDR Read and Write operations transfer two (2) pieces of data. Consequently, one (1) Continue operation may be initiated immediately after a DDR Read or Write operation to burst transfer four (4) distinct pieces of data per single external address input. If a second (2nd) Continue operation is initiated, the internal address wraps back to the initial external (base) address. The order (i.e. address sequence) in which multiple pieces of data are transferred during DDR and/or Continue operations is determined by the state of LBO mode pin. When LBO = 1, data transfers follow the Interleaved Burst address sequence depicted in the table below: Interleaved Burst Address Sequence Address Sequence SA(1:0) Sequence Key 1st (Base) Address 00 01 10 11 SA1, SA0 2nd Address 01 00 11 10 SA1, SA0 3rd Address 10 11 00 01 SA1, SA0 4th Address 11 10 01 00 SA1, SA0 When LBO = 0, data transfers follow the Linear Burst address sequence depicted in the table below:. Linear Burst Address Sequence Address Sequence SA(1:0) Sequence Key 1st (Base) Address 00 01 10 11 SA1, SA0 2nd Address 01 10 11 00 (SA1 xor SA0), SA0 3rd Address 10 11 00 01 SA1, SA0 4th Address 11 00 01 10 (SA1 xor SA0), SA0 •Programmable Impedance Output Drivers These devices have programmable impedance output drivers. The output impedance is controlled by an external resistor RQ connected between the SRAM’s ZQ pin and VSS, and is equal to one-fifth the value of this resistor, nominally. See the DC Electrical Characteristics section for further information. Output Driver Impedance Power-Up Requirements Output driver impedance will reach the programmed value within 8192 cycles after power-up. Consequently, it is recommended that Read operations not be initiated until after the initial 8192 cycles have elapsed. Output Driver Impedance Updates Data output impedance is updated during Write and Deselect operations when the output driver is disabled. Clock pull-up output impedance is updated during Write and Deselect operations when the output driver is driving “low”. Clock pull-down output impedance is updated during Write and Deselect operations when the output driver is driving “high”. 16Mb DDR1, rev 1.0 5 / 24 July 3, 2002 SONY® Preliminary CXK77Q36162GB •Power-Up Sequence For reliability purposes, Sony recommends that power supplies power up in the following sequence: VSS, VDD, VDDQ, VREF, and Inputs. VDDQ should never exceed VDD. If this power supply sequence cannot be met, a large bypass diode may be required between VDD and VDDQ. Please contact Sony Memory Application Department for further information. •Absolute Maximum Ratings Parameter Symbol Rating Units Supply Voltage VDD -0.5 to +3.0 V Output Supply Voltage VDDQ -0.5 to +2.3 V VIN -0.5 to V DDQ+0.5 (2.3V max) V Input Voltage (LBO) VMIN -0.5 to V DDQ+0.5 (2.3V max) V Input Voltage (TCK, TMS, TDI) VTIN -0.5 to VDD+0.5 (3.0V max) V Operating Temperature TA 0 to 85 °C Junction Temperature TJ 0 to 110 °C Storage Temperature TSTG -55 to 150 °C Input Voltage (Address, Control, Data, Clock) Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. •BGA Package Thermal Characteristics Parameter Junction to Case Temperature Symbol Rating Units ΘJC 1.0 °C/W •I/O Capacitance (TA = 25oC, f = 1 MHz) Parameter Input Capacitance Symbol Test conditions Min Max Units Address CIN VIN = 0V --- 4.2 pF Control CIN VIN = 0V --- 4.2 pF CK Clock CKIN VKIN = 0V --- 3.5 pF Data COUT VOUT = 0V --- 4.8 pF CQ Clock COUT VOUT = 0V --- 4.8 pF Output Capacitance Note: These parameters are sampled and are not 100% tested. 16Mb DDR1, rev 1.0 6 / 24 July 3, 2002 SONY® Preliminary CXK77Q36162GB •DC Recommended Operating Conditions Parameter (VSS = 0V, TA = 0 to 85oC) Symbol Min Typ Max Units Notes Supply Voltage VDD 2.37 2.5 2.63 V Output Supply Voltage VDDQ 1.4 1.5 1.6 V Input Reference Voltage VREF 0.65 0.75 0.85 V 1 Input High Voltage (Address, Control, Data) VIH VREF + 0.2 --- VDDQ + 0.3 V 2 Input Low Voltage (Address, Control, Data) VIL -0.3 --- VREF - 0.2 V 3 Input High Voltage (LBO) VMIH VREF + 0.3 --- VDDQ + 0.3 V Input Low Voltage (LBO) VMIL -0.3 --- VREF - 0.3 V Clock Input Signal Voltage VKIN -0.3 --- VDDQ + 0.3 V Clock Input Differential Voltage VDIF 0.2 --- VDDQ + 0.6 V Clock Input Common Mode Voltage VCM 0.65 0.75 0.85 V 1. The peak-to-peak AC component superimposed on V REF may not exceed 5% of the DC component. 2. V IH (max) AC = VDDQ + 0.75V for pulse widths less than one-quarter of the cycle time (tCYC/4). 3. V IL (min) AC = -0.75V for pulse widths less than one-quarter of the cycle time (tCYC/4). 16Mb DDR1, rev 1.0 7 / 24 July 3, 2002 SONY® Preliminary CXK77Q36162GB •DC Electrical Characteristics Parameter Symbol Input Leakage Current (Address, Control, Clock) ILI Input Leakage Current (LBO) IMLI Output Leakage Current ILO Average Power Supply Operating Current (VDD = 2.5V ± 5%, VSS = 0V, TA = 0 to 85oC) Test Conditions Min Typ Max Units VIN = V SS to VDDQ -5 --- 5 uA VMIN = VSS to V DDQ -10 --- 10 uA -10 --- 10 uA --- --- 750 mA VDDQ - 0.4 --- --- V --- --- 0.4 V --- --- 35 Ω VDIN = V SS to VDDQ G = VIH Notes IOUT = 0 mA IDD VIN = V IH or VIL tCYC = 275 MHz IOH = -6.0 mA Output High Voltage VOH RQ = 250 Ω Output Low Voltage VOL RQ = 250 Ω IOL = 6.0 mA VOH, VOL = VDDQ/2 RQ < 150Ω Output Driver Impedance ROUT VOH, VOL = VDDQ/2 (RQ/5)* 150Ω ≤ RQ ≤ 300Ω 0.85 VOH, VOL = VDDQ/2 51 RQ > 300Ω (60*0.85) RQ/5 (30*1.15) (RQ/5)* --- 1.15 --- 1 Ω Ω 2 1. For maximum output drive (i.e. minimum impedance), the ZQ pin can be tied directly to VSS. 2. For minimum output drive (i.e. maximum impedance), the ZQ pin can be left unconnected or tied to VDDQ. 16Mb DDR1, rev 1.0 8 / 24 July 3, 2002 SONY® Preliminary CXK77Q36162GB •AC Electrical Characteristics (VDD = 2.5V ± 5%, VSS = 0V, TA = 0 to 85oC) -25 Parameter -27 -3 Symbol Units Min Max Min Max Min Max Notes Input Clock Cycle Time tKHKH 2.5 --- 2.7 --- 3.0 --- ns Input Clock High Pulse Width Input Clock Low Pulse Width tKHKL tKLKH 1.0 --- 1.1 --- 1.2 --- ns Address Input Setup Time tAVKH 0.35 --- 0.35 --- 0.35 --- ns 1 Address Input Hold Time tKHAX 0.35 --- 0.35 --- 0.35 --- ns 1 Control Input Setup Time tBVKH 0.35 --- 0.35 --- 0.35 --- ns 1 Control Input Hold Time tKHBX 0.35 --- 0.35 --- 0.35 --- ns 1 Data Input Setup Time tDVKH tDVKL 0.25 --- 0.25 --- 0.3 --- ns 1 Data Input Hold Time tKHDX tKLDX 0.25 --- 0.25 --- 0.3 --- ns 1 Input Clock High to Output Data Valid Input Clock Low to Output Data Valid tKHQV tKLQV --- 1.8 ---- 1.9 --- 2.0 ns Input Clock High to Output Data Hold Input Clock Low to Output Data Hold tKHQX tKLQX 0.5 --- 0.5 --- 0.5 --- ns 1 Input Clock High to Output Data Low-Z tKHQX1 0.5 --- 0.5 --- 0.5 --- ns 1,2 Input Clock High to Output Data High-Z tKHQZ --- 1.8 ---- 1.9 --- 2.0 ns 1,2 Input Clock Cross to Output Clock High Input Clock Cross to Output Clock Low tKXCH tKXCL 0.5 1.8 0.5 1.9 0.5 2.0 ns Output Clock High to Output Data Valid Output Clock Low to Output Data Valid tCHQV tCLQV --- 0.2 --- 0.2 --- 0.2 ns 1 Output Clock High to Output Data Hold Output Clock Low to Output Data Hold tCHQX tCLQX -0.2 --- -0.2 --- -0.2 --- ns 1 Output Clock High Pulse Width tCHCL tKHKL ± 0.1 tKHKL ± 0.1 tKHKL ± 0.1 ns 1 Output Clock Low Pulse Width tCLCH tKLKH ± 0.1 tKLKH ± 0.1 tKLKH ± 0.1 ns 1 Output Enable Low to Output Valid tGLQV --- 1.8 ---- 1.9 --- 2.0 ns Output Enable Low to Output Low-Z tGLQX 0.3 --- 0.3 --- 0.3 --- ns 1,2 Output Enable High to Output High-Z tGHQZ --- 1.8 --- 1.9 --- 2.0 ns 1,2 1. These parameters are guaranteed by design through extensive corner lot characterization. 2. These parameters are measured at ± 50mV from steady state voltage. 16Mb DDR1, rev 1.0 9 / 24 July 3, 2002 SONY® CXK77Q36162GB Preliminary •AC Electrical Characteristics (Note) The four AC timing parameters listed below are tested according to specific combinations of output clocks and output data: 1. tCHQV - Output Clock High to Output Data Valid (max) 2. tCLQV - Output Clock Low to Output Data Valid (max) 3. tCHQX - Output Clock High to Output Data Hold (min) 4. tCLQX - Output Clock Low to Output Data Hold (min) The specific CQ / DQ combinations are defined as follows: 16Mb DDR1, rev 1.0 CQs DQs 2F, 8M 1D, 1H, 1M, 1T, 2B, 2K, 2P, 3H, 3M, 7F, 7K, 8D, 8H, 8T, 9B, 9F, 9K, 9P 2M, 8F 1B, 1F, 1K, 1P, 2D, 2H, 2T, 3F, 3K, 7H, 7M, 8B, 8K, 8P, 9D, 9H, 9M, 9T 10 / 24 July 3, 2002 SONY® Preliminary CXK77Q36162GB •AC Test Conditions (VDD = 2.5V ± 5%, VDDQ = 1.5V ± 0.1V, TA = 0 to 85°C) Item Symbol Conditions Units VREF 0.75 V Input High Level VIH 1.25 V Input Low Level VIL 0.25 V Input Rise & Fall Time 2.0 V/ns Input Reference Level 0.75 V Input Reference Voltage Notes Clock Input High Voltage VKIH 1.25 V VDIF = 1.0V Clock Input Low Voltage VKIL 0.25 V VDIF = 1.0V Clock Input Common Mode Voltage VCM 0.75 V Clock Input Rise & Fall Time 2.0 V/ns Clock Input Reference Level CK/CK cross V Output Reference Level 0.75 V Output Load Conditions RQ = 250Ω See Figure 1 below Figure 1: AC Test Output Load (VDDQ = 1.5V) 0.75 V 50 Ω 16.7 Ω 50 Ω 5 pF DQ 16.7 Ω 0.75 V 50 Ω 16.7 Ω 50 Ω 5 pF 16Mb DDR1, rev 1.0 11 / 24 July 3, 2002 SONY® Preliminary CXK77Q36162GB Timing Diagram of Double Data Rate (DDR) Read-Write-Read Operations Synchronously Controlled via Deselect Operations (G = Low) Figure 2 Read Read Continue Read Deselect Deselect Write Continue Write Write Read Deselect Deselect 10x 1xx CK CK tKHKH tKHKL tKLKH tAVKH tKHAX SA A1 A2 A3 A4 A5 000 010 tBVKH tKHBX B(1:3) 010 11x 010 10x 1xx 000 11x G = VIL tKLQV tKHQV tKLQX tKHQX tKHQZ tKHQX1 tDVKH tKHDX Q11 Q12 Q13 Q14 Q21 Q22 tDVKL tKLDX Q51 Q52 D31 D32 D33 D34 D41 D42 DQ tCLQX tCHQX tCLQV tCHQV tKXCH tCHCL tKXCL tCLCH CQ CQ Note: In the diagram above, two Deselect operations are inserted between Read and Write operations to control the data bus transition from output to input. This depiction is for clarity purposes only. It is NOT a requirement. Depending on the application, one Deselect operation may be sufficient. 16Mb DDR1, rev 1.0 12 / 24 July 3, 2002 SONY® Preliminary CXK77Q36162GB Timing Diagram of Single Data Rate (SDR) Read-Write-Read Operations Synchronously Controlled via Deselect Operations (G = Low) Figure 3 Read Read Continue Read Deselect Deselect Write Continue Write Write Read Deselect Deselect 10x 1xx CK CK tKHKH tKHKL tKLKH tAVKH tKHAX SA A1 A2 A3 A4 A5 001 011 tBVKH tKHBX B(1:3) 011 11x 011 10x 1xx 001 11x G = VIL tKHQV tKHQZ tKHQX tKHQX1 tDVKH tKHDX DQ Q11 Q12 Q21 D31 D32 D41 Q51 tCHQX tKXCH tCHCL tKXCL tCLCH tCHQV CQ CQ Note: In the diagram above, two Deselect operations are inserted between Read and Write operations to control the data bus transition from output to input. This depiction is for clarity purposes only. It is NOT a requirement. Depending on the application, one Deselect operation may be sufficient. 16Mb DDR1, rev 1.0 13 / 24 July 3, 2002 SONY® Preliminary CXK77Q36162GB Timing Diagram of Double Data Rate (DDR) Read-Write-Read Operations Asynchronously Controlled via G and Dummy Read Operations Figure 4 Read Read Continue Read Dummy Read Dummy Read Write Continue Write Write Read Deselect Deselect 10x 1xx CK CK tKHKH tKHKL tKLKH tAVKH tKHAX SA A1 A2 A3 A4 A5 000 010 tBVKH tKHBX B(1:3) 010 11x 010 010 010 000 11x G tGHQZ tKLQV tKHQV tKLQX tKHQX tGLQV tKHQZ tGLQX tKHQX1 tDVKH tKHDX Q11 Q12 Q13 Q14 Q21 Q22 tDVKL tKLDX Q51 Q52 D31 D32 D33 D34 D41 D42 DQ tCLQX tCHQX tCLQV tCHQV tKXCH tCHCL tKXCL tCLCH CQ CQ Note: In the diagram above, two Dummy Read operations are inserted between Read and Write operations to control the data bus transition from output to input. This depiction is for clarity purposes only. It is NOT a requirement. Depending on the application, one Dummy Read operation may be sufficient. 16Mb DDR1, rev 1.0 14 / 24 July 3, 2002 SONY® Preliminary CXK77Q36162GB Timing Diagram of Single Data Rate (SDR) Read-Write-Read Operations Asynchronously Controlled via G and Dummy Read Operations Figure 5 Read Read Continue Read Dummy Read Dummy Read Write Continue Write Write Read Deselect Deselect 10x 1xx CK CK tKHKH tKHKL tKLKH tAVKH tKHAX SA A1 A2 A3 A4 A5 001 011 tBVKH tKHBX B(1:3) 011 11x 011 011 011 001 11x G tGHQZ tKHQV tGLQV tKHQZ tGLQX tKHQX tKHQX1 tDVKH tKHDX DQ Q11 Q12 Q21 D31 D32 D41 Q51 tCHQX tKXCH tCHCL tKXCL tCLCH tCHQV CQ CQ Note: In the diagram above, two Dummy Read operations are inserted between Read and Write operations to control the data bus transition from output to input. This depiction is for clarity purposes only. It is NOT a requirement. Depending on the application, one Dummy Read operation may be sufficient. 16Mb DDR1, rev 1.0 15 / 24 July 3, 2002 SONY® Preliminary CXK77Q36162GB •Test Mode Description These devices provide a JTAG Test Access Port (TAP) and Boundary Scan interface using a limited set of IEEE std. 1149.1 functions. This test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller, etc.), SRAMs, other components, and the printed circuit board. In conformance with a subset of IEEE std. 1149.1, this device contains a TAP Controller and four TAP Registers. The TAP Registers consist of one Instruction Register and three Data Registers (ID, Bypass, and Boundary Scan Registers). The TAP consists of the following four signals: TCK: TMS: TDI: TDO: Test Clock Test Mode Select Test Data In Test Data Out Induces (clocks) TAP Controller state transitions. Inputs commands to the TAP Controller. Sampled on the rising edge of TCK. Inputs data serially to the TAP Registers. Sampled on the rising edge of TCK. Outputs data serially from the TAP Registers. Driven from the falling edge of TCK. Disabling the TAP When JTAG is not used, TCK should be tied “low” to prevent clocking the SRAM. TMS and TDI should either be tied “high” through a pull-up resistor or left unconnected. TDO should be left unconnected. Note: Operation of the TAP does not interfere with normal SRAM operation except when the SAMPLE-Z instruction is selected. Consequently, TCK, TMS, and TDI can be controlled any number of ways without adversely affecting the functionality of the device. (VDD = 2.5V ± 5%, TA = 0 to 85°C) JTAG DC Recommended Operating Conditions Parameter Symbol Test Conditions Min Max Units JTAG Input High Voltage VTIH --- 1.4 VDD + 0.3 V JTAG Input Low Voltage VTIL --- -0.3 0.8 V JTAG Output High Voltage (CMOS) VTOH ITOH = -100uA VDD - 0.1 --- V JTAG Output Low Voltage (CMOS) VTOL ITOL = 100uA --- 0.1 V JTAG Output High Voltage (TTL) VTOH ITOH = -4.0mA VDD - 0.4 --- V JTAG Output Low Voltage (TTL) VTOL ITOL = 4.0mA --- 0.4 V VTIN = VSS to VDD -10 10 uA JTAG Input Leakage Current ITLI (VDD = 2.5V ± 5%, TA = 0 to 85°C) JTAG AC Test Conditions Parameter Symbol Conditions Units JTAG Input High Level VTIH 2.5 V JTAG Input Low Level VTIL 0.0 V JTAG Input Rise & Fall Time 1.0 V/ns JTAG Input Reference Level 1.25 V JTAG Output Reference Level 1.25 V JTAG Output Load Condition 16Mb DDR1, rev 1.0 Notes See Fig.1 (page 11) 16 / 24 July 3, 2002 SONY® Preliminary CXK77Q36162GB JTAG AC Electrical Characteristics Parameter Symbol Min Max TCK Cycle Time tTHTH 100 ns TCK High Pulse Width tTHTL 40 ns TCK Low Pulse Width tTLTH 40 ns TMS Setup Time tMVTH 10 ns TMS Hold TIme tTHMX 10 ns TDI Setup Time tDVTH 10 ns TDI Hold TIme tTHDX 10 ns TCK Low to TDO Valid tTLQV TCK Low to TDO Hold tTLQX 20 0 Unit ns ns JTAG Timing Diagram Figure 6 tTHTL tTLTH tTHTH TCK tMVTH tTHMX tDVTH tTHDX TMS TDI tTLQV tTLQX TDO 16Mb DDR1, rev 1.0 17 / 24 July 3, 2002 SONY® Preliminary CXK77Q36162GB TAP Controller The TAP Controller is a 16-state state machine that controls access to the various TAP Registers and executes the operations associated with each TAP Instruction. State transitions are controlled by TMS and occur on the rising edge of TCK. The TAP Controller enters the “Test-Logic Reset” state in one of two ways: 1. At power up. 2. When a logic “1” is applied to TMS for at least 5 consecutive rising edges of TCK. The TDI input receiver is sampled only when the TAP Controller is in either the “Shift-IR” state or the “Shift-DR” state. The TDO output driver is active only when the TAP Controller is in either the “Shift-IR” state or the “Shift-DR” state. TAP Controller State Diagram Figure 7 1 Test-Logic Reset 0 0 Run-Test / Idle 1 Select DR-Scan 1 Select IR-Scan 0 0 1 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR Exit1-IR 0 0 0 Pause-DR 1 0 Exit2-IR Update-DR 16Mb DDR1, rev 1.0 0 18 / 24 0 1 1 1 0 Pause-IR 1 Exit2-DR 0 Shift-IR 1 1 1 Update-IR 1 0 July 3, 2002 SONY® CXK77Q36162GB Preliminary TAP Registers TAP Registers are serial shift registers that capture serial input data (from TDI) on the rising edge of TCK, and drive serial output data (to TDO) on the subsequent falling edge of TCK. They are divided into two groups: “Instruction Registers” (IR), which are manipulated via the “IR” states in the TAP Controller, and “Data Registers” (DR), which are manipulated via the “DR” states in the TAP Controller. Instruction Register (IR - 3 bits) The Instruction Register stores the various TAP Instructions supported by these devices. It is loaded with the IDCODE instruction at power-up, and when the TAP Controller is in the “Test-Logic Reset” and “Capture-IR” states. It is inserted between TDI and TDO when the TAP Controller is in the “Shift-IR” state, at which time it can be loaded with a new instruction. However, newly loaded instructions are not executed until the TAP Controller has reached the “Update-IR” state. The Instruction Register is 3 bits wide, and is encoded as follows: Code (2:0) Instruction Description 000 BYPASS See code “111”. 001 IDCODE Loads a predefined device- and manufacturer-specific identification code into the ID Register when the TAP Controller is in the “Capture-DR” state, and inserts the ID Register between TDI and TDO when the TAP Controller is in the “Shift-DR” state. See the ID Register description for more information. 010 SAMPLE-Z Captures the individual logic states of all address, control, data, and clock signals in the Boundary Scan Register when the TAP Controller is in the “Capture-DR” state, and inserts the Boundary Scan Register between TDI and TDO when the TAP Controller is in the “ShiftDR” state. Also disables the data and clock output drivers. See the Boundary Scan Register description for more information. 011 BYPASS See code “111”. 100 SAMPLE Captures the individual logic states of all address, control, data, and clock signals in the Boundary Scan Register when the TAP Controller is in the “Capture-DR” state, and inserts the Boundary Scan Register between TDI and TDO when the TAP Controller is in the “ShiftDR” state. See the Boundary Scan Register description for more information. 101 PRIVATE Do not use. Reserved for manufacturer use only. 110 BYPASS See code “111”. 111 BYPASS Loads a logic “0” into the Bypass Register when the TAP Controller is in the “Capture-DR” state, and inserts the Bypass Register between TDI and TDO when the TAP Controller is in the “Shift-DR” state. See the Bypass Register description for more information. Bit 0 is the LSB of the Instruction Register, and Bit 2 is the MSB. When the Instruction Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out through TDO. Bypass Register (DR - 1 bit) The Bypass Register is one bit wide, and provides the minimum length serial path between TDI and TDO. It is loaded with a logic “0” when the BYPASS instruction has been loaded in the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted between TDI and TDO when the BYPASS instruction has been loaded into the Instruction Register and the TAP Controller is in the “Shift-DR” state. 16Mb DDR1, rev 1.0 19 / 24 July 3, 2002 SONY® Preliminary CXK77Q36162GB ID Register (DR - 32 bits) The ID Register is loaded with a predetermined device- and manufacturer-specific identification code when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted between TDI and TDO when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the “Shift-DR” state. The ID Register is 32 bits wide, and is encoded as follows: Revision Number (31:28) Part Number (27:12) Sony ID (11:1) Start Bit (0) xxxx 0000 0000 0100 1100 0000 1110 001 1 Bit 0 is the LSB of the ID Register, and Bit 31 is the MSB. When the ID Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out through TDO. Boundary Scan Register (DR - 68 bits) The Boundary Scan Register is equal in length to the number of active signal connections to the SRAM (excluding the TAP pins) plus a number of place holder locations reserved for density and/or functional upgrades. The Boundary Scan Register is loaded with the contents of the SRAM’s I/O ring when the SAMPLE or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted between TDI and TDO when the SAMPLE or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the “ShiftDR” state. The Boundary Scan Register contains the following bits: DQ 36 SA, SA1, SA0 19 CK, CK 2 CQ, CQ 4 B1, B2, B3 3 G 1 LBO, ZQ 2 Place Holder 1 Note: For deterministic results, all signals composing the SRAM’s I/O ring must meet setup and hold times with respect to TCK (same as TDI and TMS) when sampled. Note: CK and CK are connected to a differential input receiver that generates a single-ended input clock signal to the device. Therefore, in order to capture specific values for these signals in the Boundary Scan Register, these signals must be at opposite logic levels when sampled. Note: When an external resistor RQ is connected between the ZQ pin and VSS, the value of the ZQ signal captured in the Boundary Scan Register is non-deterministic. Note: Place Holders are required for some NC pins to allow for future density and/or functional upgrades. They are connected to V DD internally, regardless of pin connection externally. 16Mb DDR1, rev 1.0 20 / 24 July 3, 2002 SONY® Preliminary CXK77Q36162GB Boundary Scan Register Bit Order Assignments The table below depicts the order in which bits are arranged in the Boundary Scan Register. Bit 1 is the LSB and bit 68 is the MSB. When the Boundary Scan Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out through TDO. Bit Signal Pad Bit Signal Pad 1 SA1 5R 35 SA 6A 2 SA0 5T 36 SA 4A 3 SA 6R 37 SA 4C 4 SA 7T 38 SA 3A 5 SA 7P 39 SA 3B 6 DQ 8T 40 SA 3C 7 DQ 9T 41 SA 3D 8 DQ 8P 42 DQ 2B 9 DQ 7M 43 DQ 1B 10 DQ 9P 44 DQ 2D 11 CQ 8M 45 DQ 3F 12 DQ 9M 46 DQ 1D 13 DQ 7K 47 CQ 2F 14 DQ 8K 48 DQ 1F 15 DQ 9K 49 DQ 3H 6L 50 DQ 2H 16 NC (1) 17 CK 5H 51 DQ 1H 18 CK 5G 52 ZQ 5A 19 G 5C 53 B1 5B 20 DQ 9H 54 B2 5K 21 DQ 8H 55 B3 5L 22 DQ 7H 56 LBO 4L 22 DQ 9F 57 DQ 1K 24 CQ 8F 58 DQ 2K 25 DQ 9D 59 DQ 3K 26 DQ 7F 60 DQ 1M 27 DQ 8D 61 CQ 2M 28 DQ 9B 62 DQ 1P 29 DQ 8B 63 DQ 3M 30 SA 7D 64 DQ 2P 31 SA 7C 65 DQ 1T 32 SA 7B 66 DQ 2T 33 SA 7A 67 SA 3T 34 SA 6C 68 SA 4R Note 1: NC pin at pad location 6L is connected to VDD internally, regardless of pin connection externally. 16Mb DDR1, rev 1.0 21 / 24 July 3, 2002 SONY® Preliminary CXK77Q36162GB •Ordering Information VDD I/O Type Size Speed (Cycle Time / Access Time) CXK77Q36162GB-25 2.5V HSTL 512K x 36 2.5ns / 1.8ns CXK77Q36162GB-27 2.5V HSTL 512K x 36 2.7ns / 1.9ns CXK77Q36162GB-3 2.5V HSTL 512K x 36 3.0ns / 2.0ns Part Number Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. 16Mb DDR1, rev 1.0 22 / 24 July 3, 2002 SONY® Preliminary CXK77Q36162GB 153 Pin BGA Package Dimensions 14.0 2.5 MAX 0.15 S A 0.20 // 0.35 S 0.15 S B 22.0 19.0 0. 7 A 0.15 S B C 4- 4C 10.16 0.6 ± 0.1 x4 0 1. U T R P N M L K J H G F E D C B A 20.32 13.0 1 2 3 4 5 6 7 8 9 S 1.27 153 - φ0.75 ± 0.15 φ0.15 M S AB PRELIMINARY PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE BGA-153P-021 BORAD TREATMENT COPPER-CLAD LAMINATE EIAJ CODE BGA153-P-1422 LEAD MATERIAL SOLDER PACKAGE MASS 1.5g JEDEC CODE 16Mb DDR1, rev 1.0 23 / 24 July 3, 2002 SONY® CXK77Q36162GB Preliminary •Revision History Rev. # Rev. Date Description of Modifications rev 0.0 07/23/01 Initial Version. rev 0.1 08/20/01 1. Modified DC Electrical Characteristics (p. 9). Added x36 IDD (max) spec Added x18 IDD (max) spec rev 1.0 07/03/02 16Mb DDR1, rev 1.0 750mA @ 275 MHz 700mA @ 275 MHz 1. Removed x18 support. 2. Modified DC Recommended Operating Conditions (p. 7). 1.9V to 1.6V VDDQ (max) 1.0V to 0.85V VREF, VCM (max) 3. Modified DC Electrical Characteristics (p. 8). RQ/5 ± 10% to RQ/5 ± 15% ROUT 4. Modified AC Electrical Characteristics (p. 9). 1.6ns to 1.8ns -25 tKXCH, tKXCL 1.7ns to 1.9ns -27 tKXCH, tKXCL 1.8ns to 2.0ns -3 tKXCH, tKXCL 0.25ns to 0.3ns tDVKH, tDVKL, tKHDX, tKLDX 5. Removed 1.8V VDDQ AC Test Conditions. 24 / 24 July 3, 2002