16/20/24Bit 44.1/32/48kHz Sigma-Delta Stereo DAC
16/20/24Bit 32/44.1/48kHz Sigma-Delta Stereo DAC
General Description
DAC0415X
DAC0415X
Features
This product is Sigma-Delta Digital-To-Analog
Converter for High grade Digital Audio Applications.
-16/20/24bit Sigma-Delta Digital-to-Analog Converter
-Sampling Frequency Rate 32/44.1/48KHz
-Input Rate 1Fs or 2Fs by Normal Mode/Double
The product contains Serial-to-Parallel Interface
Converter and Compensation Filter, Digital Volume
Attenuator by the Mode Interface, De-Emphasis
Filter, FIR filter, Sinc Filter, Digital Sigma-Delta
Mode Selection
-On-Chip Compensation Filter
-On-Chip 4 times Oversampling Digital Filter
Modulator, Analog Postfilter, AIF (Anti-Image-Filter).
The normal input and output channels provides
95dB SNR (Signal to Noise Ratio) over in band
-On-Chip Analog Postfilter
-Filtered Line-Level Outputs, Linear Phase Filtering
-On-Chip Voltage Reference
(20kHz : Sampling Rate = 44.1KHz).
The
product
employs
the
1bit
-Low Clock Jitter Sensitivity
-96dB SNR
-L/R Independent Digital Soft Attenuation
4th-order
Sigma-Delta architecture with 16bit resolution, over
sampling of 64X. And Analog Postfilter with low
clock sensitivity and Linear phase, filters the
Shaping-Nosie and outputs Analog voltage with
-On-Chip De-Emphasis Filter (32/44.1/48KHz)
-Zero Input Detection Mute
-Soft Mute Control
high resolution. An on-chip reference voltage is
included to allow single supply operations.
-Mono/Stereo Setting
-Single 1.8V / 3.3V(Digital/Analog) Power Supply
Applications
CD Player, CD-ROM, MP3 Player, Video-CD,
Mini-Disk, DVD etc
Block Diagram
AVDD18D AVSS18D
MSCK
BCK
LRCK
SDATA
ZDENH
S/P
Converter
&
Attenuator
Compensation
Filter
&
De-emphsis
&
FIR Filter
Sinc Filter
&
Sigma-Delta
Modulator
M D I I MZ
L N I F U D
D
SS T E
F
E N
S
L L
0
RP I
S D D
T L N
B
U
M
S
D
I
A
G
S
E
R
R
O
R
B
T
S
E
L
O
F
S
6
4
O
D
S
L
O
D
S
R
I
F
S
6
4
I
A
D
S
L
I
A
D
S
R
I
R
E
F
B
*
(I)* : Input
(O)* : Output
(B)* : Bidirection
AOUTL
AOUTR
VCOMML(I)*
VCOMCL(I)*
VCOML(I)*
VREFML(I)*
VREFPL(I)*
VHALF(O)*
VREFIN(I)*
VREF(O)*
VREFPR(I)*
VREFMR(I)*
VCOMR(I)*
VCOMCR(I)*
VCOMMR(I)*
>
3
:
0
B
I
S
T
O
N
P
Anti-Imaging
Filter
Voltage
Reference
( )
M
D
A
F
S
1
<
M
C
K
D
E
M
DAC
&
Analog
Postfilter
Test Mode Interface
Mode Interface & Timing Control
M
O
D
E
AVDD33A AVSS33A
(Dec 2001) This data sheet is a preliminary version. No responsibility is assumed by SEC for its
use nor for any infringements of patents or other rights of third parties that may result from its use. The
content of this data sheet is subject to change without any notice.
Ver 4.0
SEC ASIC
1/17
ANALOG
16/20/24Bit 44.1/32/48kHz Sigma-Delta Stereo DAC
DAC0415X
Embedded Core Block Diagram
External
Inputs
4
External
M
U
X
4
4
A
V
S
S
1
8
D
MSCK
BCK
LRCK
SDATA
MUX_SEL
Audio Processor
(DSP)
15
MODE
MCKDEM
MDAFS1
MLDFS0
DN
IIS
IFS
MUTEL
ZDENL
RSTB
PDL
IDNUM<3:0>
1
ZDENH
AVSS18D
5
A
V
D
D
1
8
D
A
V
D
D
3
3
A
AOUTL
A
V
S
S
3
3
A
AOUTR
VHALF
VREF
VREFIN This pin must be
connected to VHALF PAD
VCOML
VCOMCL
VCOMML
VREFPL Each ports must be
VCOMR connected to VREF PAD
VCOMCR
VCOMMR
VREFPR
dac0415x
VREFML
VREFMR
Each ports must be
connected to AVSS33A PAD
IREF
BISTONP
TSEL
IFS64
IADSL
IADSR
SDIAG
SERRORB
OFS64
ODSL
ODSR
These are test pins for internal blocks of the core.
So you don't need the internal test mode.
Make the test control pins disable ('L') state and
Output and bidirectional pins leave floating.
Embedded Core User Guide
- Digital serial data input and clock input refer to digital input format.
- Digital control pins inform refer to pin description.
- Mode I/F pin inform refer to Mode Interface. IDNUM<3:0> are ID number setting pins for Mode
Interface.
- External application of analog output pins refer to application circuit.
- If you want to test only embedded analog core block (Sigma-Delta DAC), you can do it just adding the
4 pins to supply digital serial input data (MSCK, BCK, LRCK, SDATA) and MUX block.
- Analog power(AVDD33A,AVSS33A) and digital power(AVDD18D,AVSS18D) should be separated.
- Bulk Power pin should be connected to analog ground(AVSS33A).
- Two pads should be dedicated to analog power(AVDD33A, AVSS33A)
- If you need not use test mode for the testability of internal core block, you make internal core block
test pins disable state. (Test Input pins are 'L' state and Test output, bi-direction pins leave floating)
SEC ASIC
2/17
ANALOG
16/20/24Bit 44.1/32/48kHz Sigma-Delta Stereo DAC
DAC0415X
Core Pin Description
SYMBOL
I/O TYPE
I/O PAD
DESCRIPTION
POWER SUPPLY PINS
I/O TYPE ABBR.
AVDD18D
DP
vdd 1t_ abb
Digital Suppl y
AVS S18D
DG
vss1t_ab b
Digital Groun d
AVDD33A
AP
vdd 3t_ abb
Ana log Supp ly
AVS S33A
AG
vss3t_ab b
Ana log Grou nd
MSCK
DI
picc_a bb
Maste r Clock Inpu t.
BCK
DI
picc_a bb
Bit Clo ck Inp ut.
LRCK
DI
picc_a bb
Sampl e Rate Clock In put. (Fs or 2Fs)
SDATA
DI
picc_a bb
Ser ial Dig ital Input
ZDENH
DO
pob2_ abb
Zero Data Detectio n Output
When Input Da ta is continu ously ze ro for more than 40 96*sampli ng time(fs), ZDENH
becomes to H
MODE
DI
picc_a bb
SoftWa re / HardWare Control Sele ct ("H" / "L ")
MCKDEM
(MCLK / DEEM)
DI
picc_a bb
Mode Interfa ce Clock Input / De-Empha sis On/Off. "H" is ena bled. "L" is d isa bled.
(When MODE pin is "H", MCLK is active . When MODE pin is "L ", DEEM is active)
MDAFS1
(MDATA / SFS1)
DI
picc_a bb
Mode Interfa ce Command Data Inpu t / De-Emph asi s Freque ncy Selecti on1
(When MODE pin is "H", MDATA is active. Wh en MO DE pi n is "L", SFS1 is a ctive)
MLDFS0
(MLD / SFS0)
DI
picc_a bb
Mode Interfa ce Command load Inpu t(when low,load) / De-E mp hasis Frequ ency
Sel ection0
(When MODE pin is "H", MLD is active. Wh en MODE p in is "L", SFS0 is a ctive)
DN
DI
picc_a bb
Input Rate Sele ct. High is Dou ble(2Fs) Mo de, Lo w is Normal( Fs) Mode.
(When MODE pin is "L" (Hardware mode ), this pin is active)
IIS
DI
picc_a bb
IIS / S tan dard Input For ma t Selection
(When MODE pin is "L" (Hardware mode ), this pin is active)
IFS
DI
picc_a bb
Input For ma t Sele ction
(When MODE pin is "L" (Hardware mode ), this pin is active)
MUTEL
DI
picc_a bb
Ana log Output Mu te. "L" en abled
(When MODE pin is "L" (Hardware mode ), this pin is active)
ZDENL
DI
picc_a bb
Zero Input Detecti on Enable . "L" i s enab led. "H" i s disabled
(When MODE pin is "L" (Hardware mode ), this pin is active)
RSTB
DI
picc_a bb
Reset Input. "L" Enab led
PDL
DI
picc_a bb
Power Down.
IDNUM<3:0>
DI
picc_a bb
Mode Interfa ce ID Number Se tting In put
AO UTL
AO
phoa_ abb
Ana log Output for L-CH
AO UTR
AO
phoa_ abb
Ana log Output for R-CH
VHALF
AO
phoa_ abb
Reference Voltage Ou tpu t for Bypa ss
VREF
AO
phoa_ abb
Reference Voltage Ou tpu t for Bypa ss
- AI : Analog Input
DIGITAL PINS
-
DI : Digital Input
AO : Analog Output
DO : Digital Output
AB : Analog Bidirectional
DB : Digital Bidirectional
AP : Analog Power
AG : Analog Ground
DP : Digital Power
DG : Digital Ground
"L" en abled
ANALOG PINS
VREFIN
Each por ts must b e con nected to VHALF P AD
VCOML
VCOMCL
VCOMML
VREFPL
AI
Each por ts must b e con nected to VREF PA D
VCOMR
VCOMCR
VCOMMR
VREFPR
SEC ASIC
3/17
ANALOG
16/20/24Bit 44.1/32/48kHz Sigma-Delta Stereo DAC
DAC0415X
VREFML
Each por ts must b e con nected to AVSS 33A PAD
VREFMR
CORE INTERNAL BLOCK TEST PINS
BISTONP
DI
picc_a bb
Memory B ist Test Mod e. "H" ena bled
SDIAG
DO
pob2_ abb
Test Output pin fo r E mb edded memory B IST (BISTONP="H")
SERRORB
DO
pob2_ abb
Test Output Pin fo r E mb edded memory B IST (BISTONP="H")
TSEL
DI
picc_a bb
Test pin for Analog P ostfilte r Inpu t Selection
IFS 64
DI
picc_a bb
64X S ampling Clock Input for Ana log Postfilter (When TSEL=H)
IADSL
DI
picc_a bb
Inputs for Analo g Postfilter of L-CH ( Wh en TS EL=H)
IADSR
DI
picc_a bb
Inputs for Analo g Postfilter of R-CH (When TSEL=H)
OFS64
DO
pob2_ abb
64X S ampling Clock output for Digital si gma-delta Modulator
ODSL
DO
pob2_ abb
L-CH Output for Digital sigma- delta Mod ulator.
ODSR
DO
pob2_ abb
R-CH Ou tpu t fo r Digital sigma-del ta Modula tor .
IRE F
AB
phoa_ abb
Test Pin for Analog S upply Curr ent
SEC ASIC
4/17
ANALOG
16/20/24Bit 44.1/32/48kHz Sigma-Delta Stereo DAC
DAC0415X
Core Configurtion
AOUTL
AOUTR
MSCK
BCK
LRCK
SDATA
VHALF
VREF
VREFIN
MODE
MCKDEM
MDAFS1
MLDFS0
DN
IIS
IFS
MUTEL
ZDENL
RSTB
PDL
IDNUM<3:0>
VCOML
VCOMCL
VCOMML
VREFPL
VCOMR
VCOMCR
VCOMMR
VREFPR
dac0415x
Used Power:
(AVDD18D AVSS18D AVDD33A AVSS33A)
VREFML
VREFMR
BISTONP
TSEL
IFS64
IADSL
IADSR
ZDENH
IREF
SDIAG
SERRORB
OFS64
ODSL
ODSR
Absolute Maximum Ratings
CHARACTERISTICS
SYMBOL
DC Supply Voltage
V DD
Storage Temperature Range
VALUES
UNITS
Digital Supply Voltage
2.7
Analog Supply Voltage
3.8
Tstg
V
V
℃
-65 to +150
Recommended Operating Conditions
CHRACTERISTICS
Supply Voltage
Operating Temp.
SYMBOL
MIN
TYP
MAX
UNITS
AVDD18D
AVDD18A
1.65
3.0
1.8
3.3
1.95
3.6
V
Topr
0
25
70
℃
Electrical Characteristics
(AVDD18D=1.8v,AVDD33A=3.3V, Temp=25℃ , Fs=44.1kHz, Signal Frequency=20~20kHz, Cload of AoutL, AoutR=10pF)
PARAMETER
MIN
TYP
RESOLUTION
MAX
UNITS
24
bits
96
dB
DYNAMIC PERFORMANCE (16Bit Data)
SNR
< 1>
THD
<2>
92
< 2>
SND(THD+Noise)
< 3>
Dynamic Range
Crosstalk
<1>
SEC ASIC
0.01
0.02
%
-80.0
-74.0
dB
72
76
dB
85
90
dB
85
90
dB
5/17
ANALOG
16/20/24Bit 44.1/32/48kHz Sigma-Delta Stereo DAC
DAC0415X
ANALOG OUTPUT
Reference Voltage Ouput
0.5 x AVDD33A
± 0.1
Frequency Responce
Voltage Range
V
± 0.5
0.70 x AVDD33A
Load Impedance
dB
Vpp
Ω
10K
DIGITAL FILTER
±0.0072
dB
Stop Band Attenuation
62.7
dB
Pass Band
0.45
Fs
Pass Band Ripple
POWER SUPPLY
Analog Current
5.0
7.0
mA
Digital Current
1.5
1.8
mA
Power Dissipation
19.2
26.34
mW
20
40
uA
Power Down Current
<1> 1kHz 0dB Sinewave Input, EIAJ
<2> 1kHz 0dB Sinewave Input, Not EIAJ
<3> 1kHz -60dB Sinewve Input, and then measured data + 60dB
AC Timing Characteristics
(AVDD18D=1.8V, AVSS18D=0V, Fs=48KHz, MSCK=768*FS,
24Bit Input Format, Normal Operation Mode, Software Mode (MODE="High"), Temp=25℃ )
CHRACTERISTICS
SYMBOL
MIN
TYP
MAX
UNIT
Fmsck
-
768*Fs
-
Hz
BCK Frequency
Fbck
-
48*Fs
-
Hz
LRCK Frequency
Flrck
-
1*Fs
-
Hz
MSCK Rising and LRCK Edge Dealay
Tmld
10
-
-
ns
MSCK Risng and LRCK Edge Setup Time
Tmlst
10
-
-
ns
BCK Rising and LRCK Edge Dealay
Tbld
10
-
-
ns
BCK Risng and LRCK Edge Setup Time
Tblst
10
-
-
ns
SDATA and BCK Rising Setup Time
Tsbst
10
-
-
ns
BCK Ring and SDATA Hold Time
Tbsht
10
-
-
ns
MCKDEM Frequency
Fmck
-
-
128*Fs
Hz
MLDFS0 Frequency
Fmld
-
-
1*Fs
Hz
MLDFS0 Load Time
Tload
550
MSCK Frequency
SEC ASIC
6/17
ns
ANALOG
16/20/24Bit 44.1/32/48kHz Sigma-Delta Stereo DAC
MSCK
DAC0415X
0.5 AVDD18D
1/Fmsck
BCK
0.5 AVDD18D
1/Fbck
LRCK
0.5 AVDD18D
1/Flrck
LRCK
0.5 AVDD18D
Tmld
Tmlst
MSCK
0.5 AVDD18D
LRCK
0.5 AVDD18D
Tbld
Tblst
BCK
0.5 AVDD18D
Tsbst
SDATA
Tbsht
0.5 AVDD18D
0.5 AVDD18D
MCKDEM
1/Fmck
Tload
MLDFS0
0.5 AVDD18D
1/Fmld
Fig 1. Timing Chart
SEC ASIC
7/17
ANALOG
16/20/24Bit 44.1/32/48kHz Sigma-Delta Stereo DAC
DAC0415X
System Clock Frequency
This Core has a system clock detection circuit which automatically senses if the system clock is operating
at 256Fs ~ 768Fs. The system clock for this core must be either 256Fs, 384Fs, 512Fs or 768Fs, where
Fs is the audio sampling frequency. The system clock should be synchronized with LRCK clock. LRCK
operates at the sampling frequency Fs.
System Clock Frequency
SAMPLING RATE FREQUENCY
(Fs:LRCK)
256fs
384fs
512Fs
768Fs
32KHz
8.1920
12.2880
16.3840
24.5760
MHz
44.1KHz
11.2896
16.9344
22.5792
33.8688
MHz
48KHz
12.2880
18.4320
24.5760
36.8640
MHz
UNIT
Input Clock and Serial Input Data Inform
DN pin is normal and double mode selection control pin. Refer to the following Table 1 for input clock
inform.
Normal Mode (DN='Low')
Double Mode (DN='High')
LRCK
44.1kHz(=1*Fs)
88.2kHz(=2*Fs)
MSCK(=384Fs)
16.9344MHz(=384*FS)
16.9344MHz(=384*Fs)
BCK
1.4112MHz(=32*Fs)
2.8224MHz(=64*Fs)
Table 1. Input Clock Informs ( Fs=44.1KHz, MSCk=384*Fs,16Bit Input Format Case )
LRCK
R-CH DATA
L-CH DATA
BCK
(1) 16Bit Right Justified
SDATA
…
14 15 16
1 2 3
MSB
…
…
14 15 16
1 2 3
LSB
…
MSB
14 15 16
…
LSB
(2) 20Bit Right Justified
SDATA
…
18 19 20
1 2 3
MSB
…
18 19 20
1 2 3
LSB
…
MSB
18 19 20
…
LSB
(3) 24Bit Right Justified
SDATA
22 23 24
…
1 2 3
MSB
…
22 23 24
1 2 3
LSB
MSB
…
22 23 24
…
LSB
(4) 24Bit Left Justified
SDATA
…
1 2 3
MSB
SEC ASIC
22 23 24
…
LSB
1
2 3
MSB
8/17
…
22 23 24
…
1 2
LSB
ANALOG
16/20/24Bit 44.1/32/48kHz Sigma-Delta Stereo DAC
LRCK
DAC0415X
R-CH DATA
L-CH DATA
BCK
(5) IIS 16Bit
SDATA
…
… 14 15 16
1 2 3
MSB
…
1
LSB
2 3
MSB
…
…
14 15 16
1 2
LSB
(6) IIS 24Bit
…
…
1 2 3
MSB
22 23 24 …
1
LSB
2 3
…
MSB
22 23 24 …
1 2
LSB
Fig 2. Digital Input Data Format
Digital audio data is interfaced to LRCK, SDATA and BCK Pins. DAC0415X can accept both standard,
IIS, and left justified data formats. Figure 2 illustrates acceptable input data formats.
Mode Interface & Function Inform
This core can do several built-in functions including digital attenuation, digital de-emphasis, double/normal
mode selection, input data format selection, soft mute, zero input detection, and others. These functions
can be operated in two different modes, Software mode or Hardware mode. Software Mode is controlled
by MCKDEM(MCLK), MDAFS1(MDATA), MLDFS0(MLD) signals from the Mode Interface. Hardware Mode
is operated by MCKDEM(DEEM), MDAFS1(SFS1), MLDFS0(SFS0),DN, IIS, IFS, MUTEL, ZDENL pins.
This basic operation mode as software or hardware can be selected by MODE Pin as Table shown in
Table 2.
MODE = "High"
Softw are Mode
MODE = "Low"
Hardw are Mode
Table 2. Mode Control
All of the functions shown are selectable within the software mode, but only de-emphasis control, double
mode, input data format, soft mute and zero input detection may be selected when using it in the
hardware mode.
- Hardware Mode (MODE = "Low")
1) De-Emphasis Control
De-Emphasis control can be selected by DEEM, SFS1 and SFS0 pins.
DEEM
SFS1
SFS0
De-Emphasis
L
X
X
De-Emphasis OFF
H
H
H
H
L
L
H
H
L
H
L
H
De-Emphasis ON (44.1KHz)
De-Emphasis ON (48KHz)
De-Emphasis ON (32KHz)
De-Emphasis ON (44.1KHz)
Table 3. De-Emphasis Control
SEC ASIC
9/17
ANALOG
16/20/24Bit 44.1/32/48kHz Sigma-Delta Stereo DAC
DAC0415X
2) Input Data Format Control
Input data format can be selected by IIS and IFS pins.
IIS
IFS
Data Format
L
L
H
H
L
H
L
H
16Bit Right Justified
20Bit Right Justified
IIS 16Bit
IIS 24Bit
Table 4. Input Data Format Control
3) Double / Normal Mode Control
DN pin is normal and double mode selection control pin.
DN
Function
"Low"
Normal Mode
" High"
Double Mode
Table 5. Double / Normal Mode Control
4) Soft Mute Control
Soft Mute control can be selected by MUTEL pin. Figure3 illustrates Soft Mute operation.
MUTEL
Function
"Low"
Soft mute On
" High:
Soft mute Off
Table 6. Soft Mute Control
Soft mute OFF
Soft mute ON
Soft mute OFF
0 dB
- ∞ dB
1024*Fs Time
1024*Fs Time
Fig 3. Soft Mute Timing Chart
5) Zero Input Detecton Enable Control
Zero Input Detection Enable control can be selected by ZDENL pin. If the input data has the
condition where the lower 4bits of the input data are DC and the remaining upper bits are all "0" or
all "1" has continued 8192 cycles of LRCK, Zero input is detected. Zero Input Detection is performed
independently for the left and right channels. The Analog Postfilter output will be immediately forced
to VREF.
ZDENL
Function
"Low"
Zero Input Detection Enable
" High"
Zero Input Detection not Enable
Table 7. Zero Input Detection Enable Control
SEC ASIC
10/17
ANALOG
16/20/24Bit 44.1/32/48kHz Sigma-Delta Stereo DAC
DAC0415X
- Software Mode (MODE = "High")
Software Mode functions are controlled by Mode Interface. When the 16-bit serial data is applied to the
MCKDEM, MDAFS1,MLDFS0 pins in the form of Fig4. Software Mode is accomplished. The higher 4bits
(MSB First Format-Bin) should be Mode Interface 4bit ID number, the middle 4bits are Address, and
according to the lower 8 bits(MSB First Format-Bin) can be adjusted to Data. When RSTB is low state,
Software Mode becomes default values. Digital Soft Attenuation (ATTL / ATTR) of Software Mode is
attenuated by the same degree that Soft Mute Control does. In case of no Software Mode function
needed, MDAFS1 should be "L", MCKDEM and MLDFS0 should be "H".
MCKDEM
LSB
MSB
MDAFS1
Don't
Care
MSB
LSB
MSB
LSB
ID<3 > ID<2> ID<1> ID<0> A<3 > A<2 > A <1> A<0 > D<7>
D<6> D<5> D<4> D<3>
Don't
Care
D<2> D<1> D<0>
MLDFS0
Over 550ns needed
Fig 4. Mode Interface Timing Chart
This section contains information concerning the programmable control registers. Table 8 provides the
default reset bar values for each index, and a bit map for each register.
ID NUMBER
ADDRESS
Mnemonic
D<7:0>
DEFAULT
VALUE
7
6
5
4
3
2
1
0
ID<3:0>
A<3:0>
IDNUM<3:0>
0000b
CMDA
00Hex
RES
ZEL
LRP
IIS
IF1
IF0
MON
MLR
IDNUM<3:0>
0001b
CMDB
00Hex
RES
RES
DNS
AIC
MUL
DEM
FS1
FS0
IDNUM<3:0>
0010b
ATTL
00Hex
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
IDNUM<3:0>
0011b
ATTR
00Hex
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
Table 8. Mode Interface Register Map
SEC ASIC
11/17
ANALOG
16/20/24Bit 44.1/32/48kHz Sigma-Delta Stereo DAC
DAC0415X
Control Register A
Address
Mnem onic
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0000b
CMDA
RES
ZEL
LRP
IIS
IF1
IF0
MON
MLR
(* : Default value)
RES
Reserved.
ZEL
Zero Input Detection Enable Bar.
LRP
0
Zero input detection enable*.
1
Zero input detection disable.
Polarity of LRCK Select.
LRP is used to select the polarity of LRCK. When bit 5 is "Low", left channel data is
assumed when LRCK is in a "HIGH" phase and right channel data is assumed when
LRCK is in a "LOW" phase. When bit 5 is "HIGH", the polarity assumption is reversed.
IIS
0
L-Channel
R-Channel
1
L-Channel
R-Channel
*
Audio Data Format Select.
IIS is used to control the input data format. A "LOW" on bit 4 sets the format to
(MSB-first, right-justified format) and a "HIGH" sets the format to IIS.
IF1,IF0
MON
MLR
0
MSB-first, right-justified format.*
1
IIS format.
Input Format Select.
IIS
IF1
IF0
Input Data Format
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16-Bit Standard (Right-Justified)*
20-Bit Standard (Right-Justified)
24-Bit Standard (Right-Justified)
24-Bit Left-Justified (MSB First)
16-Bit IIs
24-Bit IIS
Reserved
Reserved
Mono / Stereo Output Selection.
0
Stereo Output.*
1
Mono Output.
Mono Channel Selection.
When MON is "HIGH", this bit is enabled.
0
R-Channel Mono Output.
1
L-Channel Mono Output*.
SEC ASIC
12/17
ANALOG
16/20/24Bit 44.1/32/48kHz Sigma-Delta Stereo DAC
DAC0415X
Control Register B
Address
Mnem onic
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0001b
CMDB
RES
RES
DNS
AIC
MUL
DEM
FS1
FS0
(* : Default value)
RES
Reserved.
RES
Reserved.
DNS
Double / Normal Mode Selection.
AIC
0
Normal Mode Operation.*
1
Double Mode Operation.
Individual / Common Attenuation Level Control.
AIC is used as an attenuation control. When this bit is "LOW", the attenuation data on
Attenuation Register L is used for both channels, and data in Attenuation Register R is
ignored. When this bit is set "HIGH", each channel has separate attenuation data.
MUL
DEM
0
Common Attenuation Level Control*.
1
Individual Attenuation Level Control.
Soft Mute control.
0
Soft Mute ON.
1
Soft Mute OFF*.
De-Emphasis Enable Control.
0
De-Emphasis OFF*.
1
De-Emphasis ON.
FS1, FS0 De-Emphasis Sampling Frequency Selection
DEM
FS1
FS0
De-Emphasis
0
X
X
De-Emphasis OFF
1
1
1
1
0
0
1
1
0
1
0
1
De-Emphasis ON (44.1KHz)*
De-Emphasis ON (48KHz)
De-Emphasis ON (32KHz)
De-Emphasis ON (44.1KHz)
SEC ASIC
13/17
ANALOG
16/20/24Bit 44.1/32/48kHz Sigma-Delta Stereo DAC
DAC0415X
Attenuation Register L
Address
Mnem onic
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0010b
ATTL
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
(* : Default value)
AL7- AL0 L-Channel Attenuation Level Control.
Attenuation Register L is used to left channel attenuation. Bits7-0 (AL7 - AL0) are
used determine the attenuation level. The level of attenuation is given by
Attenuation Level = -20 * log1 0 (AL7 - AL0) dB
AL7
SEC ASIC
-
AL0
Attenuation Level
00
01
02
03
04
Hex
Hex
Hex
Hex
Hex
…
0 dB*
-0.068 dB
-0.102 dB
-0.137 dB
-0.171 dB
…
FC
FD
FE
FF
Hex
Hex
Hex
Hex
-38.622 dB
42.144 dB
-48.165 dB
- ∞ dB
14/17
ANALOG
16/20/24Bit 44.1/32/48kHz Sigma-Delta Stereo DAC
DAC0415X
Attenuation Register R
Address
Mnem onic
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0011b
ATTR
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
(* : Default value)
AR7- AR0 R-Channel Attenuation Level Control.
Attenuation Register L is used to left channel attenuation. Bits7-0 (AR7 - AR0) are
used determine the attenuation level. The level of attenuation is given by
Attenuation Level = -20 * log1 0 (AR7 - AR0) dB
AR7
SEC ASIC
-
AR0
Attenuation Level
00
01
02
03
04
Hex
Hex
Hex
Hex
Hex
…
0 dB*
-0.068 dB
-0.102 dB
-0.137 dB
-0.171 dB
…
FC
FD
FE
FF
Hex
Hex
Hex
Hex
-38.622 dB
42.144 dB
-48.165 dB
- ∞ dB
15/17
ANALOG
16/20/24Bit 44.1/32/48kHz Sigma-Delta Stereo DAC
DAC0415X
Functional Description
MSCK
BCK
LRCK
SDATA
MODE
MCKDEM
MDAFS1
MLDFS0
DN
IIS
IFS
MUTEL
ZDENL
RSTB
PDL
IDNUM<3:0>
S/P
Converter
&
Attenuator
Mode Interface
&
Timing Control
1Fs/2Fs
24bits
Compensation
Filter
&
De-emphsis
&
FIR Filter
4Fs/8Fs
24bits
Sinc Filter
&
Sigma-Delta
Modulator
64Fs
1bit
AOUTL
DAC
&
Analog
Postfilter
Anti-Imaging
Filter
AOUTR
Fig 5. Funtional Block Diagram
Fig 5. is the 1bit 4th order sigma-delta DAC block diagram. S/P Converter converts serial 16/20/24bit
input data to parallel 16/20/24bit data. Digital input data is attenuated by MODE interface pin control.
Compensation Filter compensates gain droop in Passband by Sinc Filter and Sigma-Dellta Modulator
Signal Transfer Function. De-emphasis Block de-emphasizes pre-emphasised input data to emphasize high
frequency in audible band. FIR Filter performs 4X interpolation. And it outputs 4Fs(DN="Low") rate data or
8Fs(DN="High") rate data by variable input data rate. It also removes the images of the input signal that
are present at multiples of the input sample frequency. And Sinc filter makes the constant 64Fs rate data
by 16 times or 8 times up-sampling FIR Filter output data according to DN(Double/Normal Mode) Pin
Selection. This operation introduces a sinc function response on the resulting frequency spectrum, which
greatly attenuates the energy of images at the multiples of 4Fs(or 8Fs).
Digital sigma-delta modulator of bit-stream type has the IFL (Inverse-Follower-Leader) topology, and it
performs a noise-shaping function. The modulator shapes the quantization noise by suppressing its
in-band component and pushes the noise energy of outside the band-of-interest without deteriorating the
audio input signal. The 64 times oversampled 1-bit PDM outputs from the modulator drives a analog
postfilter.
The analog postfilter comprises SC-postfilter, anti-imaging filter. The SC-postfilter removes the
quantization noise shaped to out-of-band by digital sigma-delta modulator. This analog filter has the good
clock jitter characteristic and very linear characteristic. And following the CTF(continuous time filter)
removes the sampling images and makes the high resolution analog output.
SEC ASIC
16/17
ANALOG
16/20/24Bit 44.1/32/48kHz Sigma-Delta Stereo DAC
DAC0415X
Application Circuit
AVDD33A
+
0.1uF
+
10uF
VHALF
AVSS33A
+
0.1uF
+
10uF
0.1uF
+
10uF
AVSS33A
VREF
AVDD18D
+
Analog Ground Plane
AVSS33A
AVSS18D
Digital Ground Plane
+
0.1uF
+
10uF
AVSS33A
AVSS18D
Fig 6. Bypass Capacitor for Power Supply Pins
Fig 7. Bypass Capacitors for Reference Pins
Analog pins and digital pins must be separated, Analog pins should be located on the analog ground
plane and digital pins should be located on the digital ground plane. Analog ground and digital ground
connection is recommended to only one path through ferrite bead like Fig 6. Supply bypass capacitors
should be located as close as possible to chip. Small bypass capacitor (0.1uF) should be positioned first
to chip than large bypass capacitor (10uF).
Reference (VREF) bypass capacitors (Fig 7.) should be located as close as possible to chip.
AOUTL
+ 1uF
L-CH Output
100k
AVSS33A
AOUTR
+ 1uF
R-CH Output
100k
AVSS33A
Fig 8. Analog output application
Fig8 is simple high pass filter circuit for analog output. It performs ac-coupling for analog output signal
from analog common level to analog ground. Recommended component values are 1uF and 100k Ω
User Guide
- This analog Core Verilog behavioral-modeling will be supplied.
SEC ASIC
17/17
ANALOG
16/20/24Bit 44.1/32/48kHz Sigma-Delta Stereo DAC
DAC0415X
FEEDBACK REQUEST
Sigma-Delta DAC Specification
We appreciate your interest in our products. If you have further questions, please specify in the
attached form. Thank you very much.
Parameter
Min
Typ
Max
Unit
supply voltage
V
Max master clock frequency
Hz
Operating temperature
℃
Sampling Frequency
Hz
Dynamic range
dB
Total harmonic distortion
dB
Signal-to-noise ratio
dB
Input format resolution
(Serial/Parallel interface)
Bit
Channel
Mono
Stereo
Power dissipation
mW
Full scale output voltage range
Vpp
group delay
Remarks
sec
Phase linearity deviation for
passband region
(Deg)
Peak-to-peak frequency response
ripple for passband region
dB
- Could you explain external/internal pin configurations as required?
- Specially requested function list :
SEC ASIC
ANALOG
16/20/24Bit 44.1/32/48kHz Sigma-Delta Stereo DAC
DAC0415X
History Card
Version
Date
Modified Items
Ver 1.0
'00.Sep.
1. Original version published
Ver 1.1
'01.Mar.
1. I/O pad type changed (Core Pin Description)
Ver 2.0
'01.Feb
1. Data Sheet Up-date
Ver3.0
`01.April
1. Data Sheet Up-Date
2. AOUTL,AOUTR GDS Port changed
Ver4.0
`01.Dec
1. Final Data Sheet
SEC ASIC
Comments
ANALOG