ETC HY51S64803HG(HGL)

HY51V(S)64803HG/HGL
8M x 8Bit EDO DRAM
PRELIMINARY
DESCRIPTION
This familiy is a 64Mbit dynamic RAM organized 8,388,608 x 8 bit configuration with Extended Data Out
mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The advanced circuit and process allow this device to achieve high performance and low power dissipation. Features are access time(45ns or 50ns) and refresh cycle(8K ref ) and power consumption
(Normal or low power with self refresh).
Advanced CMOS process as well as circuit techniques for wide operating margins allow this device to
achieve high speed access and high reliability
FEATURES
•
•
•
•
•
•
•
Extended data out operation
Read-modify-write capability
Multi-bit parallel test capability
LVTTL(3.3V) compatible inputs and outputs
/RAS only, CAS-before-/RAS, Hidden and self
refresh(L-version) capability
•
JEDEC standard pinout
32pin plastic SOJ/TSOP-II(400mil)
Single power supply of 3.3V +/- 10%
Battery back up operation(L-version)
•
•
Fast access time and cycle time
Part No
tRAC
tAA
tCAC
tRC
tHPC
HY51V(S)64803HG/HGL-45
45ns
23ns
12ns
74ns
17ns
HY51V(S)64803HG/HGL-5
50ns
25ns
13ns
84ns
20ns
HY51V(S)64803HG/HGL-6
60ns
30ns
15ns
104ns
25ns
Power dissipation
Active
Standby
•
45ns
50ns
60ns
352mW
312mW
278mW
1.8mW(CMOS level Max)
0.72mW (L-version : Max)
Refresh cycle
Part No
Ref
Normal
HY51V64803HG*
8K
64ms
HY51V64803HGL**
8K
L-part
128ms
* Normal : /RAS only ref : 8K/64ms, CBR & Hidden ref : 4K /64ms
** L-part : /RAS only ref : 8K 128ms, CBR & Hidden ref : 4K/128ms
ORDERING INFORMATION
Part Number
Access Time
Package
HY51V(S)64803HG/HG(L)J-45
HY51V(S)64803HG/HG(L)J-5
HY51V(S)64803HG/HG(L)J-6
45ns
50ns
60ns
400mil 32pin SOJ
HY51V(S)64803HG/HG(L)T-45
HY51V(S)64803HG/HG(L)T-5
HY51V(S)64803HG/HG(L)T-6
45ns
50ns
60ns
400mil 32pin TSOP-II
(S) : Self refresh,
(L) : Low power
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.0.1/Apr.01
HY51V(S)64803HG/HGL
PIN CONFIGURATION
VCC
1
32
VSS
IO0
2
31
IO7
IO1
3
30
IO6
IO2
4
29
IO5
IO3
5
28
IO4
NC
6
27
VSS
VCC
7
26
/CAS
/WE
8
25
/OE
/RAS
9
24
A12
A0
10
23
A11
A1
11
22
A10
A2
12
21
A9
A3
13
20
A8
A4
14
19
A7
A5
15
18
A6
VCC
16
17
VSS
32 Pin Plastic SOJ / TSOP-II
PIN DESCRIPTION
Pin
Function
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
Write Enable
/OE
Output Enable
A0-A12
Address Inputs
A0-A12
Refresh Address Inputs
I/O 0- I/O 7
Data Input / Output
Vcc
Power (3.3V)
Vss
Ground
NC
No connection
Rev.0.1/Apr.01
2
HY51V(S)64803HG/HGL
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
o
C
Storage Temperature
TSTG
-55 ~ 125
o
C
Voltage on Any Pin relative to Vss
VT
-0.5 ~ Vcc + 0.5
(Max 4.6V)
V
Voltage on Vcc relative to Vss
Vcc
-0.5 ~ 4.6
V
Short Circuit Output Current
IOUT
50
mA
Power Dissipation
PT
1
W
Note : Operation at above absolute maximum rating can adversely affect device reliability.
Recommended DC OPERATING CONDITIONS (TA=0 to 70 oC)
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
Vcc
3.0
3.3
3.6
V
1,2
Power Supply Voltage
Vss
0
0
0
V
2
Input High Voltage
VIH
2.0
-
Vcc + 0.3
V
1
Input Low Voltage
VIL
-0.3
-
0.8
V
1
Note : All voltages are referenced to Vss
1. 6.0V at pulse width 10ns which is measured at Vcc
2. -0.1V at pulse width 10ns which is measured at Vss
Rev.0.1/Apr.01
3
HY51V(S)64803HG/HGL
DC CHARACTERISTICS (Vcc = 3.3V +/- 10%, TA=0 to 70°C)
Symbol
Parameter
Min
Max
Unit
2.4
Vcc
V
0
0.4
V
45ns
-
130
50ns
-
120
60ns
-
110
-
1
45ns
-
130
50ns
-
120
60ns
-
110
45ns
-
100
50ns
-
90
60ns
-
80
CMOS interface ( /RAS, /UCAS, /LCAS >= Vcc-0.2V, Dout = High-Z)
-
0.5
mA
Standby current ( L-version)
-
200
uA
45ns
-
130
50ns
-
120
60ns
-
110
VOH
Output Level
Output Level voltage(Iout= -2mA)
VOL
Output Level
Output Level voltage(Iout=2mA)
ICC1
ICC2
ICC3
ICC4
Operating current ( tRC = tRC min)
Standby current (TTL interface)
Power supply standby current
(/RAS, /UCAS,/LCAS=VIH, Dout = High-Z)
/RAS only refresh current (tRC= tRC min)
Extended data out page mode current
(/RAS=VIL, /CAS, Address cycling : tHPC=tHPC min)
mA
Note
1, 2
mA
mA
2
mA
1, 3
ICC5
ICC6
/CAS-before-/RAS refresh current (tRC=tRC min)
4
mA
ICC7
Battery back up operating current (standby with CBR)
(tRC=31.25us, tRAS=300ns, Dout=High-Z)
-
350
uA
4, 5
ICC8
Standby current
Power supply standby current
(/RAS=VIH, /CAS = VIL, Dout=Enable)
-
5
uA
1
ICC9
Self refresh current
(/RAS, /CAS <= 0.2V, Dout=High-Z)
-
350
uA
5
II(L)
Input leakage current, Any input (0V<= Vin<=Vcc)
-5
5
uA
IO(L)
Output leakage current, (Dout is disabled, 0V<= Vout<=Vcc)
-5
5
uA
Note :
1. Icc depends on output load condition when the device is selected, Icc(max) is specified at the output open condition
2. Address can be changed once or less while RAS=VIL
3. Measured with one sequential address change per EDO cycle, tHPC
4. VIH>=Vcc-0.2V, 0V<=VIL<=0.2V
5. L-Version
Rev.0.1/Apr.01
4
HY51V(S)64803HG/HGL
CAPACITANCE (Vcc=3.3V +/-10%, TA=25°C)
Parameter
Symbol
Min.
Max
Unit
Note
Input capacitance (Address)
CI1
-
5
pF
1
Input capacitance (Clocks)
CI2
-
5
pF
1
Output capacitance (Data-in, Data-out)
CI/O
-
7
pF
1, 2
Note : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. /RAS, /UCAS and /LCAS = VIH to disable Dout
AC CHARACTERISTICS
(Vcc=3.3V +/-10%, TA=0~70C, Note 1, 2, 19)
Test Condition
•
•
•
Input rise and fall times = 2ns
Input level : VIL/VIH = 0.0 / 0.3V
Input timing reference level : VIL/VIH = 0.8/2.0V
•
Output timing reference level :
VOL/VOH=0.8/0.2V
Output load : 1 TTL gate + CL (100pF)
including scope and jig
•
Read, Write, Read-modify-Write and Refresh Cycles
-45
Parameter
-50
-60
Symbol
Unit
Min
Max
Min
Max
Min
Max
Note
Random read or write cycle time
tRC
74
-
84
-
104
-
ns
/RAS precharge time
tRP
25
-
30
-
40
-
ns
/CAS precharge time
tCP
7
-
8
-
10
-
ns
/RAS pulse width
tRAS
45
10,000
50
10,000
60
10,000
ns
/CAS pulse width
tCAS
7
10,000
8
10,000
10
10,000
ns
Row address set-up time
tASR
0
-
0
-
0
-
ns
Row address hold time
tRAH
7
-
8
-
10
-
ns
Column address set-up time
tASC
0
-
0
-
0
-
ns
Column address hold time
tCAH
7
-
8
-
10
-
ns
/RAS to /CAS delay time
tRCD
11
33
12
37
14
45
ns
3
/RAS to Column address delay time
tRAD
9
22
10
25
12
30
ns
4
/RAS hold time
tRSH
12
-
13
-
15
-
ns
/CAS hold time
tCSH
38
-
40
-
42
-
ns
/CAS to /RAS precharge time
tCRP
5
-
5
-
5
-
ns
Rev.0.1/Apr.01
5
HY51V(S)64803HG/HGL
- continued -45
Parameter
-50
-60
Symbol
Min
Max
Min
Max
Min
Max
Unit
Note
/OE to Din delay time
tODD
12
-
13
-
15
-
ns
5
/OE delay time from Din
tDZO
0
-
0
-
0
-
ns
6
/CAS delay time from Din
tDZC
0
-
0
-
0
-
ns
6
Transition time ( Rise and Fall)
tT
2
50
2
50
2
50
ns
7
-
64
-
64
-
64
ms
8K Ref.
-
128
-
128
-
128
ms
8K Ref.
Unit
Note
Refresh period
tREF
Refresh period (L-version)
Read Cycles
-45
Parameter
-50
-60
Symbol
Min
Max
Min
Max
Min
Max
Access time from /RAS
tRAC
-
45
-
50
-
60
ns
8, 9
Access time from /CAS
tCAC
-
12
-
13
-
15
ns
9,10,17
Access time from column address
tAA
-
23
-
25
-
30
ns
9,11,17
Access time from /OE
tOAC
-
12
-
13
-
15
ns
9
Read command set-up time
tRCS
0
-
0
-
0
-
ns
Read command hold time to /CAS
tRCH
0
-
0
-
0
-
ns
12
Read command hold time to /RAS
tRRH
0
-
0
-
0
-
ns
12
Column address to /RAS lead time
tRAL
23
-
25
-
30
-
ns
Column address to /CAS lead time
tCAL
15
-
15
-
18
-
ns
Output buffer turn off delay time from /CAS
tOFF
-
12
-
13
-
15
ns
13,21
Output buffer turn off delay time from /OE
tOEZ
-
12
-
13
-
15
ns
13
/CAS to Din delay time
tCDD
12
-
13
-
15
-
ns
5
/RAS to Din delay time
tRDD
12
-
13
-
15
-
ns
/WE to Din delay time
tWDD
12
-
13
-
15
-
ns
Output buffer turn off delay time from /RAS
tOFR
-
12
-
13
-
15
ns
13,21
Output buffer turn off delay time from /WE
tWEZ
-
12
-
13
-
15
ns
13
Output data hold time
tOH
3
-
3
-
3
-
ns
21
Output data hold time from /RAS
tOHR
3
-
3
-
3
-
ns
21
Read command hold time from /RAS
tRCHR
45
-
50
-
60
-
ns
Output data hold time from /OE
tOHO
3
-
3
-
3
-
ns
/CAS to output in low-Z
tCLZ
0
-
0
-
0
-
ns
Rev.0.1/Apr.01
6
HY51V(S)64803HG/HGL
Write Cycles
-45
Parameter
-50
-60
Symbol
Min
Max
Min
Max
Min
Max
Unit
Note
14
Write command set-up time
tWCS
0
-
0
-
0
-
ns
Write command hold time
tWCH
7
-
8
-
10
-
ns
Write command pulse width
tWP
7
-
8
-
10
-
ns
Write command to /RAS lead time
tRWL
12
-
13
-
15
-
ns
Write command to /CAS lead time
tCWL
7
-
8
-
10
-
ns
Data-in set-up time
tDS
0
-
0
-
0
-
ns
15
Data-in hold time
tDH
7
-
8
-
10
-
ns
15
Unit
Note
Read-Modify-Write Cycles
-45
Parameter
-50
-60
Symbol
Min
Max
Min
Max
Min
Max
Read-modify-write cycle time
tRWC
101
-
116
-
140
-
ns
/RAS to /WE delay time
tRWD
63
-
67
-
79
-
ns
14
/CAS to /WE delay time
tCWD
30
-
30
-
34
-
ns
14
Column address to /WE delay time
tAWD
40
-
42
-
49
-
ns
14
/OE hold time from /WE
tOEH
12
-
13
-
15
-
ns
Refresh cycles
-45
Parameter
-50
-60
Symbol
Unit
Min
Max
Min
Max
Min
Max
/CAS set-up time
( /CAS-before-/RAS Refresh Cycle)
tCSR
5
-
5
-
5
-
ns
/CAS hold time
( /CAS-before-/RAS Refresh Cycle)
tCHR
7
-
8
-
10
-
ns
/WE set-up time
( /CAS-before-/RAS Refresh Cycle)
tWRP
0
-
0
-
0
-
ns
/WE hold time
( /CAS-before-/RAS Refresh Cycle)
tWRH
7
-
8
-
10
-
ns
/RAS precharge to /CAS hold time
( /CAS-before-/RAS Refresh Cycle)
tRPC
5
-
5
-
5
-
ns
Rev.0.1/Apr.01
Note
7
HY51V(S)64803HG/HGL
Extended Data Out Mode Cycles
-45
Parameter
-50
-60
Symbol
Min
Max
Min
Max
Min
Max
Unit
Note
20
EDO page mode cyle time
tHPC
17
-
20
-
25
-
ns
Write pulse width during /CAS precharge
tWPE
7
-
8
-
10
-
ns
EDO mode /RAS pulse width
tRASP
-
100K
-
100K
-
100K
ns
16
Access time from /CAS precharge
tACP
-
28
-
28
-
35
ns
9,17
/RAS hold time from /CAS precharge
tRHCP
26
-
28
-
35
-
ns
/CAS hold time referred /OE
tCOL
7
-
8
-
10
-
ns
/CAS to /OE set-up time
tCOP
5
-
5
-
5
-
ns
Read command hold time
from /CAS precharge
tRCHP
26
-
28
-
35
-
ns
Output data hold time from /CAS low
tDOH
3
-
3
-
3
-
ns
/OE precharge time
tOEP
7
-
8
-
10
-
ns
9,22
EDO Page Mode Read-Modify-Write Cycle
-45
Parameter
-50
-60
Symbol
Unit
Min
Max
Min
Max
Min
Max
Note
EDO read-modify-write cycle time
tHPRWC
57
-
57
-
68
-
ns
EDO page mode read-modify-write cycle
/CAS precharge to /WE delay time
tCPW
45
-
45
-
54
-
ns
14
Unit
Note
Self Refresh Cycle (L-Version)
-45
Parameter
-50
-60
Symbol
Min
Max
Min
Max
Min
Max
/RAS pulse width ( self refresh)
tRASS
100
-
100
-
100
-
us
26
/RAS precharge time ( self refresh)
tRPS
90
-
90
-
110
-
ns
26
/CAS hold time ( self refresh)
tCHS
-50
-
-50
-
-50
-
ns
Rev 0.1 / Apr. 01
HY51V(S)64803HG/HGL
Notes :
1. AC measurements assume t T = 2ns
2. AC initial pause of 200us is required after power up followed by a minimum of eight initialization cycles
( any combination of cycles containing /RAS-only refresh or /CAS-before-/RAS refresh)
3. Operation with the tRCD(max) limit insures that tRAC(max) can be met, t RCD(max) is specified as a
reference point only : if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by tCAC.
4. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only : if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by tAA.
5. Either tODD or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals, also transition times
are measured between V IH(min) and VIL(max)
8. Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown
9. Measured with a load circuit equivalent to 1 TTL loads and 100pF.
10. Assumes that tRCD>=tRCD(max) and tRCD + tCAC(max) >= tRAD + tAA(max)
11. Assumes that tRAD>=tRAD(max) and tRCD + tCAC(max) <= tRAD + tAA(max)
12. Either tRCH of tRRH must be satified for a read cycles
13. tOFF(max), tOEZ(max), tOFR(max) and tWEZ(max) define the time at which the outputs achieve the
open circuit condition and is not referenced to output voltage levels
14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only : If tWCS >=t WCS(min), the cycle is an early write
cycle and the data out pin will remain open circuit(high impedance) throughout the entire cycle :
If tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min), the cycle is a read-modify-write and
the data output will contain data read from the selected cell : if neither of the above sets of conditions
is satified, the condition of the data out (at access time) is indeterminate.
15. tDS and tDH are refered to /CAS leading edge in early write cycles and to /WE leading edge in delayed
write or read-modify-write cycles
16. tRASP defineds /RAS pulse width in extended data out mode cycles
17. Access time is determined by the longest among tAA, tCAC and tACP
18. In delaying write or read-modify-write cycles, /OE must disable output buffer prior to applying data to
the device.
Rev 0.1 / Apr. 01
HY51V(S)64803HG/HGL
19. When output buffers are enabled once, sustain the low impedence state until valid data is obtained.
when output buffer is turned on and off within a very short time, generally it causes large Vcc/Vss line
noise, which causes to degrade V IH min / VIL max level
20. tHPC(min) can be achieved during a series of EDO mode early write cycles or EDO mode read cycels
If both write and read operation are mixed in a EDO mode, /RAS cycle[EDO mode mix cycle (1)(2)]
minimum value of /CAS cycle t HPC[tCAS + tCP + 2tT] become greater than the specified tHPC(min)
value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle
(1) and (2)
21. Data output turns off and becomes high impedance from later rising edge of /RAS and /CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of /RAS and
/CAS between tOHR and tOH and between tOFR and tOFF
22. tDOH defines the time at which the output level go cross, VOL=0.8V, VOH=2.0V of output timing
reference level.
23. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64ms
period on the condition a) and b) below
a) Enter self refresh mode within 15.6us after either burst refresh or distributed refresh at equal interval
to all refresh addresses are completed.
b) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6us after
exiting from self refresh mode
24. In case of entering from /RAS-only-refresh, It is necessary to execute CBR refresh before and after
self refresh mode according as note 23
25. For L-version, It is available to apply each 128ms and 31.2us instead of 64ms and 15.6us at note 23
26. At tRASS > 100us, self refresh mode is activated, and not active at tRASS < 10us, It is undefined within
the range of 10us < tRASS < 100us. For tRASS > 10us, It is necessary to satify tRPS
27. XXX : H or L [ H : VIH(min) <= VIN <=VIH(max), L : VIH(min) <=VIN <=VIH(max)]
///// : Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be
applied VIH or VIL
Rev 0.1 / Apr. 01
HY51V(S)64803HG/HGL
PACKAGE INFORMATION
400mil 32pin SOJ Dimension
Unit: mm
0.64 MIN
20.95 MIN
21.38 MAX
1.165 MAX
11.31 MAX
11.05 MIN
9.65 MAX
9.15 MIN
10.03 MIN
10.29 MAX
3.24 MIN
3.76 MAX
MIN
1.16 MAX
2.09 MIN
3.01 MAX
0.33 MIN
0.53 MAX
1.27
0.33 MIN
0.49 MAX
0.10
400mil 32p TSOP-II Dimension
Unit: mm
10.16
1.20 MAX
NORMAL TYPE
1.15 MAX
0.42
0.08
0.40
0.06
1.27
0.80
11.96 MAX
0.40 MIN
0.60 MAX
11.56 MIN
0 ~ 5 Deg.
0.145
0.05
0.125
0.04
0.68
20.95 MIN
21.35 MAX
0.08 MIN
0.18 MAX
0.10
Dimension including the plating thickness
Base material dimension
Rev.0.1/Apr.01
11