GM71V65163C
GM71VS65163CL
4,196,304 WORDS x 16 BIT
MOS DYNAMIC RAM
Description
Pin Configuration
50 SOJ / TSOP-II
The GM71V(S)65163C/CL is the new generation
dynamic RAM organized 4,196,304 words by 16
bits. The GM71V(S)65163C/CL utilizes advanced
CMOS Silicon Gate Process Technology as well as
advanced circuit techniques for wide operating
margins, both internally and to the system user.
System oriented features include single power supply
of 3.3V+/-10% tolerance, direct interfacing
capability with high performance logic families such
as Schottky TTL.
VCC
1
50
VSS
IO0
2
49
IO15
IO1
3
48
IO14
IO2
4
47
IO13
IO3
5
46
IO12
VCC
6
45
VSS
IO4
7
44
IO11
IO5
8
43
IO10
IO6
9
42
IO9
IO7
10
41
IO8
NC
11
40
NC
VCC
12
39
VSS
/WE
13
38
/LCAS
/RAS
14
37
/UCAS
NC
15
36
/OE
NC
16
35
NC
NC
17
34
NC
NC
18
33
NC
A0
19
32
A11
A1
20
31
A10
A2
21
30
A9
22
29
A8
A7
The GM71V(S)65163C/CL offers Extended Data
Out(EDO) Mode as a high speed access mode.
Features
* 4,196,304 Words x 16 Bit
* Extended Data Out (EDO) Mode Capability
* Fast Access Time & Cycle Time
(Unit: ns)
tRAC
tAA
tCAC
tRC
tHPC
GM71V(S)65163C/CL-5
50
25
13
90
20
A3
A4
23
28
GM71V(S)65163C/CL-6
60
30
15
110
25
A5
24
27
A6
VCC
25
26
VSS
*Power dissipation
- Active : 540mW/504mW(MAX)
- Standby : 1.8 mW ( CMOS level : MAX )
0.54mW ( L-Version : MAX)
*EDO page mode capability
*Access time : 50ns/60ns (max)
*Refresh cycles
- RAS only Refresh
4096 cycles/64 ms (GM71V65163C)
4096 cycles/128ms (GM71VS65163CL)(L_Version)
*CBR & Hidden Refresh
4096 cycles/64 ms (GM71V65163C)
4096 cycles/128 ms (GM71VS65163CL)( L-Version )
*4 variations of refresh
-RAS-only refresh
-CAS-before-RAS refresh
-Hidden refresh
-Self refresh (L-Version)
*Single Power Supply of 3.3V+/-10 % with a built-in VBB generator
*Battery Back Up Operation ( L-Version )
Rev 0.1 / Apr’01
(Top View)
GM71V65163C
GM71VS65163CL
Pin Description
Pin
Function
A0-A11
Address Inputs
A0-A11
Refresh Address Inputs
RAS
UCAS,LCAS
OE
Pin
Function
Write Enable
WE
I/O0 - I/O15
Data Input / Output
Row Address Strobe
VCC
Power (+3.3V)
Column Address Strobe
VSS
Ground
Output Enable
NC
No Connection
Ordering Information
Type No.
Access Time
Package
GM71V(S)65163C/CLJ-5
GM71V(S)65163C/CLJ-6
50ns
60ns
400 Mil
50Pin
Plastic SOJ
GM71V(S)65163C/CLT-5
GM71V(S)65163C/CLT-6
50ns
60ns
400 Mil
50Pin
Plastic TSOP II
Absolute Maximum Ratings*
Symbol
Parameter
TSTG
Rating
Unit
-55 to 125
C
-0.5 to VCC + 0.5
(MAX ; 4.6V)
V
-0.5 to 4.6
V
Storage Temperature (Plastic)
VT
Voltage on any Pin Relative to VSS
VCC
Voltage on VCC Relative to VSS
IOUT
Short Circuit Output Current
50
mA
Power Dissipation
1.0
W
PT
*Note : Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Recommended DC Operating Conditions (TA = 0 ~ 70C)
Symbol
Parameter
Min
Typ
Max
Unit
Notes
VCC
Supply Voltage
3.0
3.3
3.6
V
1,2
VSS
Supply Voltage
0
0
0
V
2
VIH
Input High Voltage
2.0
-
Vcc+0.3
V
1
VIL
Input Low Voltage
-0.3
-
0.8
V
1
TA
Ambient Temperature under Bias
0
-
70
C
Rev 0.1 / Apr’01
GM71V65163C
GM71VS65163CL
DC Electrical Characteristics: (VCC = 3.3V+/-10%, TA = 0 ~ 70C)
Symbol
Parameter
Min
Max
Unit Note
VOH
Output Level
Output Level Voltage (IOUT = -2mA)
2.4
VCC
V
VOL
Output Level
Output Level Voltage (IOUT = 2mA)
0
0.4
V
ICC1
Operating Current (tRC = tRC min)
50ns
-
150
60ns
-
140
-
2
mA
ICC2
Standby Current (TTL interface)
Power Supply Standby Current
(RAS, UCAS,LCAS= VIH, DOUT = High-Z)
ICC3
RAS-Only Refresh Current
( tRC = tRC min)
50ns
-
150
60ns
-
140
Extended Data Out page Mode Current
(RAS = VIL, CAS, Address Cycling: tHPC = tHPC min)
50ns
-
120
60ns
-
110
-
0.5
mA
-
300
uA
-
150
ICC4
ICC5
ICC6
CMOS interface
(RAS, UCAS,LCAS>=VCC-0.2V, DOUT = HighZ)
Standby Current(L_Version)
CAS-before-RAS Refresh Current
(tRC = tRC min)
50ns
60ns
1,2
mA
mA
2
mA
1,3
4
mA
140
ICC7
Battery Back Up Operating Current(Standby with CBR)
(tRC=31.25us,,tRAS=300ns,Dout=High-Z)
-
500
uA
4, 5
ICC8
Standby Current (CMOS)
Power Supply Standby Current
RAS = VIH,UCAS, LCAS = VIL , DOUT = Enable
-
5
mA
1
ICC9
Self Refresh Current
(RAS,UCAS,LCAS <=0.2V,Dout=High-Z)
-
400
uA
5
II(L)
Input Leakage Current, Any Input
(0V<=VIN<=Vcc)
-5
5
uA
IO(L)
Output Leakage Current
(DOUT is Disabled, 0V<=VOUT<=Vcc)
-5
5
uA
Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Measured with one sequential address change per EDO cycle, tHPC.
4. VIH>=VCC-0.2V, 0V<=VIL<=0.2V
5. L-Version
Rev 0.1 / Apr’01
GM71V65163C
GM71VS65163CL
Capacitance (VCC = 3.3V+/-10%, TA = 25C)
Symbol
Parameter
Typ
Max
Unit
Note
CI1
Input Capacitance (Address)
-
5
pF
1
CI2
Input Capacitance (Clocks)
-
7
pF
1
CI/O
Output Capacitance (Data-in,Data-Out)
-
7
pF
1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. RAS, UCAS and LCAS = VIH to disable DOUT.
AC Characteristics (VCC = 3.3V+/-10%, TA = 0 ~ 70C, Notes 1, 2,19,20)
Test Conditions
Input rise and fall times : 2ns
Output timing reference levels : VOL/VOH = 0.8/2.0V
Input level : VIL/VIH = 0.0/3.0V
Output load : 1 TTL gate+CL (100pF)
Input timing reference levels : VIL/VIH = 0.8/2.0V
(Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
GM71V(S)65163C/CL-5 GM71V(S)65163C/CL-6
Parameter
Symbol
Unit
Min
Max
Min
Max
-
104
-
ns
40
-
ns
Notes
tRC
Random Read or Write Cycle Time
84
tRP
RAS Precharge Time
30
tCP
CAS Precharge Time
8
-
10
-
ns
tRAS
RAS Pulse Width
50
10000
60
10000
ns
tCAS
CAS Pulse Width
8
10000
10
10000
ns
tASR
Row Address Set-up Time
0
-
0
-
ns
tRAH
Row Address Hold Time
8
-
10
-
ns
tASC
Column Address Set-up Time
0
-
0
-
ns
21
tCAH
Column Address Hold Time
8
-
10
-
ns
21
tRCD
RAS to CAS Delay Time
12
37
14
45
ns
3
tRAD
RAS to Column Address Delay Time
10
25
12
30
ns
4
tRSH
RAS Hold Time
13
-
15
-
ns
tCSH
CAS Hold Time
35
-
40
-
ns
tCRP
CAS to RAS Precharge Time
5
-
5
-
ns
22
tODD
OE to DIN Delay Time
13
-
15
-
ns
5
tDZO
OE Delay Time from DIN
0
-
0
-
ns
6
tDZC
CAS Delay Time from DIN
0
-
0
-
ns
6
tT
tREF
TransitionTime (Rise and Fall)
2
50
2
50
ns
7
Refresh Period
-
64
-
64
ms
Refresh Period ( L-Version )
-
128
-
128
ms
Rev 0.1 / Apr’01
-
24
4096
cycles
4096
cycles
GM71V65163C
GM71VS65163CL
Read Cycles
Parameter
Symbol
GM71V(S)65163C/CL-5 GM71V(S)65163C/CL-6
Notes
Unit
Min
Max
Min
Max
tRAC
Access Time from RAS
-
50
-
60
ns
8,9
tCAC
Access Time from CAS
-
13
-
15
ns
9,10,17
tAA
tOAC
Access Time from Column Address
-
25
-
30
ns
9,11,17
Access Time from OE
-
13
-
15
ns
9
tRCS
Read Command Set-up Time
0
-
0
-
ns
21
tRCH
Read Command Hold Time to CAS
0
-
0
-
ns
12,22
tRRH
Read Command Hold Time to RAS
0
-
0
-
ns
12
tRAL
Column Address to RAS Lead Time
25
-
30
-
ns
tCAL
Column Address to CAS Lead Time
15
-
18
-
ns
tOFF
Output Buffer Turn-off Delay Time from CAS
-
13
-
15
ns
13,26
tOEZ
Output Buffer Turn-off Delay Time from OE
-
13
-
15
ns
13
tCDD
CAS to DIN Delay Time
13
-
15
-
ns
5
tRDD
RAS to DIN Delay Time
13
-
15
-
ns
tWDD
WE to DIN Delay Time
13
-
15
-
ns
tOFR
Output Buffer Turn-off Delay Time from RAS
-
13
-
15
ns
13,26
tWEZ
Output Buffer Turn-off Delay Time from WE
-
13
-
15
ns
13
tOH
Output Data Hold Time
3
-
3
-
ns
26
tOHR
Output Data Hold Time from RAS
3
-
3
-
ns
26
tRCHR
Read Command Hold Time from RAS
50
-
60
-
ns
tOHO
Output data hold time from OE
3
-
3
-
ns
tCLZ
CAS to Output in Low - Z
0
-
0
-
ns
Rev 0.1 / Apr’01
GM71V65163C
GM71VS65163CL
Write Cycles
GM71V(S)65163C/CL-5
GM71V(S)65163C/CL-6
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
tWCS
Write Command Set-up Time
0
-
0
-
ns
14,21
tWCH
Write Command Hold Time
8
-
10
-
ns
21
tWP
Write Command Pulse Width
8
-
10
-
ns
tRWL
Write Command to RAS Lead Time
13
-
15
-
ns
tCWL
Write Command to CAS Lead Time
8
-
10
-
ns
23
tDS
Data-in Set-up Time
0
-
0
-
ns
15,23
tDH
Data-in Hold Time
8
-
10
-
ns
15,23
Unit
Notes
Read-Modify-Write Cycles
GM71V(S)65163C/CL-5
GM71V(S)65163C/CL-6
Parameter
Symbol
Min
Max
Min
Max
tRWC
Read-Modify-Write Cycle Time
116
-
140
-
ns
tRWD
RAS to WE Delay Time
67
-
79
-
ns
14
tCWD
CAS to WE Delay Time
30
-
34
-
ns
14
tAWD
Column Address to WE Delay Time
42
-
49
-
ns
14
tOEH
OE Hold Time from WE
13
-
15
-
ns
Refresh Cycles
Cycle
GM71V(S)65163C/CL-5
Symbol
Parameter
GM71V(S)65163C/CL-6
Min
Max
Min
Max
Unit
Notes
tCSR
CAS Set-up Time
(CAS-before-RAS Refresh Cycle)
5
-
5
-
ns
21
tCHR
CAS Hold Time
(CAS-before-RAS Refresh Cycle)
8
-
10
-
ns
22
tWRP
WE setup time
(CAS-before-RAS Refresh Cycle)
0
-
0
-
ns
tWRH
WE hold time
(CAS-before-RAS Refresh Cycle)
8
-
10
-
ns
tRPC
RAS Precharge to CAS Hold Time
5
-
5
-
ns
Rev 0.1 / Apr’01
21
GM71V65163C
GM71VS65163CL
Extended Data Out Mode Cycles
GM71V(S)65163C/CL-5 GM71V(S)65163C/CL-6
Parameter
Symbol
Unit
Min
Max
Min
Max
20
-
25
-
tHPC
EDO Page Mode Cycle Time
tWPE
Write pulse width during CAS Precharge
8
-
10
tRASP
EDO Mode RAS Pulse Width
-
100000
tACP
Access Time from CAS Precharge
-
tRHCP
RAS Hold Time from CAS Precharge
tCOL
Notes
25
-
ns
ns
-
100000
ns
16
28
-
35
ns
9,17,22
28
-
35
-
ns
CAS Hold Time Referred OE
8
-
10
-
ns
tCOP
CAS to OE set-up Time
5
-
5
-
ns
tRCHP
Read Command Hold Time from CAS
Precharge
28
-
35
-
ns
tDOH
tOEP
Output Data Hold Time from CAS Low
3
-
3
-
ns
OE Precharge Time
8
-
10
-
ns
9,27
EDO Page Mode Read-Modify-Write cycle
GM71V(S)65163C/CL-5 GM71V(S)65163C/CL-6
Parameter
Symbol
Unit
Max
Min
Max
57
-
68
-
ns
45
-
54
-
ns
14,22
Unit
Notes
tHPRWC EDO Read-Modify-Write Cycle Time
tCPW
Notes
Min
EDO Page Mode Read-Modify-Write Cycle
CAS Precharge to WE Delay Time
Self Refresh Cycles (L_Version)
GM71V(S)65163C/CL-5
Parameter
Symbol
GM71V(S)65163C/CL-6
Min
Max
Min
Max
tRASS
RAS Pulse Width(Self-Refresh)
100
-
100
-
us
31
tRPS
tCHS
RAS Precharge Time(Self-Refresh)
90
-
110
-
us
31
CAS Hold Time(Self-Refresh)
-50
-
-50
-
us
23
Rev 0.1 / Apr’01
GM71V65163C
GM71VS65163CL
Notes:
AC measurements assume tT = 2ns.
AC initial pause of 200us is required after power up followed by a minimum of eight
initialization cycles ( any combination of cycles containing RAS-only refresh or CAS-beforeRAS refresh)
3. Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only: if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by tCAC.
4. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only: if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by tAA.
5. Either tODD or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH(min) and VIL (max).
8. Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that tRCD>=tRCD(max) and tRCD + tCAC(max) >=tRAD + tAA(max).
11. Assumes that tRAD >=tRAD (max) and tRCD + tCAC(max)<=tRAD + tAA(max).
12. Either tRCH or tRRH must be satisfied for a read cycles.
1.
2.
13. tOFF(max), tOEZ(max), tOFR(max) and tWEZ(max) define the time at which the outputs achieve the
open circuit condition and is not referenced to output voltage levels.
14. tWCS, tRWD, tCWD, tAWD, and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only: if tWCS >=tWCS(min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle: if
tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min) and tCPW>=tCPW(min), the cycle is a readmodify-write and the data output will contain data read from the selected cell: if neither of the
above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
15. tDS and tDH are referred to UCAS and LCAS leading edge in early write cycles and to WE
leading edge in delayed write or read-modify-write cycles.
16. tRASP defines RAS pulse width in extended data out mode cycles.
17. Access time is determined by the longest among tAA, tCAC and tACP.
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device.
19. When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large VCC/VSS line noise, which causes to degrade VIH min/VIL max level.
20. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the
device. UCAS and LCAS cannot be staggered within the same write/read cycles.
21. tASC, tCAH, tRCS, tWCS, tWCH, tCSR and tRPC are determined by the earlier falling edge of UCAS or
LCAS.
22. tCRP, tCHR, tRCH, tACP and tCPW are determined by the later rising edge of UCAS or LCAS.
Rev 0.1 / Apr’01
GM71V65163C
GM71VS65163CL
23. tCWL, tDH, tDS and tCHS should be satisfied by the both UCAS and LCAS.
24. tCP is determined by the time that both UCAS and LCAS are high.
25. tHPC(min) can be achieved during a series of EDO mode early write cycles or EDO mode read
cycles. If both write and read operation are mixed in a EDO mode, RAS cycle { EDO mode mix
cycle (1),(2) } minimum value of CAS cycle tHPC(tCAS + tCP + 2tT) becomes greater than the
specified tHPC(min) value. The value of CAS cycle time of mixed EDO page mode is shown in
EDO page mode mix cycle (1) and (2).
26. Data output turns off and becomes high impedance from later rising edge of RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between tOHR and tOH, and between tOFR and tOFF.
27. tDOH defines the time at which the output level go cross. VOL=0.8V, VOH=2.0V of output timing
reference level.
28. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within
64ms period on the condition a and b below.
a. Enter self refresh mode within 15.6us after either burst refresh or distributed refresh at equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addressed within 15.6us
after exiting from self refresh mode.
29. In case of entering from RAS-only-refresh, it is necessary to execute CBR refresh before and
after self refresh mode according as note 28.
30. For L_Version, it is available to apply each 128§ Â and 31.2us instead of 64§ Âand 15.6us at
note 28.
31. At tRASS > 100 us , self refresh mode is activated, and not active at tRASS <10us. It is undefined
within the range of 10 us < tRASS < 100 us . for tRASS > 10 us , it is necessary to satisfy tRPS.
32. XXX: H or L ( H : VIH(min)<=VIN<=VIH(max), L: VIH(min)<=VIN<=VIH(max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
Rev 0.1 / Apr’01
GM71V65163C
GM71VS65163CL
TSOP-II 50 PIN Package Dimension
0.40 MIN
0.60 MAX
1.15 MAX
0.30
0.10
0.28
0.08
0.80
0.10
Dimension including the plating thickness
Base material dimension
Rev 0.1 / Apr’01
0.08 MIN
0.18 MAX
0.145
0.05
0.125
0.04
Unit: mm
0.80
0.68
1.20 MAX
10.16
11.56 MIN
0~5
11.96 MAX
¡ £
20.95 MIN
21.35 MAX