5 4 3 2 1 History D Rev. Date Description Made by Approved by 1.00 2008/03/17 First formal release Chris Lin Eric Hsu 1.10 2008/08/27 Add External Regulator circuit Chris Lin Eric Hsu 1.20 2009/02/26 Add I2C EEPROM circuit Chris Lin Eric Hsu 1.30 2009/08/28 1. 2. 3. 4. 5. 6. Chris Lin Eric Hsu 1.40 2009/09/21 1. Add chip power switch descripter. 2. Add down port LED circuit. Chris Lin Eric Hsu 1.50 2009/12/09 Add R7 0R For EMI Solution Chris Lin Eric Hsu 1.60 2010/03/12 1. Add LB7 For EMI Solution. Nash Li 2. 24C02 pin5 pull-up resister from 15K change to 10K. 3. Delete down port LED circuit. C19 form 0.1u change to 1u R13 from 1K change to 15K R9, R10 from 10K, 20K change to 30K R3 from 470R change to 680R C12 form 0.1u change to 1u Change parts number D C C Eric Hsu GL850G-SSOP28 chip version & schematic option. B B CHIP Version GL850G-21 Power Switch 24C02 V GL850G-22 V V GL850G-11 2Port only GL850G-13 2Port only V V GENESYS LOGIC, INC. A A GLB6054A GL850G SSOP28 Demo Board Title USB2.0 Hub Controller Size B Date: 5 4 3 2 Document Number Rev 1.60 History Friday, March 12, 2010 Sheet 1 1 of 2 5 4 3 2 1 GL850G-22 not support power switch R1: Mount -> Internal regulator Remove -> External regulator B_VCC LB2 FB U1 PWREN1# OVCUR1# PWREN2# OVCUR2# PGANG PSELF DVDD GND VCC LB1 FB 3_3V_IN AVDD3 DP1 DM1 DP0 GL850G DM0 SSOP28 V33 V5 AVDD3 AVDD DM2 DP2 RREF AVDD X1 X2 DM3 DP3 AVDD DM4 DP4 RESET# TEST/SCL DP1 DM1 DP0 DM0 3_3V_IN 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AVDD AVDD2 D AVDD1 DM2 DP2 RREF AVDD2 X1 X2 DM3 DP3 AVDD3 DM4 DP4 RESET TEST/SCL AVDD AVDD1 DVDD Option: Customized VID, PID, String, Configuration. + EC1 10uF PGANG PSELF LB7 DGND C2 0.1uF C3 0.1uF C4 0.1uF C5 1uF C6 1uF DVDD 1 2 3 4 C7 0.1uF C1 A0 A1 A2 GND 8 7 6 5 VCC WP SCL SDA 1 2 3 4 5 DM0 DP0 U2 R1 0R PWREN1 OVCUR1 UP1 0.1uF TEST/SCL PWREN1 R13 10K G4 G3 G2 G1 G4 G3 VCC G2 DG1 D+ ID GND H1 H2 D H1 H2 SMD USB miniAB AT24C02 DVDD FB EC1 close to PIN24 C8 0.1uF As close to GL850G DOWN1 LB3 FB G1 VDP1 + EC2 100uF VCC VDP3 RESET R9 30K X1 C10 20P OVCUR1 C12 1uF R10 30K 1 2 C11 20P 12MHz USBA-A DOWN2 R3 680R 680R 1% R7 0R R2 10K LB4 FB R5 100K R6 47K G1 VDP2 + R4 VDP4 C HAND2 DVDD EC3 100uF A B_VCC 6V2A Gang Mode RREF VDP2 G2 2 X2 1 VCC DD+ GND C13 0.1uF LED2 PGANG VCC DD+ GND G2 PWR_LED As close to GL850G HAND1 1 2 3 4 DM2 DP2 HAND2 USBA-A C F1 VDP1 X1 C C9 0.1uF HAND1 1 2 3 4 DM1 DP1 DOWN3 LB5 FB G1 VDP3 Poly Fuse for Gang Mode + EC4 100uF B C14 0.1uF HAND1 1 2 3 4 DM3 DP3 VCC DD+ GND G2 B HAND2 USBA-A J1 DC JACK Option: 5V to 3.3V regulator. POWER CIRCUIT VCC I Vin P 1uF 2 3 1 VCC Vout O GND G 0 3_3V_IN + C19 1uF EC6 100uF C16 0.1uF HAND1 1 2 3 4 DM4 DP4 S + EC5 10uF B_VCC R11 510K G R12 4.7K D PSELF R17 VCC DD+ GND AME8805-SOT89 5V to 3.3V Q1 FDN338P S_VCC A P G1 VDP4 C18 S_VCC C15 0.1uF DOWN4 LB6 FB U4 NOTE: Please use 5V adapter G2 HAND2 USBA-A PSELF GENESYS LOGIC, INC. R17:Remove -> Internal regulator Mount -> External regulator A GLB6054A GL850G SSOP28 Demo Board Title USB2.0 Hub Controller Size B Date: 5 4 3 2 Document Number Rev 1.60 GL850G SSOP28 Friday, March 12, 2010 Sheet 1 2 of 2