SST ST7588T

Sitronix
ST7588T
81 x 132 Dot Matrix LCD Controller/Driver
n INTRODUCTION
ST7588T is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 132-segment,
80-common and 1-icon driver circuits. ST7588T can be connected directly to a microprocessor which accepts parallel
2
interface (8-bit), serial peripheral interface (3-line or 4-line SPI), I C interface. Display data stores in an on-chip display data
RAM (DDRAM) of 81 x 132 bits. It performs display data RAM read/write operation without external operating clock to
minimize the power consumption. In addition, because it contains power supply circuits to drive liquid crystal, it is possible to
make a display system with the fewest components.
n FEATURES
Single-chip LCD controller & driver
On-chip Low Power Analog Circuit
Driver Output Circuits
Ø
Built-in Voltage Booster (x2, x3, x4, x5, x6)
Ø
132-segment / 81-common (1/81 duty)
Ø
Support external booster supply (VOUT)
Ø
Optional display duty
Ø
Built-in Voltage Regulator
Ø
1/49, 1/65 and 1/81 (selected by MODE[1:0] pin)
With 255-step electronic contrast control
Partial display mode: 1/33 duty and 1/17 duty
(temperature gradient -0.12%/°C)
On-chip Display Data RAM
Ø
Built-in Voltage Follower (with 1/4 ~ 1/11 bias)
Ø
Ø
Supports external power supply circuits
Capacity: 81X132=10,692 bits
Microprocessor Interface
External RESB (hardware reset) Pin
Ø
8-bit parallel bi-directional interface supports
Built-in Oscillation Circuit
6800-series or 8080-series MPU
Ø
Ø
4-line A mode SPI (write only)
Wide Voltage Range
Ø
4-line B mode SPI (write only)
Ø
VDD1: 1.8V to 3.3V (typ.)
Ø
3-line 8-bit A mode SPI (write only)
Ø
VDD2: 2.4V to 3.3V (typ.)
Ø
3-line 8-bit B mode SPI (write only)
Ø
Recommend LCD Vop: 9.5V ~ 10.5V
Ø
3 line 9-bit SPI (write only)
Ø
Oscillator requires no external components
(1/10 Bias, 1/81 Duty)
2
Temperature Range: -30 to +85 °C
I C (Inter-Integrated Circuit) Interface (write only)
ST7588T
6800, 8080, 4-Line, 3-Line interface
(without I2C interface)
ST7588Ti
I2C interface
Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice.
Ver 1.3
1/61
2007/09/20
ST7588T
n PAD ARRANGEMENT (COG)
Chip Size: 7,708 μm × 980 μm
Bump Pitch: (minimum)
PAD NO 1~185, 248~276: 45μm (COM/SEG)
PAD NO 186~187, 188~189, 191~192, 193~194, 195~196, 197~198, 199~200, 201~202, 213~214,215~216: 119μm
PAD NO 187~188, 189~190, 192~193, 194~195, 196~197, 198~199, 200~201, 209~211, 212~213, 214~215, 216~217,
218~220: 73μm
PAD NO 190~191: 134μm;
PAD NO 202~203: 77μm;
PAD NO 203~204, 205~206: 175μm;
PAD NO 220~221: 93μm;
PAD NO 204~205, 206~207: 75μm
PAD NO 207~208: 150μm;
PAD NO 208~209: 68μm;
PAD NO 211~212, 217~218: 102μm
PAD NO 221~243, 244~247: 70μm
PAD NO 243~244: 145μm
Bump Size:
PAD NO 1~156, 174~185, 248~259: 30(x) μm × 80(y) μm
PAD NO 157~173, 260~276: 80(x) μm × 30(y) μm
PAD NO 186~202, 209~247: 55(x) μm × 60(y) μm
PAD NO 203~208: 45(x) μm × 60(y) μm
Bump Height: 17 μm
Chip Thickness: 480 μm
Ver 1.3
2/61
2007/09/20
ST7588T
n PAD CENTER COORDINATES (49 duty)
Pad No.
Pin Name
X
Y
Pad No.
Pin Name
X
Y
001
Reserved
3487
379
036
SEG[108]
1912
379
002
Reserved
3442
379
037
SEG[107]
1867
379
003
Reserved
3397
379
038
SEG[106]
1822
379
004
Reserved
3352
379
039
SEG[105]
1777
379
005
Reserved
3307
379
040
SEG[104]
1732
379
006
Reserved
3262
379
041
SEG[103]
1687
379
007
Reserved
3217
379
042
SEG[102]
1642
379
008
Reserved
3172
379
043
SEG[101]
1597
379
009
Reserved
3127
379
044
SEG[100]
1552
379
010
Reserved
3082
379
045
SEG[99]
1507
379
011
Reserved
3037
379
046
SEG[98]
1462
379
012
Reserved
2992
379
047
SEG[97]
1417
379
013
SEG[131]
2947
379
048
SEG[96]
1372
379
014
SEG[130]
2902
379
049
SEG[95]
1327
379
015
SEG[129]
2857
379
050
SEG[94]
1282
379
016
SEG[128]
2812
379
051
SEG[93]
1237
379
017
SEG[127]
2767
379
052
SEG[92]
1192
379
018
SEG[126]
2722
379
053
SEG[91]
1147
379
019
SEG[125]
2677
379
054
SEG[90]
1102
379
020
SEG[124]
2632
379
055
SEG[89]
1057
379
021
SEG[123]
2587
379
056
SEG[88]
1012
379
022
SEG[122]
2542
379
057
SEG[87]
967
379
023
SEG[121]
2497
379
058
SEG[86]
922
379
024
SEG[120]
2452
379
059
SEG[85]
877
379
025
SEG[119]
2407
379
060
SEG[84]
832
379
026
SEG[118]
2362
379
061
SEG[83]
787
379
027
SEG[117]
2317
379
062
SEG[82]
742
379
028
SEG[116]
2272
379
063
SEG[81]
697
379
029
SEG[115]
2227
379
064
SEG[80]
652
379
030
SEG[114]
2182
379
065
SEG[79]
607
379
031
SEG[113]
2137
379
066
SEG[78]
562
379
032
SEG[112]
2092
379
067
SEG[77]
517
379
033
SEG[111]
2047
379
068
SEG[76]
472
379
034
SEG[110]
2002
379
069
SEG[75]
427
379
035
SEG[109]
1957
379
070
SEG[74]
382
379
Ver 1.3
3/61
2007/09/20
ST7588T
Pad No.
Pin Name
X
Y
Pad No.
Pin Name
X
Y
071
SEG[73]
337
379
107
SEG[37]
-1283
379
072
SEG[72]
292
379
108
SEG[36]
-1328
379
073
SEG[71]
247
379
109
SEG[35]
-1373
379
074
SEG[70]
202
379
110
SEG[34]
-1418
379
075
SEG[69]
157
379
111
SEG[33]
-1463
379
076
SEG[68]
112
379
112
SEG[32]
-1508
379
077
SEG[67]
67
379
113
SEG[31]
-1553
379
078
SEG[66]
22
379
114
SEG[30]
-1598
379
079
SEG[65]
-23
379
115
SEG[29]
-1643
379
080
SEG[64]
-68
379
116
SEG[28]
-1688
379
081
SEG[63]
-113
379
117
SEG[27]
-1733
379
082
SEG[62]
-158
379
118
SEG[26]
-1778
379
083
SEG[61]
-203
379
119
SEG[25]
-1823
379
084
SEG[60]
-248
379
120
SEG[24]
-1868
379
085
SEG[59]
-293
379
121
SEG[23]
-1913
379
086
SEG[58]
-338
379
122
SEG[22]
-1958
379
087
SEG[57]
-383
379
123
SEG[21]
-2003
379
088
SEG[56]
-428
379
124
SEG[20]
-2048
379
089
SEG[55]
-473
379
125
SEG[19]
-2093
379
090
SEG[54]
-518
379
126
SEG[18]
-2138
379
091
SEG[53]
-563
379
127
SEG[17]
-2183
379
092
SEG[52]
-608
379
128
SEG[16]
-2228
379
093
SEG[51]
-653
379
129
SEG[15]
-2273
379
094
SEG[50]
-698
379
130
SEG[14]
-2318
379
095
SEG[49]
-743
379
131
SEG[13]
-2363
379
096
SEG[48]
-788
379
132
SEG[12]
-2408
379
097
SEG[47]
-833
379
133
SEG[11]
-2453
379
098
SEG[46]
-878
379
134
SEG[10]
-2498
379
099
SEG[45]
-923
379
135
SEG[9]
-2543
379
100
SEG[44]
-968
379
136
SEG[8]
-2588
379
101
SEG[43]
-1013
379
137
SEG[7]
-2633
379
102
SEG[42]
-1058
379
138
SEG[6]
-2678
379
103
SEG[41]
-1103
379
139
SEG[5]
-2723
379
104
SEG[40]
-1148
379
140
SEG[4]
-2768
379
105
SEG[39]
-1193
379
141
SEG[3]
-2813
379
106
SEG[38]
-1238
379
142
SEG[2]
-2858
379
Ver 1.3
4/61
2007/09/20
ST7588T
Pad No.
Pin Name
X
Y
Pad No.
Pin Name
X
Y
143
SEG[1]
-2903
379
179
Reserved
-3263
-379
144
SEG[0]
-2948
379
180
Reserved
-3218
-379
145
COMS1
-2993
379
181
Reserved
-3173
-379
146
COM[0]
-3038
379
182
Reserved
-3128
-379
147
COM[1]
-3083
379
183
Reserved
-3083
-379
148
COM[2]
-3128
379
184
Reserved
-3038
-379
149
COM[3]
-3173
379
185
Reserved
-2993
-379
150
COM[4]
-3218
379
186
SYNC
-2417
-389
151
COM[5]
-3263
379
187
CL
-2298
-389
152
COM[6]
-3308
379
188
DOF
-2225
-389
153
COM[7]
-3353
379
189
CSB
-2106
-389
154
COM[8]
-3398
379
190
VSS
-2033
-389
155
COM[9]
-3443
379
191
RESB
-1899
-389
156
COM[10]
-3488
379
192
A0
-1780
-389
157
COM[11]
-3743
358
193
/WR(R/W)
-1707
-389
158
COM[12]
-3743
313
194
/RD(E)
-1588
-389
159
COM[13]
-3743
268
195
D0
-1515
-389
160
COM[14]
-3743
223
196
D1
-1396
-389
161
COM[15]
-3743
178
197
D2
-1323
-389
162
COM[16]
-3743
133
198
D3
-1204
-389
163
COM[17]
-3743
88
199
D4
-1131
-389
164
COM[18]
-3743
43
200
D5
-1012
-389
165
COM[19]
-3743
-2
201
D6
-939
-389
166
COM[20]
-3743
-47
202
D7
-820
-389
167
COM[21]
-3743
-92
203
T5
-743
-389
168
COM[22]
-3743
-137
204
T4
-568
-389
169
COM[23]
-3743
-182
205
T3
-493
-389
170
Reserved
-3743
-227
206
T2
-318
-389
171
Reserved
-3743
-272
207
T1
-243
-389
172
Reserved
-3743
-317
208
T0
-93
-389
173
Reserved
-3743
-362
209
VSS
-25
-389
174
Reserved
-3488
-379
210
VSS
48
-389
175
Reserved
-3443
-379
211
VSS
121
-389
176
Reserved
-3398
-379
212
MS
223
-389
177
Reserved
-3353
-379
213
MODE0
296
-389
178
Reserved
-3308
-379
214
MODE1
415
-389
Ver 1.3
5/61
2007/09/20
ST7588T
Pad No.
Pin Name
X
Y
Pad No.
Pin Name
X
Y
215
PS0
488
-389
246
V3
2846
-389
216
PS1
607
-389
247
V4
2916
-389
217
PS2
680
-389
248
COMS2
2992
-379
218
VDD1
782
-389
249
COM[47]
3037
-379
219
VDD1
855
-389
250
COM[46]
3082
-379
220
VDD1
928
-389
251
COM[45]
3127
-379
221
VDD2
1021
-389
252
COM[44]
3172
-379
222
VDD2
1091
-389
253
COM[43]
3217
-379
223
VOUT
1161
-389
254
COM[42]
3262
-379
224
VOUT
1231
-389
255
COM[41]
3307
-379
225
VOUT
1301
-389
256
COM[40]
3352
-379
226
CAP3N
1371
-389
257
COM[39]
3397
-379
227
CAP3N
1441
-389
258
COM[38]
3442
-379
228
CAP3P
1511
-389
259
COM[37]
3487
-379
229
CAP3P
1581
-389
260
COM[36]
3743
-362
230
CAP5P
1651
-389
261
COM[35]
3743
-317
231
CAP5P
1721
-389
262
COM[34]
3743
-272
232
CAP1N
1791
-389
263
COM[33]
3743
-227
233
CAP1N
1861
-389
264
COM[32]
3743
-182
234
CAP1P
1931
-389
265
COM[31]
3743
-137
235
CAP1P
2001
-389
266
COM[30]
3743
-92
236
CAP2P
2071
-389
267
COM[29]
3743
-47
237
CAP2P
2141
-389
268
COM[28]
3743
-2
238
CAP2N
2211
-389
269
COM[27]
3743
43
239
CAP2N
2281
-389
270
COM[26]
3743
88
240
CAP4P
2351
-389
271
COM[25]
3743
133
241
CAP4P
2421
-389
272
COM[24]
3743
178
242
VRS
2491
-389
273
Reserved
3743
223
243
V0
2561
-389
274
Reserved
3743
268
244
V1
2706
-389
275
Reserved
3743
313
245
V2
2776
-389
276
Reserved
3743
358
Ver 1.3
6/61
2007/09/20
ST7588T
n PAD CENTER COORDINATES (65 duty)
Pad No.
Pin Name
X
Y
Pad No.
Pin Name
X
Y
001
COM[35]
3487
379
036
SEG[108]
1912
379
002
COM[34]
3442
379
037
SEG[107]
1867
379
003
COM[33]
3397
379
038
SEG[106]
1822
379
004
COM[32]
3352
379
039
SEG[105]
1777
379
005
Reserved
3307
379
040
SEG[104]
1732
379
006
Reserved
3262
379
041
SEG[103]
1687
379
007
Reserved
3217
379
042
SEG[102]
1642
379
008
Reserved
3172
379
043
SEG[101]
1597
379
009
Reserved
3127
379
044
SEG[100]
1552
379
010
Reserved
3082
379
045
SEG[99]
1507
379
011
Reserved
3037
379
046
SEG[98]
1462
379
012
Reserved
2992
379
047
SEG[97]
1417
379
013
SEG[131]
2947
379
048
SEG[96]
1372
379
014
SEG[130]
2902
379
049
SEG[95]
1327
379
015
SEG[129]
2857
379
050
SEG[94]
1282
379
016
SEG[128]
2812
379
051
SEG[93]
1237
379
017
SEG[127]
2767
379
052
SEG[92]
1192
379
018
SEG[126]
2722
379
053
SEG[91]
1147
379
019
SEG[125]
2677
379
054
SEG[90]
1102
379
020
SEG[124]
2632
379
055
SEG[89]
1057
379
021
SEG[123]
2587
379
056
SEG[88]
1012
379
022
SEG[122]
2542
379
057
SEG[87]
967
379
023
SEG[121]
2497
379
058
SEG[86]
922
379
024
SEG[120]
2452
379
059
SEG[85]
877
379
025
SEG[119]
2407
379
060
SEG[84]
832
379
026
SEG[118]
2362
379
061
SEG[83]
787
379
027
SEG[117]
2317
379
062
SEG[82]
742
379
028
SEG[116]
2272
379
063
SEG[81]
697
379
029
SEG[115]
2227
379
064
SEG[80]
652
379
030
SEG[114]
2182
379
065
SEG[79]
607
379
031
SEG[113]
2137
379
066
SEG[78]
562
379
032
SEG[112]
2092
379
067
SEG[77]
517
379
033
SEG[111]
2047
379
068
SEG[76]
472
379
034
SEG[110]
2002
379
069
SEG[75]
427
379
035
SEG[109]
1957
379
070
SEG[74]
382
379
Ver 1.3
7/61
2007/09/20
ST7588T
Pad No.
Pin Name
X
Y
Pad No.
Pin Name
X
Y
071
SEG[73]
337
379
107
SEG[37]
-1283
379
072
SEG[72]
292
379
108
SEG[36]
-1328
379
073
SEG[71]
247
379
109
SEG[35]
-1373
379
074
SEG[70]
202
379
110
SEG[34]
-1418
379
075
SEG[69]
157
379
111
SEG[33]
-1463
379
076
SEG[68]
112
379
112
SEG[32]
-1508
379
077
SEG[67]
67
379
113
SEG[31]
-1553
379
078
SEG[66]
22
379
114
SEG[30]
-1598
379
079
SEG[65]
-23
379
115
SEG[29]
-1643
379
080
SEG[64]
-68
379
116
SEG[28]
-1688
379
081
SEG[63]
-113
379
117
SEG[27]
-1733
379
082
SEG[62]
-158
379
118
SEG[26]
-1778
379
083
SEG[61]
-203
379
119
SEG[25]
-1823
379
084
SEG[60]
-248
379
120
SEG[24]
-1868
379
085
SEG[59]
-293
379
121
SEG[23]
-1913
379
086
SEG[58]
-338
379
122
SEG[22]
-1958
379
087
SEG[57]
-383
379
123
SEG[21]
-2003
379
088
SEG[56]
-428
379
124
SEG[20]
-2048
379
089
SEG[55]
-473
379
125
SEG[19]
-2093
379
090
SEG[54]
-518
379
126
SEG[18]
-2138
379
091
SEG[53]
-563
379
127
SEG[17]
-2183
379
092
SEG[52]
-608
379
128
SEG[16]
-2228
379
093
SEG[51]
-653
379
129
SEG[15]
-2273
379
094
SEG[50]
-698
379
130
SEG[14]
-2318
379
095
SEG[49]
-743
379
131
SEG[13]
-2363
379
096
SEG[48]
-788
379
132
SEG[12]
-2408
379
097
SEG[47]
-833
379
133
SEG[11]
-2453
379
098
SEG[46]
-878
379
134
SEG[10]
-2498
379
099
SEG[45]
-923
379
135
SEG[9]
-2543
379
100
SEG[44]
-968
379
136
SEG[8]
-2588
379
101
SEG[43]
-1013
379
137
SEG[7]
-2633
379
102
SEG[42]
-1058
379
138
SEG[6]
-2678
379
103
SEG[41]
-1103
379
139
SEG[5]
-2723
379
104
SEG[40]
-1148
379
140
SEG[4]
-2768
379
105
SEG[39]
-1193
379
141
SEG[3]
-2813
379
106
SEG[38]
-1238
379
142
SEG[2]
-2858
379
Ver 1.3
8/61
2007/09/20
ST7588T
Pad No.
Pin Name
X
Y
Pad No.
Pin Name
X
Y
143
SEG[1]
-2903
379
179
Reserved
-3263
-379
144
SEG[0]
-2948
379
180
Reserved
-3218
-379
145
COMS1
-2993
379
181
Reserved
-3173
-379
146
COM[0]
-3038
379
182
Reserved
-3128
-379
147
COM[1]
-3083
379
183
Reserved
-3083
-379
148
COM[2]
-3128
379
184
Reserved
-3038
-379
149
COM[3]
-3173
379
185
Reserved
-2993
-379
150
COM[4]
-3218
379
186
SYNC
-2417
-389
151
COM[5]
-3263
379
187
CL
-2298
-389
152
COM[6]
-3308
379
188
DOF
-2225
-389
153
COM[7]
-3353
379
189
CSB
-2106
-389
154
COM[8]
-3398
379
190
VSS
-2033
-389
155
COM[9]
-3443
379
191
RESB
-1899
-389
156
COM[10]
-3488
379
192
A0
-1780
-389
157
COM[11]
-3743
358
193
/WR(R/W)
-1707
-389
158
COM[12]
-3743
313
194
/RD(E)
-1588
-389
159
COM[13]
-3743
268
195
D0
-1515
-389
160
COM[14]
-3743
223
196
D1
-1396
-389
161
COM[15]
-3743
178
197
D2
-1323
-389
162
COM[16]
-3743
133
198
D3
-1204
-389
163
COM[17]
-3743
88
199
D4
-1131
-389
164
COM[18]
-3743
43
200
D5
-1012
-389
165
COM[19]
-3743
-2
201
D6
-939
-389
166
COM[20]
-3743
-47
202
D7
-820
-389
167
COM[21]
-3743
-92
203
T5
-743
-389
168
COM[22]
-3743
-137
204
T4
-568
-389
169
COM[23]
-3743
-182
205
T3
-493
-389
170
COM[24]
-3743
-227
206
T2
-318
-389
171
COM[25]
-3743
-272
207
T1
-243
-389
172
COM[26]
-3743
-317
208
T0
-93
-389
173
COM[27]
-3743
-362
209
VSS
-25
-389
174
COM[28]
-3488
-379
210
VSS
48
-389
175
COM[29]
-3443
-379
211
VSS
121
-389
176
COM[30]
-3398
-379
212
MS
223
-389
177
COM[31]
-3353
-379
213
MODE0
296
-389
178
Reserved
-3308
-379
214
MODE1
415
-389
Ver 1.3
9/61
2007/09/20
ST7588T
Pad No.
Pin Name
X
Y
Pad No.
Pin Name
X
Y
215
PS0
488
-389
246
V3
2846
-389
216
PS1
607
-389
247
V4
2916
-389
217
PS2
680
-389
248
COMS2
2992
-379
218
VDD1
782
-389
249
COM[63]
3037
-379
219
VDD1
855
-389
250
COM[62]
3082
-379
220
VDD1
928
-389
251
COM[61]
3127
-379
221
VDD2
1021
-389
252
COM[60]
3172
-379
222
VDD2
1091
-389
253
COM[59]
3217
-379
223
VOUT
1161
-389
254
COM[58]
3262
-379
224
VOUT
1231
-389
255
COM[57]
3307
-379
225
VOUT
1301
-389
256
COM[56]
3352
-379
226
CAP3N
1371
-389
257
COM[55]
3397
-379
227
CAP3N
1441
-389
258
COM[54]
3442
-379
228
CAP3P
1511
-389
259
COM[53]
3487
-379
229
CAP3P
1581
-389
260
COM[52]
3743
-362
230
CAP5P
1651
-389
261
COM[51]
3743
-317
231
CAP5P
1721
-389
262
COM[50]
3743
-272
232
CAP1N
1791
-389
263
COM[49]
3743
-227
233
CAP1N
1861
-389
264
COM[48]
3743
-182
234
CAP1P
1931
-389
265
COM[47]
3743
-137
235
CAP1P
2001
-389
266
COM[46]
3743
-92
236
CAP2P
2071
-389
267
COM[45]
3743
-47
237
CAP2P
2141
-389
268
COM[44]
3743
-2
238
CAP2N
2211
-389
269
COM[43]
3743
43
239
CAP2N
2281
-389
270
COM[42]
3743
88
240
CAP4P
2351
-389
271
COM[41]
3743
133
241
CAP4P
2421
-389
272
COM[40]
3743
178
242
VRS
2491
-389
273
COM[39]
3743
223
243
V0
2561
-389
274
COM[38]
3743
268
244
V1
2706
-389
275
COM[37]
3743
313
245
V2
2776
-389
276
COM[36]
3743
358
Ver 1.3
10/61
2007/09/20
ST7588T
n PAD CENTER COORDINATES (81 duty)
Pad No.
Pin Name
X
Y
Pad No.
Pin Name
X
Y
001
COM[51]
3487
379
036
SEG[108]
1912
379
002
COM[50]
3442
379
037
SEG[107]
1867
379
003
COM[49]
3397
379
038
SEG[106]
1822
379
004
COM[48]
3352
379
039
SEG[105]
1777
379
005
COM[47]
3307
379
040
SEG[104]
1732
379
006
COM[46]
3262
379
041
SEG[103]
1687
379
007
COM[45]
3217
379
042
SEG[102]
1642
379
008
COM[44]
3172
379
043
SEG[101]
1597
379
009
COM[43]
3127
379
044
SEG[100]
1552
379
010
COM[42]
3082
379
045
SEG[99]
1507
379
011
COM[41]
3037
379
046
SEG[98]
1462
379
012
COM[40]
2992
379
047
SEG[97]
1417
379
013
SEG[131]
2947
379
048
SEG[96]
1372
379
014
SEG[130]
2902
379
049
SEG[95]
1327
379
015
SEG[129]
2857
379
050
SEG[94]
1282
379
016
SEG[128]
2812
379
051
SEG[93]
1237
379
017
SEG[127]
2767
379
052
SEG[92]
1192
379
018
SEG[126]
2722
379
053
SEG[91]
1147
379
019
SEG[125]
2677
379
054
SEG[90]
1102
379
020
SEG[124]
2632
379
055
SEG[89]
1057
379
021
SEG[123]
2587
379
056
SEG[88]
1012
379
022
SEG[122]
2542
379
057
SEG[87]
967
379
023
SEG[121]
2497
379
058
SEG[86]
922
379
024
SEG[120]
2452
379
059
SEG[85]
877
379
025
SEG[119]
2407
379
060
SEG[84]
832
379
026
SEG[118]
2362
379
061
SEG[83]
787
379
027
SEG[117]
2317
379
062
SEG[82]
742
379
028
SEG[116]
2272
379
063
SEG[81]
697
379
029
SEG[115]
2227
379
064
SEG[80]
652
379
030
SEG[114]
2182
379
065
SEG[79]
607
379
031
SEG[113]
2137
379
066
SEG[78]
562
379
032
SEG[112]
2092
379
067
SEG[77]
517
379
033
SEG[111]
2047
379
068
SEG[76]
472
379
034
SEG[110]
2002
379
069
SEG[75]
427
379
035
SEG[109]
1957
379
070
SEG[74]
382
379
Ver 1.3
11/61
2007/09/20
ST7588T
Pad No.
Pin Name
X
Y
Pad No.
Pin Name
X
Y
071
SEG[73]
337
379
107
SEG[37]
-1283
379
072
SEG[72]
292
379
108
SEG[36]
-1328
379
073
SEG[71]
247
379
109
SEG[35]
-1373
379
074
SEG[70]
202
379
110
SEG[34]
-1418
379
075
SEG[69]
157
379
111
SEG[33]
-1463
379
076
SEG[68]
112
379
112
SEG[32]
-1508
379
077
SEG[67]
67
379
113
SEG[31]
-1553
379
078
SEG[66]
22
379
114
SEG[30]
-1598
379
079
SEG[65]
-23
379
115
SEG[29]
-1643
379
080
SEG[64]
-68
379
116
SEG[28]
-1688
379
081
SEG[63]
-113
379
117
SEG[27]
-1733
379
082
SEG[62]
-158
379
118
SEG[26]
-1778
379
083
SEG[61]
-203
379
119
SEG[25]
-1823
379
084
SEG[60]
-248
379
120
SEG[24]
-1868
379
085
SEG[59]
-293
379
121
SEG[23]
-1913
379
086
SEG[58]
-338
379
122
SEG[22]
-1958
379
087
SEG[57]
-383
379
123
SEG[21]
-2003
379
088
SEG[56]
-428
379
124
SEG[20]
-2048
379
089
SEG[55]
-473
379
125
SEG[19]
-2093
379
090
SEG[54]
-518
379
126
SEG[18]
-2138
379
091
SEG[53]
-563
379
127
SEG[17]
-2183
379
092
SEG[52]
-608
379
128
SEG[16]
-2228
379
093
SEG[51]
-653
379
129
SEG[15]
-2273
379
094
SEG[50]
-698
379
130
SEG[14]
-2318
379
095
SEG[49]
-743
379
131
SEG[13]
-2363
379
096
SEG[48]
-788
379
132
SEG[12]
-2408
379
097
SEG[47]
-833
379
133
SEG[11]
-2453
379
098
SEG[46]
-878
379
134
SEG[10]
-2498
379
099
SEG[45]
-923
379
135
SEG[9]
-2543
379
100
SEG[44]
-968
379
136
SEG[8]
-2588
379
101
SEG[43]
-1013
379
137
SEG[7]
-2633
379
102
SEG[42]
-1058
379
138
SEG[6]
-2678
379
103
SEG[41]
-1103
379
139
SEG[5]
-2723
379
104
SEG[40]
-1148
379
140
SEG[4]
-2768
379
105
SEG[39]
-1193
379
141
SEG[3]
-2813
379
106
SEG[38]
-1238
379
142
SEG[2]
-2858
379
Ver 1.3
12/61
2007/09/20
ST7588T
Pad No.
Pin Name
X
Y
Pad No.
Pin Name
X
Y
143
SEG[1]
-2903
379
179
COM[33]
-3263
-379
144
SEG[0]
-2948
379
180
COM[34]
-3218
-379
145
COMS1
-2993
379
181
COM[35]
-3173
-379
146
COM[0]
-3038
379
182
COM[36]
-3128
-379
147
COM[1]
-3083
379
183
COM[37]
-3083
-379
148
COM[2]
-3128
379
184
COM[38]
-3038
-379
149
COM[3]
-3173
379
185
COM[39]
-2993
-379
150
COM[4]
-3218
379
186
SYNC
-2417
-389
151
COM[5]
-3263
379
187
CL
-2298
-389
152
COM[6]
-3308
379
188
DOF
-2225
-389
153
COM[7]
-3353
379
189
CSB
-2106
-389
154
COM[8]
-3398
379
190
VSS
-2033
-389
155
COM[9]
-3443
379
191
RESB
-1899
-389
156
COM[10]
-3488
379
192
A0
-1780
-389
157
COM[11]
-3743
358
193
/WR(R/W)
-1707
-389
158
COM[12]
-3743
313
194
/RD(E)
-1588
-389
159
COM[13]
-3743
268
195
D0
-1515
-389
160
COM[14]
-3743
223
196
D1
-1396
-389
161
COM[15]
-3743
178
197
D2
-1323
-389
162
COM[16]
-3743
133
198
D3
-1204
-389
163
COM[17]
-3743
88
199
D4
-1131
-389
164
COM[18]
-3743
43
200
D5
-1012
-389
165
COM[19]
-3743
-2
201
D6
-939
-389
166
COM[20]
-3743
-47
202
D7
-820
-389
167
COM[21]
-3743
-92
203
T5
-743
-389
168
COM[22]
-3743
-137
204
T4
-568
-389
169
COM[23]
-3743
-182
205
T3
-493
-389
170
COM[24]
-3743
-227
206
T2
-318
-389
171
COM[25]
-3743
-272
207
T1
-243
-389
172
COM[26]
-3743
-317
208
T0
-93
-389
173
COM[27]
-3743
-362
209
VSS
-25
-389
174
COM[28]
-3488
-379
210
VSS
48
-389
175
COM[29]
-3443
-379
211
VSS
121
-389
176
COM[30]
-3398
-379
212
MS
223
-389
177
COM[31]
-3353
-379
213
MODE0
296
-389
178
COM[32]
-3308
-379
214
MODE1
415
-389
Ver 1.3
13/61
2007/09/20
ST7588T
Pad No.
Pin Name
X
Y
Pad No.
Pin Name
X
Y
215
PS0
488
-389
251
COM[77]
3127
-379
216
PS1
607
-389
252
COM[76]
3172
-379
217
PS2
680
-389
253
COM[75]
3217
-379
218
VDD1
782
-389
254
COM[74]
3262
-379
219
VDD1
855
-389
255
COM[73]
3307
-379
220
VDD1
928
-389
256
COM[72]
3352
-379
221
VDD2
1021
-389
257
COM[71]
3397
-379
222
VDD2
1091
-389
258
COM[70]
3442
-379
223
VOUT
1161
-389
259
COM[69]
3487
-379
224
VOUT
1231
-389
260
COM[68]
3743
-362
225
VOUT
1301
-389
261
COM[67]
3743
-317
226
CAP3N
1371
-389
262
COM[66]
3743
-272
227
CAP3N
1441
-389
263
COM[65]
3743
-227
228
CAP3P
1511
-389
264
COM[64]
3743
-182
229
CAP3P
1581
-389
265
COM[63]
3743
-137
230
CAP5P
1651
-389
266
COM[62]
3743
-92
231
CAP5P
1721
-389
267
COM[61]
3743
-47
232
CAP1N
1791
-389
268
COM[60]
3743
-2
233
CAP1N
1861
-389
269
COM[59]
3743
43
234
CAP1P
1931
-389
270
COM[58]
3743
88
235
CAP1P
2001
-389
271
COM[57]
3743
133
236
CAP2P
2071
-389
272
COM[56]
3743
178
237
CAP2P
2141
-389
273
COM[55]
3743
223
238
CAP2N
2211
-389
274
COM[54]
3743
268
239
CAP2N
2281
-389
275
COM[53]
3743
313
240
CAP4P
2351
-389
276
COM[52]
3743
358
241
CAP4P
2421
-389
242
VRS
2491
-389
243
V0
2561
-389
244
V1
2706
-389
245
V2
2776
-389
246
V3
2846
-389
247
V4
2916
-389
248
COMS2
2992
-379
249
COM[79]
3037
-379
250
COM[78]
3082
-379
Ver 1.3
14/61
2007/09/20
ST7588T
n BLOCK DIAGRAM
Figure 1
Ver 1.3
Block diagram
15/61
2007/09/20
ST7588T
n PIN DESCRIPTIONS
LCD driver outputs
Pin Name
Type
Description
No. of Pins
LCD segment driver outputs
The display data and frame signal control the output voltage of segment driver.
SEG0 to
SEG131
Segment Driver Output
Normal Display Reverse Display
Display data
Frame
1
1
Negative
Positive
V0
VSS
V2
V3
0
0
Negative
Positive
V2
V3
V0
VSS
VSS
VSS
O
Display OFF,
Power save mode
132
LCD column driver outputs
The scan signal and frame signal control the output voltage of common driver.
COM0 to
COM79
Display data
Frame
Common Driver Output
Normal Display Reverse Display
1
1
Negative
Positive
VSS
V0
0
0
Negative
Positive
V1
V4
O
Display OFF,
Power save mode
COMS1
COMS2
O
80
VSS
Common output for the icons. COMS1 and COMS2 are identical.
The output signals of these pins are same. If not using, they should be left open.
2
MICROPROCESSOR INTERFACE
Pin Name
Type
Description
No. of Pins
Microprocessor interface selection pins
Interface Mode
PS2 PS1 PS0
PS[2:0]
I
0
1
0
0
0
0
8-bit 8080 parallel interface
8-bit 6800 parallel interface
0
1
1
1
0
0
4-line serial interface A mode
4-line serial interface B mode
0
1
0
0
1
1
3-line (8 bit) serial interface A mode
3-line (8-bit) serial interface B mode
0
1
1
1
1
1
3-line (9-bit) serial interface
I2C serial interface
3
CSB
I
Chip select input pin
Microprocessor Interface is enabled only when CSB is "L".
When chip select is non-active (CSB=“H”), D[7:0] are high impedance.
CSB is not used in I2C interface. Fix this pin to “H” by VDD1.
RESB
I
Reset input pin
When RESB is “L”, initialization is executed.
1
I
It determines whether the data bits are data or a command.
A0= “H” : Indicates that D[7:0] are display data.
A0= “L” : Indicates that D[7:0] are control data.
A0 is not used in 3-line SPI or I2C interface. Fix this pin to “H” by VDD1.
1
A0
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ST7588T
Pin Name
Type
Description
No. of Pins
Read/Write execution control pin : (when PS[1:0]=L,L)
Description
PS2 MPU type /WR(R/W)
H
/WR(R/W)
6800-series
R/W
Read/Write control input pin.
R/W=“H”: read
R/W=“L”: write
/WR
Write enable clock input pin.
The data on D0 to D7 are latched at the rising
edge of the /WR signal.
I
L
8080-series
1
This pin is not used in the serial interface. Fix to “H” by VDD1.
/RD (E)
I
Read/Write execution control pin : (when PS[1:0]=L,L)
PS2 MPU Type
/RD (E)
Description
Enable control input pin.
R/W=“H”: When E is “H”, D0 to D7 are in an
H
6800-series
E
output status.
R/W=“L”: The data on D0 to D7 are latched at the
falling edge of the E signal.
Read enable clock input pin
L
8080-series
/RD
When /RD is “L”, D0 to D7 are in an output
status.
1
This pin is not used in the serial interface. Fix to “H” by VDD1.
When using parallel interface: 8-bit interface
This is an 8-bit bi-directional data bus that connected to the standard 8-bit
microprocessor data bus.
When chip select pin (CSB) is not active, D7 to D0 are high impedance.
D[7:0]
I/O
When using serial interface: 3-line or 4-line
D0: serial input clock (SCL).
D1 to D3: serial input data (SDA).
D4, D5, D6, D7: fix to “H” by VDD1.
When chip select pin (CSB) is not active, D7 to D0 are high impedance.
2
When using I C interface (PS[2:0]="H")
D0: SCL, serial clock input.
D1: SDA_IN, serial input data.
2
D2 to D5: SDA_OUT, serial data acknowledge for the I C interface.
D6 and D7 are slave address bit 0 and 1 which can be set as 00 to 11.
D1 to D5 must be connected together (SDA)
Chip select pin (CSB) is not used and must be fixed to “H” by VDD1.
8
2
By connecting SDA_OUT to SDA_IN externally, the SDA line becomes fully I C
interface compatible. Separating acknowledge output from the serial data input is
advantageous for chip-on-glass (COG) applications. In COG applications, the ITO
resistance and the pull-up resistor will form a voltage divider which affects
acknowledge-signal level. Larger ITO resistance will raise the acknowledge-signal
level and system cannot recognize this level as a valid logical “0” level. By splitting
SDA_IN from SDA_OUT, the IC can be used in a mode which ignores the
acknowledge-bit. For applications that check the acknowledge-bit, it is important to
minimize the ITO resistance of the SDA_OUT trace to guarantee a valid low level.
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Pin Name
Type
Description
No. of Pins
Use this pin can select 1/49 duty, 1/65duty or 1/81 duty mode
Mode0
Duty
Mode1
MODE[1:0]
I
0
0
0
1
1/49 duty
1/65 duty
1
1
0
1
--1/81 duty
1
Power Supply Pins
Pin Name
VSS
VDD1
VDD2
VOUT
Type
Description
Power Ground.
Digital Supply Voltage.
Power The 2 supply rails VDD1 and VDD2 could be connected together.
If Digital Option pin is high, must be this level.
Analog Supply Voltage.
The 2 supply rails VDD1 and VDD2 could be connected together.
If using external voltage generator, the external supply voltage should connect to
Power VOUT pad as an external voltage input.
VOUT must series one capacitor to VDD2.
Power
V0,
This is a multi-level power supply for the liquid crystal operation.
Power
V1, V2, V3, V4
VOUT ≥ V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
Voltage Regulator reference level.
VRS
Power
This pin must be left open.
No. of Pins
9
5
4
3
5
1
Test Pin
Pin Name
Type
T0~T5
MS
Test
I
SYNC
/DOF
CL
O
Ver 1.3
Description
No. of Pins
These pins are reserved for test only.
Please fix this pin to “H” by VDD1.
6
1
Please let these pads floating.
1
1
1
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ST7588T
ITO Limitations
PIN Name
ITO Resistance
T0~5, SYNC, /DOF, CL
VDD1, VDD2, VSS, VOUT
V0, V1, V2, V3, V4, CAP1P, CAP1N, CAP2P, CAP2N , CAP3P, CAP3N, CAP4P, CAP5P
2
Floating
<100Ω
<200Ω
D[5:1] (if using I C interface mode)
CSB, E, R/W, A0, D[7:0]
<300Ω
<1KΩ
PS[2:0], MODE[1:0], MS
RESB
< 5KΩ
<10KΩ
Note:
1.
The option setting to be “H” should connect to VDD1.
2.
The option setting to be “L” should connect to VSS1.
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n FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
CSB pin is used as chip-select input. ST7588T can interface with an MPU when CSB is "L". When CSB is “H”, the pins of A0,
/RD (E), and /WR(R/W) with any combination will be ignored and D[7:0] are high impedance. In 3-line and 4-line serial
interfaces, the internal shift-register and bit-counter are reset when CSB is “H”.
Interface Selection
ST7588T has eight types of interface for all kinds of MPU (6 kinds of serial interface and 2 kinds of parallel interface). The
selection among these interfaces uses PS[2:0] pins as shown in Table 1.
Table 1
Type
PS2
Parallel
Serial
Parallel / Serial Interface Mode
PS1
PS0
Interface mode
0
0
0
8bit 8080-series MPU mode
1
0
0
8 bit 6800-series MPU mode
0
1
0
4-line serial interface A mode
1
1
0
4-line serial interface B mode
0
1
0
0
1
1
3-line (8 bit) serial interface A mode
3-line (8-bit) serial interface B mode
0
1
1
1
1
1
3-line (9-bit) serial interface
2
I C serial interface
Parallel Interface
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS0 as shown in Table 2. The
type of data transfer is determined by signals at A0, /RD (E) and /WR(R/W) as shown in Table 3.
Table 2
Microprocessor Selection for Parallel Interface
PS2
CSB
A0
E_RD
RW_WR
DB0 to DB7
MPU bus
H
L
CSB
CSB
A0
A0
E
/RD
RW
/WR
DB0 to DB7
DB0 to DB7
6800-series
8080-series
Table 3
Common
6800-series
Parallel Data Transfer
8080-series
Description
E_RD
RW_WR
E_RD
RW_WR
(E)
(RW)
(/RD)
(/WR)
H
H
H
L
H
Display data read out
H
L
H
H
L
H
H
L
L
H
Display data write
Register status read
L
H
L
H
L
Writes to internal register (instruction)
A0
NOTE: In 6800-series interface mode, fixing E_RD pin at “H” can use CSB as enable signal instead. In this case, the
interface data is latched at the rising edge of CSB and the access type of this transfer is determined by signals at A0 and
RW_WR as defined in 6800-series mode.
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Serial Interface
4-Line SPI
When the ST7588T is active (CSB=”L”), serial data (DB1~3) and serial clock (DB0) inputs are enabled. While not active, the
internal 8-bit shift register and the 3-bit counter are reset. The display data/command indication may be controlled either by
software or the Register Select (A0) Pin. When the A0 pin is used, data is display data when A0 is high and is command data
when A0 is low. When A0 is not used, the LCD Driver will receive command from MCU by default. If messages on the data
pin are data rather than command, MCU should send Data Direction command (11101000) to control the data direction and
then one more command to define the number of data bytes will be write. After these two continuous commands are sent, the
following messages will be data rather than command. Serial data can be read on the rising edge of serial clock going into
DB6 and processed as 8-bit parallel data on the eighth serial clock. And the DDRAM column address pointer will be
increased by one automatically. The next bytes after the display data string is handled as command data.
(1) 4-Line SPI A Mode (PS0 = "L", PS1 = "H", PS2 = "L")
Figure 2
4-Line SPI Timing
(2) 4-Line SPI B Mode (PS0 = "L", PS1 = "H", PS2 = "H")
Figure 3
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3-Line SPI
(1) 3-Line (8 bit) SPI
In this mode, the default transfer type is command. Two kinds of parameters must be set before write data: start addresses
and data length. The flow to write data is: (1) Set start addresses, (2) Set data length and (3) Transfer data. Each bit is
latched at the rising edge of SCL. The column address pointer is automatically increased by 1 after receiving 1 byte data.
1
Instruction
Set Page Address
Set Column Address (H)
0
1
1
1
2
Set Column Address (L)
Set No. of Data Bytes (H)
Set No. of Data Bytes (M)
1
0
0
1
1
1
Flow
3
Flow
Ver 1.3
1
1
1
0
1
0
Y1
X5
X2
X1
X3
0
DA10 DA9
DA7 DA6 DA5
Set No. of Data Bytes (L) & Start
0
1
0
1
DA3 DA2
Transfer Data bytes
Figure 4 3-line (8 bit) SPI A mode Timing (A0 is not used)
Y0
X4
X0
DA8
DA4
DA1
DA0
1
1
0
1
1
1
1
1
1
1
1
0
0
Set No. of Data Bytes (L) & Start
DA0 DA1 DA2 DA3
1
0
Transfer Data bytes
Figure 5 3-line (8 bit) SPI B mode Timing (A0 is not used)
1
0
1
Instruction
Set Page Address
Set Column Address (H)
Y0
X4
2
Set Column Address (L)
Set No. of Data Bytes (H)
Set No. of Data Bytes (M)
X0
DA8
DA4
3
Bit Order (Left --> Right)
0
0
Y3
Y2
1
1
X7
X6
Y1
X5
Bit Order (Left --> Right)
Y2
Y3
0
0
X6
X7
1
1
X1
X2
X3
DA9 DA10
0
DA5 DA6 DA7
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ST7588T
“Set No. of Data Bytes” is used in this mode only. It must be 3 continuous instructions with valid data length which informs
ST7588T the following n-bytes transfers are display data. After receiving these 3 instructions, the following transfers will be
treated as display data until the data length counter is cleared. If data is halted during transmitting, it is not valid data. New
data will be transferred serially with most significant bit first.
NOTE: In spite of transmission of data, if CSB is disabled, state stops abnormally. Next state is initialized.
(2) 3-Line (9-bit) SPI
This mode uses the first bit to indicate the following 8 bits are data or instruction.
Figure 6
3-line SPI (9-bit) Timing
I2C Interface
2
2
The I C interface receives and executes the commands sent via the I C Interface. It also receives display data and sends it to
2
the DDRAM. The I C Interface uses two-line to communicate between different ICs or modules. The two lines are a Serial
Data line (SDA) and a Serial Clock line (SCL). Both lines must be connected with a pull-up resistor which drives SDA and
2
SCLK to high when the bus is not busy. Data transfer may be initiated only when the bus is not busy. The I C interface of
ST7588T supports write access and checking acknowledge-bit.
(1) BIT TRANSFER
One data bit is transferred during each clock pulse. Data on the SDA line must remain stable during the HIGH period of the
clock pulse, because changes on SDA at this moment will be interpreted as START or STOP. Please refer to Figure 8.
(2) START AND STOP CONDITIONS
Both SDA and SCLK lines remain HIGH when the bus is ready. A HIGH-to-LOW transition on SDA, while SCLK is HIGH, is
defined as the START condition (S). A LOW-to-HIGH transition on SDA, while SCLK is HIGH, is defined as the STOP
condition (P). Please refer to Figure 9.
(3) SYSTEM CONFIGURATION
The system configuration is illustrated in Figure 10. A short glossary is listed below:
Ø
Transmitter: the device that sends the data to the bus.
Ø
Receiver: the device that receives the data from the bus.
Ø
Master: the device which initiates a transfer, generates clock signals and terminates the transfer.
Ø
Slave: the device which is addressed by a master.
Ø
Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message.
Ø
Arbitration: procedure to ensure that, if more than one master tries to control the bus simultaneously, only one is
allowed to do so and the message is not corrupted.
Ø
Synchronization: procedure to synchronize the clock signals of two or more devices.
(4) ACKNOWLEDGE
Each byte of eight bits is followed by an acknowledge-bit. The transmitter generates an extra acknowledge-related clock
pulse to check the acknowledge-bit. To receive the acknowledge-bit, the transmitter set the SCLK at LOW and put a HIGH
signal on SDA. The device that acknowledges must pull-down SDA (acknowledgement) during the acknowledgement clock
pulse. The transmitter will check SDA for the acknowledgement. Acknowledge-bit on SDA must be stable LOW during the
HIGH period of the acknowledgement clock pulse (set-up and hold times must be taken into consideration). A slave receiver
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2
which is addressed must generate an acknowledge-bit after the reception of each byte. Acknowledgement on the I C
Interface is illustrated in Figure 7.
Figure 7
2
Acknowledgement of the I C Interface
Figure 8
Figure 9
Bit transfer
Definition of START and STOP conditions
Figure 10 System configuration
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2
(5) I C Interface protocol
2
The ST7588T supports command/data write addressed slaves on the bus. Before any data is transmitted on the I C Interface,
the device, which should respond, is addressed first. Four 7-bit slave addresses (011100, 011101, 011110, and 011111) are
reserved for the ST7588T. The least significant 2 bits of the slave address is set by connecting SA1 and SA0 to either logic 0
2
(VSS) or logic 1 (VDD1). The I C Interface protocol is illustrated in Figure 11.
A transfer is initiated with a START condition (S) set by the master and followed by the slave address. All slaves with the
corresponding address acknowledge in parallel, all the others will ignore this transfer. After acknowledgement, one or more
command words follow which define the status of the addressed slaves. A command word consists of a control byte, which
defines Co and A0, plus a data byte.
The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co=0). After a control byte with a
cleared Co bit, only data bytes will follow. The A0 bit indicates the following data byte is a command or a display data. All
addressed slaves on the bus also acknowledge the control and data bytes. The last control byte is followed by either series
data bytes with display data or series data bytes with commands (depends on A0 bit). If A0 bit in the last control byte is set to
logic 1, these data bytes are display data bytes and will be stored in DDRAM. The data pointer is automatically updated after
each display data byte. If A0 bit in the last control byte is set to logic 0, these data bytes are commands and will be decoded
A0
Co
Co=0
A0
Co=1
A0
SA1
SA0
R/W
Co
R/W
A0
SA1
SA0
to execute the receiving instructions. The master issues a STOP condition (P) at the end of the transmission.
Figure 11 2-line Interface protocol
Co
0
1
Ver 1.3
Last control byte to be sent. Only a stream of data bytes is allowed to follow.
This stream may only be terminated by STOP or RE-START condition.
Another control byte will follow the data byte unless a STOP or RE-START condition is received.
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ST7588T
Data Transfer
The ST7588T uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to
on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in Figure 12. Moreover, when
reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and
the MPU reads this stored data from bus holder for the next data read cycle as shown in Figure 13. This means that a dummy
read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the
data of the specified address cannot be output with the read display data instruction right after the address sets, but can be
output at the second read of data.
MPU signal
A0
/WR
D0 to D7
N
D(N)
D(N+1) D(N+2)
D(N+3)
N
D(N)
D(N+1)
D(N+2)
D(N+3)
N
N+1
N+2
N+3
Internal signals
/WR
BUS HOLDER
COLUMN ADDRESS
Figure 12 Write Timing
MPU signal
A0
/WR
/RD
D0 to D7
Dummy
N
D(N)
D(N+1)
Internal signals
/WR
/RD
BUS HOLDER
COLUMN ADDRESS
N
N
D(N)
D(N+1) D(N+2)
D(N)
D(N+1) D(N+2)
Figure 13 Read Timing
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ST7588T
DISPLAY DATA RAM (DDRAM)
The ST7588T contains an 81X132 bit static RAM that stores the display data. The display data RAM store the dot data for the
LCD. It has an 81(10 pageX8 bit +1 pageX1 bit) X 132. There is a direct correspondence between X-address and column
output number. It is 81-row by 132-column addressable array. Each pixel can be selected when the page and column
addresses are specified.
Page Address Circuit
This circuit is for providing a Page Address to Display Data RAM. It incorporates 4-bit Page Address register changed by only
the “Set Page” instruction. Page Address 11 is a special RAM area for the icons and display data D0 is only valid.
Line Address Circuit
This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line
Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip
RAM. It incorporates 7-bit Line Address register changed by only the initial display line instruction and 7-bit counter circuit. At
the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and
generates the line address for transferring the 132-bit RAM data to the display data latch circuit. When icon is selected by
setting icon page address, display data of icons are not scrolled because the MPU cannot access Line Address of icons.
Column Address Circuit
Column Address Circuit has an 8-bit preset counter that provides Column Address to the Display Data RAM as shown in
Figure 14. The display data RAM column address is specified by the Column Address Set command. The specified column
address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed
continuously.
Register MX and MY selection instruction makes it possible to invert the relationship between the Column Address and the
segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing MX select instruction. Refer to the
following Figure 15.
SEG Output
Segment Pads
MX
SEG0
SEG131
“0”
Seg0
“1”
Seg131 ß Segment Address ß
à Segment Address à Seg131
Seg0
COM Output
MY
Common Pads
COM0
COM79
COMS
“0”
Com0
à Common Address à Com79 à
COMS
“1”
Com79 ß Common Address ß
Com0 à
COMS
Data is downloaded in bytes into the RAM matrix of ST7588T as indicated in Figs.14, 15, 16. The display RAM has a matrix
of 81 by 132 bits. The address pointer addresses the columns. The address range is: X=0~131 (10000011); Y=0~10 (1010).
Addresses out of this range are not allowed.
In horizontal addressing mode, the X address increments after each access (see Figure 16). After reaching the last X
address (X = 131), X address wraps around to 0 and Y address increases to address the next row.
After the very last address (X = 131, Y = 10) the address pointers wrap around to address (X = 0, Y =0)
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Data structure
Figure 14 RAM format and addressing, if DO=0
0
1
0
1
2
3
4
2
132 133 134
264 265 266
396 397 398
528 529 530
1188 1189 1190
1319
0
Y-address
Figure 15 RAM format and addressing, if DO=1
9
10
131
X-address
Figure 16 Sequence of writing data bytes into RAM with horizontal addressing
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ST7588T
LCD DRIVER CIRCUIT
This driver circuit is configured by 81-channel common drivers and 132-channel segment drivers. This LCD panel driver
voltage depends on the combination of display data and M (Frame Indicator) signal.
COM0
M
VDD
VSS
COM0
V0
V1
V2
V3
V4
VSS
COM1
V0
V1
V2
V3
V4
VSS
COM2
V0
V1
V2
V3
V4
VSS
SEG0
V0
V1
V2
V3
V4
VSS
SEG1
V0
V1
V2
V3
V4
VSS
COM0
to
SEG0
V0
V1
V2
V3
V4
VSS
-V4
-V3
-V2
-V1
-V0
COM0
to
SEG1
V0
V1
V2
V3
V4
VSS
-V4
-V3
-V2
-V1
-V0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
SEG 0
1
2
3
4
Figure 17 LCD Driver output waveform
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REFERENCE BOOSTER CIRCUIT EXAMPLE
ST7588T
ST7588T
ST7588T
ST7588T
ST7588T
Figure 18 Booster Configuration
Notes:
1.
C1 = 1uF ~ 4.7uF. Please take care about the “Voltage Rating” of the capacitor.
2.
VOUT should not exceed the Absolutely Maximum Rating.
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RESET CIRCUIT
Setting RESB to “L” or Reset instruction can initialize internal function.
When RESB becomes “L”, the following procedure is entered.
Page address: 0
Column address: 0
Display control: Display blank
COM Scan Direction MY: 0
SEG Select Direction MX: 0
DO=0
Oscillator: OFF
N-line inversion register: 0 (disable)
Power down mode (PD = 1)
Normal instruction set (H[1:0] = 00)
Display blank (E = D = 0)
Address counter X [7:0] = 0, Y [3:0] = 0
Bias system (BS [2:0] = 010)
V0 is equal to 0; the HV generator is switched off (VOP [6:0] = 0)
After power-on, RAM data are undefined
While RESB is “L” or reset instruction is executed, no instruction except read status can be accepted. Reset status appears
at DB0. After DB0 becoming “L”, any instruction can be accepted. RESB must be connected to the reset pin of the MPU, and
initialize the MPU and this LSI at the same time. The initialization by RESB is essential before used.
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Partial Display on LCD
The ST7588T realizes the Partial Display function on LCD with low-duty driving for saving power consumption and showing
the various display duty. To show the various display duty on LCD, LCD driving duty and bias are programmable via the
instruction. Moreover, built-in power supply circuits are controlled by the instruction for adjusting the LCD driving voltages.
Figure 20 Reference Example for Partial Display
Figure 21 Partial Display (Partial Display Duty=16, initial COM0=0)
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Figure 22 Moving Display (Partial Display Duty=16, Initial COM0=8)
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ST7588T
n INSTRUCTION TABLE
INSTRUCTION
A0
R/W
(WR)
COMMAND BYTE
D4
D3
D2
DESCRIPTION
D7
D6
D5
H independent instruction
Write data
1
0
D7
D6
D5
D4
D3
Read data
Read status byte
1
0
1
1
D7
PD
D6
0
D5
V
D4
D
Function Set
0
0
0
0
1
MX
A0
R/W
(WR)
D7
D6
H[1:0]=[0:0]
Set V0 (VOP) range 0
0
0
0
0
0
0
1
0
END
Read/modify/write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
Display control
SI3-8bit data
(L)&start
0
0
0
0
0
0
1
D
0
E
0
0
0
1
0
1
DA3
DA2
DA1
SI3-8bit data (M)
0
0
0
1
1
0
DA7
DA6
DA5
SI3-8bit data (H)
0
0
0
1
1
1
0
DA10
DA9
Set Y address
0
0
0
1
0
0
Y3
Y2
Y1
Y0
Set Y address of RAM
0≦Y≦9
Set X Address (L)
0
0
1
1
1
0
X3
X2
X1
X0
Set X address of RAM,
Low-bit. 0≦X≦131
Set X Address (H)
0
0
1
1
1
1
X7
X6
X5
X4
Set X address of RAM,
High-bit. 0≦X≦131
Display
configuration
0
0
0
0
0
0
1
DO
0
V
Top/bottom row mode set data
order
Bias system
Set V0 (VOP)
0
0
0
0
0
1
0
VOP6
0
VOP5
1
VOP4
0
VOP3
BS2
VOP2
BS1
VOP1
A0
R/W
(WR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
1
0
PS
Partial Display
0
Set Partial Display
0
part
0
0
0
0
0
1
0
0
0
0
0
0
1
DP3
DP2
DP1
Set Start line
0
0
1
S6
S5
S4
S3
S2
S1
S0
H[1:0]=[1:1]
RESET
0
0
0
0
0
0
0
0
1
1
High Power Mode
Frame
0
0
0
0
1
0
0
0
1
0
1
0
0
1
HP
FR2
0
FR1
0
High Power Mode SET
FR0 Frame rate control
N line inversion
0
0
0
1
0
NL4
NL3
NL2
NL1
NL0 Sets N line inversion
INSTRUCTION
D1
D0
D2
D1
D0
Write data to RAM
D3
E
D2
MX
D1
MY
D0
DO
Read data to RAM
Read status byte
MY
PD
H1
H0
Mirror X, Mirror Y, Power
Down, Extended table
COMMAND BYTE
D5
D4
D3
D2
D1
D0
DESCRIPTION
PRS V0 (VOP) range L/H select
Release read/modify/write
RAM address at R:+0 , W:+1
Sets display configuration
Set the number of data bytes,
DA0
Low-bit (8 bit 3-line SPI)
Set the number of data bytes,
DA4
Middle-bit (8 bit 3-line SPI)
Set the number of data bytes,
DA8
High-bit (8 bit 3-line SPI)
H[1:0]=[0:1]
INSTRUCTION
BS0 Sets bias system (BSx)
VOP0 Write V0 (VOP) to register
COMMAND BYTE
DESCRIPTION
H[1:0]=[1:0]
Set Partial screen
0
mode
Ver 1.3
34/61
PS=1: Enable Partial screen
mode.
WS Set partial screen size
Set display area for partial
DP0
screen mode
Specify the initial display line to
realize vertical scrolling
Software reset
2007/09/20
ST7588T
n INSTRUCTION DESCRIPTION
H[1:0] independent
Write data
8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and
page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to
the addressed page. During auto-increment, the column address wraps to 0 after the last column is written.
D7
D6
D5
D4
D3
D2
D1
D0
A0
WR(R/W)
0
0
Write data
Read data
8-bit data of Display Data from the RAM location specified by the column address and page address can be read to the
microprocessor.
A0
1
WR(R/W)
1
D7
D6
D5
D4
D3
Read data
D2
D1
D0
D5
D4
D3
D2
D1
D0
V
D
E
MX
MY
DO
D3
MY
D2
PD
D1
H1
D0
H0
Read status byte
Indicates the internal status of the ST7588T
D7
D6
A0
WR(R/W)
0
Flag
PD
V
D,E
MX
1
PD
0
Description
PD=0:chip is active
PD=1:chip is in power down mode
When V = 0, the horizontal addressing is selected.
When V = 1, the vertical addressing is selected.
D
0
E The bits D and E select the display mode.
0 Display OFF
0
1
1 All display segments on
0 Normal mode
1 1 Inverse video mode
SEG bi-direction selection
MY=0:normal direction (SEG0(SEG131)
MY=1:reverse direction (SEG131(SEG0)
MY
COM bi-direction selection
MY=0:normal direction (COM0(COM79)
MY=1:reverse direction (COM79(COM0)
DO
DO=0:MSB is on top
DO=1:LSB is on top
Function Set
A0
0
WR(R/W)
0
D7
0
D6
0
D5
1
Flag
MX
MY
PD
H0, H1
Ver 1.3
D4
MX
Description
SEG bi-direction selection
MY=0:normal direction (SEG0àSEG131); MY=1:reverse direction (SEG131àSEG0)
COM bi-direction selection
MY=0:normal direction (COM0àCOM79); MY=1:reverse direction (COM79àCOM0)
PD=0:chip is active; PD=1:chip is in power down mode
All LCD outputs at VSS (display off), bias generator and VOUT generator off, V0 can be
disconnected, oscillator off (external clock possible), RAM contents not cleared; RAM data
can be written.
Selection of Extended Command Table
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ST7588T
H[1:0]=[0:0]
Set V0 (VOP) range
V0 (VOP) range L/H select
D7
A0
WR(R/W)
D6
0
0
0
0
PRS=0: V0 (VOP) programming range LOW
PRS=1: V0 (VOP) programming range HIGH
D5
D4
D3
D2
D1
D0
0
0
0
1
0
PRS
END
This command releases the read/modify/write mode, and returns the column and row address to the address it was at when
the mode was entered.
A0
WR(R/W)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
1
1
0
Read/modify/write
This command is used coupled with the “END” command. Once this command has been input, the display data read
command does not change the column and row address, but only the display data write command increments (+1) the
address depend on V register setting. This mode is kept until the END command is input. When the END command is input,
the address returns to the address it was at when the read/modify/write command was entered. This function makes it
possible to reduce the load on the MPU when there are repeating data changes in a specified display region, such as when
there is a blanking cursor.
A0
0
WR(R/W)
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
1
D1
1
D0
1
* Even in read/modify/write mode, other commands aside from display data read/write commands can also be used.
Ver 1.3
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ST7588T
Display Control
This bits D and E selects the display mode.
A0
WR(R/W)
D7
D6
0
0
0
0
D5
0
Flag
D,E
D4
0
D3
1
D2
D
D1
0
D0
E
Description
D
0
E The bits D and E select the display mode.
0 Display OFF
1
0
0 Normal display
1 All display segments on
1
1 Inverse video mode
Set SI3-8 bit Data
Display Data Length resister
This command is used in 8-bit 3-line SPI only. When A0 is not used, the Display Data Length instruction is used to indicate
the specified number of display data byte to be transmitted. The next byte after the display data string is handled as data.
0
WR
(R/W)
0
0
1
0
1
DA3
DA2
DA1
DA0
SPI3-8bit Data(L) & Start
0
0
0
0
0
0
1
1
1
1
0
1
DA7
0
DA6
DA10
DA5
DA9
DA4
DA8
SPI3-8bit Data(M)
SPI3-8bit Data(H)
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
Display Data Length
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
2
0
:
0
:
0
:
0
:
0
:
0
:
0
:
0
:
0
:
1
:
0
:
3
:
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
1
1
0
1317
1318
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
1
1
0
1
0
1
0
1319
1320
A0
D7
D6
D5
D4
D3
D2
D1
D0
Description
Set Y address of RAM
Y [3:0] defines the Y address vector address of the display RAM.
A0
0
WR(R/W)
0
D7
0
D6
1
D5
0
D4
0
D3
Y3
D2
Y2
D1
Y1
Y3
Y2
Y1
Y0
CONTENT
ALLOWED X-RANGE
0
0
0
0
0
0
0
1
Page0 (display RAM)
Page1 (display RAM)
0 to 131
0 to 131
0
0
0
0
1
1
0
1
Page2 (display RAM)
Page3 (display RAM)
0 to 131
0 to 131
0
0
1
1
0
0
0
1
Page4 (display RAM)
Page5 (display RAM)
0 to 131
0 to 131
0
0
1
1
1
1
0
1
Page6 (display RAM)
Page7 (display RAM)
0 to 131
0 to 131
1
1
0
0
0
0
0
1
Page8 (display RAM)
Page9 (display RAM)
0 to 131
0 to 131
Ver 1.3
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D0
Y0
2007/09/20
ST7588T
Set X address of RAM
The X address points to the columns. The range of X is 0…131.
WR
A0
D7
D6
D5
(R/W)
Set X Address (Low)
Set X address (High)
0
0
0
0
1
1
1
1
1
1
D4
D3
D2
D1
D0
0
1
X3
X7
X2
X6
X1
X5
X0
X4
X7
X6
X5
X4
X3
X2
X1
X0
Column address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
2
3
:
1
:
0
:
0
:
0
:
0
:
0
:
0
:
0
:
128
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
129
130
1
0
0
0
0
0
1
1
131
H[1:0]=[0:1]
Display configuration
Top/bottom row mode set data order and the direction of Address.
A0
WR(R/W)
D7
D6
D5
D4
D3
0
0
Flag
DO
V
0
0
0
0
1
D2
D1
D0
DO
0
V
D2
BS2
D1
BS1
D0
BS0
Description
DO=0:MSB is on top
DO=1:LSB is on top
When V = 0, the horizontal addressing is selected.
When V = 1, the vertical addressing is selected.
System Bias
Select LCD bias ratio of the voltage required for driving the LCD.
A0
WR(R/W)
D7
D6
D5
D4
D3
0
0
0
0
0
1
0
BS2
BS1
BS0
Bias
0
0
0
0
0
1
11
10
0
0
1
1
0
1
9
8
1
1
0
0
0
1
7
6
1
1
1
1
0
1
5
4
LCD bias voltage
Ver 1.3
Symbol
Bias voltage for 1/9 bias
Symbol
Bias voltage for 1/9 bias
V0
V1
V0
8/9 X V0
V3
V4
2/9 X V0
1/9 X V0
V2
7/9 X V0
VSS
VSS
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ST7588T
Set V0 (VOP) value:
A0
0
WR(R/W)
0
D7
1
D6
VOP6
D5
VOP5
D4
VOP4
D3
VOP3
D2
VOP2
D1
VOP1
D0
VOP0
The operation voltage V0 (VOP) can be set by software.
V0 = VOP = ( a + VOP × b )
(1)
The parameters are described in table 4.The maximum voltage that can be generated is depending on the VDD1 voltage and
the display load current. Two overlapping V0 (VOP) ranges are selectable via the command “Booster control”. For the LOW
(PRS=0) range a=a1 and for the HIGH (PRS=1) range a=a2 with steps equal to “b” in both ranges. Note that the charge
pump is turned off if VOP [6;0] and the bit PRS are all set to zero.
Table 4
SYMBOL
a1
VALUE
3.528(PRS=0)
UNIT
V
a2
b
8.862(PRS=1)
0.042
V
V
Typical values for parameter for the HV-Generator programming
V0
Charge pump off
b
00
a2
a1+b
01
02
03
04
05
06
.....
7D
7E
7F
00
01
02
Lower Range (PRS=0)
03
04
05
06
.....
7D
7E
7F
Higher Range (PRS=1)
VOP [6:0] (0x00~0x7F}
Figure 23 V0 (VOP) programming of ST7588T
* Recommended LCD VOP voltage is 9.5V~10.5V (1/10 Bias).
H[1:0]=[1:0]
Partial screen mode
A0
0
Flag
PS
Ver 1.3
WR(R/W)
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
1
D1
0
D0
PS
Description
Full display mode or partial screen mode selection.
PS=0:Full display mode with MUX 1:80.
PS=1:Partial screen mode with MUX 1:16 or MUX 1:32.
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ST7588T
Partial screen size
This instruction controls partial screen size, partial screen 16 rows when WS is low and partial screen 32 rows when WS is
high.
D7
D6
D5
D4
D3
D2
D1
D0
A0
WR(R/W)
0
0
0
0
0
0
1
0
0
WS
Display part
This instruction can select partial screen display area.
A0
WR(R/W)
D7
D6
D5
0
0
0
0
0
D4
D3
D2
D1
D0
1
DP3
DP2
DP1
DP0
(1) 1/16 Duty
Flag
Status
DP3 DP2 DP1
DP0
Description
0
0
0
0
RAM bank 0 to 1 (row0~row15)
0
0
0
0
0
1
1
0
RAM bank 1 to 2 (row8~row23)
RAM bank 2 to 3 (row16~row31)
0
0
0
1
1
0
1
0
RAM bank 3 to 4 (row24~row39)
RAM bank 4 to 5 (row32~row47)
0
0
1
1
0
1
1
0
RAM bank 5 to 6 (row40~row55)
RAM bank 6 to 7 (row48~row63)
0
1
1
0
1
0
1
0
RAM bank 7 to 8 (row56~row71)
RAM bank 8 to 9 (row64~row79)
1
0
0
1
RAM bank 9 (row72~row79)
(2) 1/32 Duty
Flag
Status
DP3 DP2 DP1
DP0
Description
0
0
0
0
RAM bank 0 to 3 (row0~row31)
0
0
0
0
0
1
1
0
RAM bank 1 to 4 (row8~row39)
RAM bank 2 to 5 (row16~row47)
0
0
0
1
1
0
1
0
RAM bank 3 to 6 (row24~row55)
RAM bank 4 to 7 (row32~row63)
0
0
1
1
0
1
1
0
RAM bank 5 to 8 (row40~row71)
RAM bank 6 to 9 (row48~row79)
0
1
1
0
1
0
1
0
RAM bank 7 to 9 (row56~row79)
RAM bank 8 to 9 (row64~row79)
1
0
0
1
RAM bank 9 (row72~row79)
Set start line
Sets the line address of display RAM to determine the initial display line instruction. The RAM display data is displayed at the
top of row (COM0) of LCD panel.
A0
0
WR(R/W)
0
D7
1
D6
S6
D5
S5
D4
S4
D3
S3
D2
S2
D1
S1
D0
S0
S6
S5
S4
S3
S2
S1
S0
Line address
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
2
3
:
1
:
0
:
0
:
1
:
1
:
0
:
1
:
77
1
1
0
0
0
0
1
1
1
1
1
1
0
1
78
79
Note: when 81 duty is selected, 4f (1001111) is MAX;
when 65 duty is selected, 3f (0111111) is MAX;
when 49 duty is selected, 2f (0101111) is MAX
Ver 1.3
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ST7588T
H[1:0]=[1:1]
Reset
This instruction resets initial display line, column address, page address, and common output status select to their initial
status .This instruction cannot initialize the LCD power supply, which is initialized by the RESB pin.
A0
0
WR(R/W)
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
1
D0
1
High Power Mode
This command is to enter the high power mode. HP=1: high power mode, HP=0: normal mode.
A0
WR(R/W)
D7
D6
D5
D4
D3
D2
D1
0
0
D0
1
0
1
1
0
HP
0
0
D7
0
D6
0
D5
0
D4
0
D3
1
D2
FR2
D1
FR1
D0
FR0
Frame frequency
A0
0
WR(R/W)
0
This command is used to set the frame frequency.
FR2
0
FR1
0
FR0
0
Frame frequency
50 Hz
0
0
0
1
1
0
68 Hz
70 Hz
0
1
1
0
1
0
73 Hz
75 Hz
1
1
0
1
1
0
78 Hz
81 Hz
1
1
1
150 Hz
Set N-line inversion
Sets the inverted line number within range of 3 to 33 to improve the display quality by controlling the phase of the internal
LCD AC signal (M)
Note: The N-line inversion mode will be disabled when partial display mode enter. After the partial display mode end, the
N-line inversion mode will return as it was.
A0
WR(R/W)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
0
NL4
NL3
NL2
NL1
NL0
NL4
0
NL3
0
NL2
0
NL1
0
NL0
0
Selected n-line inversion
Frame inversion
0
0
0
0
0
0
0
1
1
0
3-line inversion
4-line inversion
0
:
0
:
0
:
1
:
1
:
5-line inversion
:
1
1
1
1
1
1
0
1
1
0
31-line inversion
32-line inversion
1
1
1
1
1
33-line inversion
Ver 1.3
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ST7588T
n COMMAND DESCRIPTION
Referential Instruction Setup Flow: Initializing with the built-in Power Supply Circuits
Figure 24 Initializing with the Built-in Power Supply Circuits
Referential Instruction Flow for Power Down:
Function set PD=0, H1=0, H0=1
Set V0 (VOP)=0
Function set PD=0, H1=0, H0=0
Set PRS=0
Function set PD=0, H1=1, H0=1
Write Command #10100001B
[command for discharge]
Function set PD=1, H1=1, H0=1
[Power Down Mode]
Delay 250ms
Write Command #10100000B
[discharge process finished]
Power Down Mode Entered
Figure 25 Instruction Flow for Power Down
Ver 1.3
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ST7588T
n ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System; see notes 1 and 2.
Parameter
Symbol
Conditions
Unit
Digital Power Supply Voltage
VDD1
–0.3 ~ 3.6
V
Analog Power supply voltage
VDD2
–0.3 ~ 3.6
V
VOUT, V0
–0.5 ~ +13.5
V
V1, V2, V3, V4
0.3 to V0
V
Input voltage
VIN
–0.5 to VDD+0.5
V
Output voltage
VO
–0.5 to VDD+0.5
V
Operating temperature
TOPR
–30 to +85
°C
Storage temperature
TSTR
–65 to +150
°C
LCD Operation Power supply voltage
LCD Driving Power supply voltage
Notes
1.
Stresses above those listed under Limiting Values may cause permanent damage to the device.
2.
Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to
VSS unless otherwise noted.
3.
Insure that the voltage levels of V1, V2, V3, and V4 are always such that
4.
Recommended LCD VOP voltage is 9.5V~10.5V (1/10 Bias).
VOUT ≧ V0 ≧ V1 ≧ V2 ≧ V3 ≧ V4 ≧ Vss
Ver 1.3
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ST7588T
n DC CHARACTERISTICS
VSS = 0V; Tamb = -30℃ to +85℃; unless otherwise specified.
Item
Symbol
Condition
Rating
Min.
Typ.
Max.
Units
Applicable
Pin
Operating Voltage (1)
VDD1
1.8
--
3.3
V
VDD1
Operating Voltage (2)
VDD2
2.4
--
3.3
V
VDD2
High-level Input Voltage
VIHC
0.7 x VDD1
--
VDD1
V
Low-level Input Voltage
VILC
VSS
--
0.3 x VDD1
V
High-level Output Voltage
VOHC
IOH=1mA
0.8 x VDD1
--
VDD1
V
Low-level Output Voltage
VOLC
IOL=1mA
VSS
--
0.2 x VDD1
V
VIN = VDD1 or VSS
-1.0
--
1.0
μA
--
0.8
1.1
kΩ
--
50
--
kHz
--
75
--
Hz
Input leakage current
Liquid
Crystal
Driver
ILI
ON
Resistance
Internal
Oscillator
Oscillator
Frequency
Frame
Frequency
Item
Internal
Voltage Step-up
Power
Circuit output
RON
Ta = 25°C
V0 =
(relative to VSS)
11.0 V
fOSC
SEGn
COMn
*1
1/81 duty
fFRAME
Symbol
Condition
VOUT
(Relative To VSS)
Rating
Min.
Typ.
Max.
--
--
13.5
Units
V
Applicable
Pin
VSS, *2
* Recommended LCD VOP voltage is 9.5V~10.5V (1/10 Bias).
Dynamic Consumption Current: During Display, with the Internal Power Supply OFF Current consumed by total ICs when an
external power supply is used.
Test pattern
Symbol
Display Pattern SNOW
ISS
Power Down
ISS
Condition
VDD = 3.0 V,
V0 – VSS = 10.0 V
Ta = 25°C
Min.
Rating
Typ.
Max.
--
120
--
0.05
Units
Notes
--
μA
*3
2
μA
*4
Notes to the DC characteristics:
1.
Internal clock
2.
The maximum possible VOUT voltage that may be generated is dependent on voltage, temperature and (display) load.
3.
If external V0 used, the display load current is not transmitted to I DD.
4.
Power-down mode. During power down, all static currents are switched off.
Ver 1.3
44/61
2007/09/20
ST7588T
n TIMING CHARACTERISTICS
System Bus Read/Write Characteristics (For the 8080 Series MPU)
Figure 26
(VDD = 3.3V, Ta = –30 to 85 °C)
Item
Signal
Address hold time
Address setup time
A0
System cycle time
Write L pulse width
Write H pulse width
Read L pulse width
Read H pulse width
/WR
/RD
Data setup time (Write)
Data hold time (Write)
Data access time (Read)
D[7:0]
Output disable time (Read)
Ver 1.3
45/61
Symbol
Condition
Rating
Min.
Max.
tAH8
20
--
tAW8
20
--
tCYC8
80
--
tCCLW
70
--
tCCHW
30
--
tCCLR
90
--
tCCHR
30
--
tDS6
80
--
tDH6
20
--
tACC6
CL = 100 pF
--
50
tOH6
CL = 100 pF
10
30
Units
ns
2007/09/20
ST7588T
(VDD = 2.7V, Ta = –30 to 85 °C)
Item
Signal
Address hold time
A0
Address setup time
System cycle time
Write L pulse width
/WR
Write H pulse width
Read L pulse width
/RD
Read H pulse width
Data setup time (Write)
Data hold time (Write)
Data access time (Read)
D[7:0]
Output disable time (Read)
Symbol
Rating
Condition
Min.
Max.
tAH8
20
--
tAW8
20
--
tCYC8
90
--
tCCLW
80
--
tCCHW
30
--
tCCLR
110
--
tCCHR
30
--
tDS6
90
--
tDH6
20
--
tACC6
CL = 100 pF
--
60
tOH6
CL = 100 pF
10
40
Units
ns
(VDD = 1.8V, Ta = –30 to 85 °C)
Item
Signal
Symbol
Condition
Rating
Min.
Max.
tAH8
20
--
tAW8
20
--
tCYC8
220
--
tCCLW
200
--
tCCHW
30
--
tCCLR
220
--
tCCHR
30
--
Data setup time (Write)
tDS6
220
--
Data hold time (Write)
tDH6
20
--
Address hold time
Address setup time
A0
System cycle time
Write L pulse width
Write H pulse width
Read L pulse width
Read H pulse width
Data access time (Read)
/WR
/RD
D[7:0]
Output disable time (Read)
tACC6
CL = 100 pF
--
100
tOH6
CL = 100 pF
10
30
Units
ns
1.
The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
2.
All timing is specified using 20% and 80% of VDD as the reference.
3.
tCCLW and tCCLR are specified as the overlap between CSB being “L” and WR and RD being at the “L” level.
(tr +tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.
Ver 1.3
46/61
2007/09/20
ST7588T
System Bus Read/Write Characteristics (For the 6800 Series MPU)
Figure 27
(VDD = 3.3V, Ta = –30 to 85 °C)
Item
Signal
Symbol
Condition
Rating
Min.
Max.
tAH6
20
--
tAW6
60
--
tCYC6
100
--
tEWLW
30
--
tEWHW
40
--
tEWLR
30
--
tEWHR
40
--
WRITE Data setup time
tDS6
70
--
WRITE Data hold time
tDH6
20
--
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
READ access time
WR
RD
D0 to D7
READ Output disable time
Ver 1.3
47/61
tACC6
CL = 100 pF
--
70
tOH6
CL = 100 pF
10
40
Units
ns
2007/09/20
ST7588T
(VDD = 2.7V, Ta = –30 to 85 °C)
Item
Signal
Address hold time
A0
Address setup time
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WR
RD
WRITE Data setup time
WRITE Data hold time
D0 to D7
READ access time
READ Output disable time
Symbol
Rating
Condition
Min.
Max.
tAH6
20
--
tAW6
70
--
tCYC6
140
--
tEWLW
30
--
tEWHW
40
--
tEWLR
30
--
tEWHR
40
--
tDS6
90
--
tDH6
20
--
tACC6
CL = 100 pF
--
80
tOH6
CL = 100 pF
10
40
Units
ns
(VDD = 1.8V, Ta = –30 to 85 °C)
Item
Signal
Symbol
Condition
Rating
Min.
Max.
tAH6
20
--
tAW6
80
--
tCYC6
270
--
tEWLW
40
--
tEWHW
60
--
tEWLR
40
--
tEWHR
70
--
WRITE Data setup time
tDS6
210
--
WRITE Data hold time
tDH6
20
--
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
READ access time
WR
RD
D0 to D7
READ Output disable time
tACC6
CL = 100 pF
--
80
tOH6
CL = 100 pF
10
40
Units
ns
1.
The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
2.
All timing is specified using 20% and 80% of VDD as the reference.
3.
tCCLW and tCCLR are specified as the overlap between CSB being “L” and WR and RD being at the “L” level.
(tr +tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.
Ver 1.3
48/61
2007/09/20
ST7588T
2
SERIAL INTERFACE (I C Interface)
Figure 28
(VDD = 3.3V, Ta = –30 to 85 °C)
Item
Signal
Symbol
SCL clock frequency
SCL
SCL clock low period
Condition
Rating
Min.
Max.
fSCLK
DC
400
SCL
tLOW
150
--
SCL clock high period
SCL
tHIGH
100
--
Data set-up time
SDA
tSU;Dat
90
--
Data hold time
SDA
tHD;Dat
40
--
Setup time for a repeated START condition
SDA
tSU;STA
70
--
Start condition hold time
SDA
tHD;STA
170
--
tSU;STO
90
--
tBUF
70
--
Setup time for STOP condition
BUS free time between a STOP and START condition
SCL
Units
kHz
ns
(VDD = 2.7V, Ta = –30 to 85 °C)
Item
SCL clock frequency
Signal
Symbol
SCL
Condition
Rating
Min.
Max.
fSCLK
DC
400
SCL clock low period
SCL
tLOW
190
--
SCL clock high period
SCL
tHIGH
110
--
Data set-up time
SDA
tSU;Dat
110
--
Data hold time
SDA
tHD;Dat
30
--
Setup time for a repeated START condition
SDA
tSU;STA
90
--
Start condition hold time
SDA
tHD;STA
220
--
tSU;STO
110
--
tBUF
90
--
Setup time for STOP condition
BUS free time between a STOP and START condition
SCL
Ver 1.3
49/61
Units
kHz
ns
2007/09/20
ST7588T
SERIAL INTERFACE (4-Line Interface)
First bit
Last bit
Figure 29
(VDD = 3.3V, Ta = –30 to 85 °C)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
A0
Address hold time
Data setup time
SDA
Data hold time
CS-SCL time
CSB
CS-SCL time
Symbol
Condition
Rating
Min.
Max.
tSCYC
100
--
tSHW
60
--
tSLW
60
--
tSAS
20
--
tSAH
80
--
tSDS
20
--
tSDH
20
--
tCSS
30
--
tCSH
120
--
Units
ns
(VDD = 2.7V, Ta = –30 to 85 °C)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
CS-SCL time
Ver 1.3
A0
SDA
CSB
50/61
Symbol
Condition
Rating
Min.
Max.
tSCYC
120
--
tSHW
70
--
tSLW
70
--
tSAS
20
--
tSAH
100
--
tSDS
20
--
tSDH
20
--
tCSS
30
--
tCSH
150
--
Units
ns
2007/09/20
ST7588T
(VDD = 1.8V, Ta = –30 to 85 °C)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
CS-SCL time
A0
SDA
CSB
Symbol
Max.
tSCYC
330
--
tSHW
150
--
tSLW
150
--
tSAS
20
--
tSAH
160
--
tSDS
40
--
tSDH
40
--
tCSS
40
--
tCSH
370
--
The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
2.
All timing is specified using 20% and 80% of VDD as the standard.
51/61
Rating
Min.
1.
Ver 1.3
Condition
Units
ns
2007/09/20
ST7588T
SERIAL INTERFACE (3-Line Interface)
First bit
Last bit
Figure 30
(VDD = 3.3V, Ta = –30 to 85 °C)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Data setup time
SDA
Data hold time
CS-SCL time
CSB
CS-SCL time
Symbol
Condition
Rating
Min.
Max.
tSCYC
100
--
tSHW
60
--
tSLW
60
--
tSDS
20
--
tSDH
20
--
tCSS
30
--
tCSH
120
--
Units
ns
(VDD = 2.7V, Ta = –30 to 85 °C)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Data setup time
Data hold time
CS-SCL time
CS-SCL time
Ver 1.3
SDA
CSB
52/61
Symbol
Condition
Rating
Min.
Max.
tSCYC
120
--
tSHW
70
--
tSLW
70
--
tSDS
20
--
tSDH
20
--
tCSS
30
--
tCSH
150
--
Units
ns
2007/09/20
ST7588T
(VDD = 1.8V, Ta = –30 to 85 °C)
Item
Signal
Symbol
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Data setup time
SDA
Data hold time
CS-SCL time
CSB
CS-SCL time
Rating
Condition
Min.
Max.
tSCYC
330
--
tSHW
150
--
tSLW
150
--
tSDS
40
--
tSDH
40
--
tCSS
40
--
tCSH
370
--
1.
The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
2.
All timing is specified using 20% and 80% of VDD as the standard.
Units
ns
n RESET TIMING
tRW
RESB
tR
Internal
Status
During Reset ...
Reset Finished
Figure 31
(VDD = 3.3V, Ta = –30 to 85 °C)
Item
Signal
Reset time
Reset “L” pulse width
/RES
Symbol
Condition
Rating
Min.
Typ.
Max.
tR
--
--
400
tRW
1200
--
--
Units
ns
(VDD = 2.7V, Ta = –30 to 85 °C)
Item
Signal
Reset time
Reset “L” pulse width
/RES
Symbol
Condition
Rating
Min.
Typ.
Max.
tR
--
--
350
tRW
1600
--
--
Units
ns
(VDD = 1.8V, Ta = –30 to 85 °C)
Item
Signal
Reset time
Reset “L” pulse width
Ver 1.3
/RES
Symbol
Condition
Rating
Min.
Typ.
Max.
tR
--
--
140
tRW
4500
--
--
53/61
Units
ns
2007/09/20
ST7588T
n THE MPU INTERFACE (REFERENCE EXAMPLES)
ST7588T can be connected to either 80X86 Series MPU or to 6800 Series MPU.
(1) 8080 Series MPU
VDD
MPU
A0
A1 to A7
IORQ
A0
CSB
Decoder
DO to D7
RD
WR
RES
GND
RESET
VDD
PS2
PS1
PS0
D0 to D7
/RD (E)
/WR (R/W)
/RES
VSS
ST7588T
VCC
VSS
(2) 6800 Series MPU
VDD
MPU
A0
A1 to A7
IORQ
A0
Decoder
CSB
DO to D7
RD
WR
RES
GND
VDD
PS0
PS1
PS2
RESET
D0 to D7
E (/RD)
R/W (/WR)
/RES
VSS
ST7588T
VCC
VSS
(3) Using the Serial Interface (4-line interface A mode)
VDD
VCC
A0
CSB
Decoder
VDD
PS0
PS1
PS2
Port 1
Port 2
RES
GND
ST7588T
MPU
A1 to A7
A0
SDA
SCL
/RES
RESET
VSS
VSS
Ver 1.3
54/61
2007/09/20
ST7588T
(4) Using the Serial Interface (4-line interface B mode)
VDD
VCC
A0
CSB
Decoder
VDD
PS2
PS1
PS0
Port 1
Port 2
RES
GND
ST7588T
MPU
A1 to A7
A0
SDA
SCL
/RES
VSS
RESET
VSS
(5) Using the Serial Interface (3-line interface 8 bit A mode)
VDD
VCC
CSB
Decoder
Port 1
Port 2
RES
GND
ST7588T
MPU
A1 to A7
VDD
PS2
PS1
PS0
SDA
SCL
/RES
VSS
RESET
VSS
(6) Using the Serial Interface (3-line interface 8 bit B mode)
VDD
VCC
CSB
Decoder
Port 1
Port 2
RES
GND
ST7588T
MPU
A1 to A7
VDD
PS0
PS1
PS2
SDA
SCL
/RES
VSS
RESET
VSS
Ver 1.3
55/61
2007/09/20
ST7588T
(7) Using the Serial Interface (3-line interface 9 bit)
VDD
VCC
CSB
Decoder
Port 1
Port 2
RES
GND
ST7588T
MPU
A1 to A7
VDD
PS2
PS1
PS0
SDA
SCL
/RES
VSS
RESET
VSS
2
(8) Using the Serial Interface (I C interface)
VDD
VDD
PS0
PS1
PS2
Port 1
Port 2
RES
ST7588T
MPU
VCC
SDA
SCL
/RES
RESET
GND
VSS
VSS
Ver 1.3
56/61
2007/09/20
ST7588T
n APPLICATION CIRCUITS
For the 6800 interface & 32 duty (partial display)
~
COM37
COM39
COMS2
V4
V3
V2
V1
V0
VRS
CAP4P
CAP4P
CAP2N
CAP2N
CAP2P
CAP2P
CAP1P
CAP1P
CAP1N
CAP1N
CAP5P
CAP5P
CAP3P
CAP3P
CAP3N
CAP3N
VOUT
VOUT
VOUT
VDD2
VDD2
VDD
VDD
VDD
PS2
PS1
PS0
MODE1
MODE0
MS
VSS
VSS
VSS
T0
T1
T2
T3
T4
T5
D7
D6
D5
D4
D3
D2
D1
D0
/RD(E)
/WR(R/W)
A0
RESB
VSS
CSB
DOF
CL
SYNC
SEG131
SEG0
COMS1
COM8
COM10
~
Ver 1.3
57/61
2007/09/20
ST7588T
For the 4-line A interface & 65 duty
Ver 1.3
58/61
2007/09/20
ST7588T
For the 3-line 9 bit interface & 49 duty
~
COM37
COM47
COMS2
V4
V3
V2
V1
V0
VRS
CAP4P
CAP4P
CAP2N
CAP2N
CAP2P
CAP2P
CAP1P
CAP1P
CAP1N
CAP1N
CAP5P
CAP5P
CAP3P
CAP3P
CAP3N
CAP3N
VOUT
VOUT
VOUT
VDD2
VDD2
VDD
VDD
VDD
PS2
PS1
PS0
MODE1
MODE0
MS
VSS
VSS
VSS
T0
T1
T2
T3
T4
T5
D7
D6
D5
D4
D3
D2
D1
D0
/RD(E)
/WR(R/W)
A0
RESB
VSS
CSB
DOF
CL
SYNC
SEG131
SEG0
COMS1
COM0
COM10
~
Ver 1.3
59/61
2007/09/20
ST7588T
2
For the I C interface & 81 duty
2
In I C application, be awarded that the impedance of SDAs and GNDs should be treated as the POWER PIN.
~
COM51
COM69
COM79
COMS2
V4
V3
V2
V1
V0
VRS
CAP4P
CAP4P
CAP2N
CAP2N
CAP2P
CAP2P
CAP1P
CAP1P
CAP1N
CAP1N
CAP5P
CAP5P
CAP3P
CAP3P
CAP3N
CAP3N
VOUT
VOUT
VOUT
VDD2
VDD2
VDD
VDD
VDD
PS2
PS1
PS0
MODE1
MODE0
MS
VSS
VSS
VSS
T0
T1
T2
T3
T4
T5
D7
D6
D5
D4
D3
D2
D1
D0
/RD(E)
/WR(R/W)
A0
RESB
VSS
CSB
DOF
CL
SYNC
COM39
COM40
SEG131
SEG0
COMS1
COM0
COM10
COM28
~
Ver 1.3
60/61
2007/09/20
ST7588T
n REVERSION HISTORY
Version
Data
1.0
2005/08/01
1.1
2005/11/11
1.2
2005/12/22
1.2a
2005/12/29
1.3
2007/09/20
Ver 1.3
Description
1.
2.
Remove “Preliminary”.
2
Update I C SCL clock frequency.
1.
2.
3.
4.
1.
Chip thickness.
Redraw some figures.
Bias default value BS[2:0]=010.
Update VDD2 range.
Remove History before V1.0.
1.
1.
2.
Add voltage endurance warning to Booster Connection.
Fix description mistake.
Remove Master-Slave related sections. Master-Slave function is reserved for special
specification by customer.
Redraw timing figures.
2
Remove I C timing at 1.8V.
Fix Power Save flow mistake.
3.
4.
5.
61/61
2007/09/20