AMSCO AS8201

Austria Mikro Systeme International AG
AS8201
TTP/C-C1 Communications
Controller
Data Sheet
TTP/C-C1 Communications Controller Data Sheet
AS8201
Austria Mikro Systeme International AG
Key Features
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First dedicated controller supporting TTP/C (time triggered protocol class C)
Device for building up TTP/C nodes in a TTP/C local area networks (clusters).
Suited for dependable distributed real-time systems with guaranteed response time
application examples:
automotive: braking, steering, vehicle dynamics control, drive train control
industry: air plane flap control, rail way points
Bit data rate 2 Mbits/s @ clock 20 MHz, 5.0V
Fabricated in 0.6u CMOS process, automotive temperature range of -40 to 125deg C
1k x 16 RAM message, status and control area
RAM for instruction code and configuration data
16 bit non-multiplexed host CPU interface
16 bit RISC architecture
external firmware (FLASH memory) conforming the TTP/C specification
automatic booting after power on
software tools, design-in support, development boards available ( http://www.tttech.com)
120 pin PQFP Package
Description
The TTP/C-C1 communications controller is the first integrated device supporting serial
communication according to the TTP/C specification (time triggered protocol class C). It
performs all communications tasks such as reception and transmission of messages in a
TTP/C cluster without interaction of the host CPU.
TTP/C provides mechanisms that allow the deployment in high-dependability distributed realtime systems. It provides the following services:
• predictable transmission of messages with minimal jitter
• fault-tolerant distributed clock synchronisation
• consistent membership service with small delay
• masking of single faults
Host
processor
Interface
Quarz or
Oscillator
Boot ROM
Interface
RAM_DATA[15:0]
RAM_ADDRESS[10:0]
RAM_CEB
RAM_OEB
RAM_WEB
RAM_READYB
TIME_OVERFLOW
TIME_SIGNAL
TIME_TICK
MICROTICK
XENA0
XIN0
XOUT0
RESETB
ROM_ADDRESS[16:0]
ROM_DATA[15:0]
ROM_RESETB
ROM_CEB
ROM_OEB
ROM_WEB
ROM_READY
Controller
network
interface
(CNI)
TTP/C-C1
protocol
processor core
Reset &
Time
base
Instruction
memory
Receiver
RXD[1:0]
Bus
guardian
BDE[1:0]
XENA1
XIN1
XOUT1
Transmitter
TXD[1:0]
CTS[1:0]
OE[1:0]
Network
configuration
memory
(MEDL)
TTP/C
bus Meadia
Drivers
TEST_SE Test
FTEST
InterFTEST_IEN face
LED[7:0]
Figure 1 Block Diagramm
Rev. NC, October 1999
Page 2 of 13
TTP/C-C1 Communications Controller Data Sheet
AS8201
Austria Mikro Systeme International AG
The CNI (controller network interface) forms a temporal firewall. It decouples the controller
network from the host subsystem by use of a dual ported RAM. This prevents the propagation
of control errors. The interface to the host CPU is implemented as 16 bit wide non-multiplexed
asynchronous bus interface.
TTP/C follows a conflict-free media access strategy called time-division-multiple access
(TDMA). This means, TTP/C deploys a time slot technique based on a global time which is
permanently synchronised. Each node is assigned a time slot in which it is allowed to perform
transmit operation. The sequence of time slots is called TDMA round, a set of TDMA rounds
forms a cluster cycle. After one cluster cycle the operation of the network repeats. The
sequence of interactions forming the cluster cycle is defined in a static time schedule, called
message-descriptor-list (MEDL). The definition of the MEDL in conjunction with the global time
determines the response time for a service request.
The membership of all nodes in the network is evaluated by the communication controller. This
information is presented in a consistent fashion to all correct cluster members. During
operation, the status of every other node is propagated within one TDMA round. The MEDL is
loaded into the configuration memory before run time when the system starts up.
Package and Pin Assignment
Type: PQFP 120, plastic quad flat package
TTP/C-C1
Communications
Controller
(TOP VIEW)
Figure 1 PQFP 120 pin package and pin assignment
Rev. NC, October 1999
Page 3 of 13
TTP/C-C1 Communications Controller Data Sheet
AS8201
Austria Mikro Systeme International AG
Pin Description
PinNr.
1
2
3-18
19
20
21
22
23
24
25
26
27
28
29
30
31
Pin Name
VDD
VSS
RAM_DATA[0:15]
VDD
VSS
RAM_OEB
RAM_WEB
RAM_READYB
TIME_OVERFLOW
TIME_SIGNAL
TIME_TICK
MICROTICK
XENA0
VDD
VSS
XIN0
Dir
P
P
I/O
P
P
I
I
O
O
O
O
O
I
P
P
A
32
XOUT0
A
33
34
35
36
37
38
39
40
VSS
VDD
OE[0]
RXD[0]
TXD[0]
CTS[0]
BDE[0]
RESETB
P
P
I
IPU
O
O
O
I
41
42
43
44-50
TEST_SE
FTEST
FTEST_IEN
LED[0:6]
IPD
IPD
IPD
O
51
52
53
54
55
56
57
58
59
OE[1]
RXD[1]
TXD[1]
CTS[1]
BDE[1]
XENA1
VDD
VSS
XIN1
I
IPU
O
O
O
I
P
P
A
60
XOUT1
A
61
62
VSS
VDD
P
P
Rev. NC, October 1999
Description
positive power supply
negative power supply
DPRAM data bus, tristate
positive power supply
negative power supply
DPRAM output enable, active low
DPRAM write enable, active low
DPRAM ready, active low, indicates read/write operation finished
CNI control signal, overflow of global time
CNI control signal, CNI time signal
CNI clock signal, macrotick, typically about 1us at 20 MHz clock.
output of main clock, inverted to signal applied at pin XOUT0.
oscillator 0 (main clock) enable, active low.
positive power supply
negative power supply
analog pad from oscillator / use as input when providing external
clock
analog pad from oscillator / leave open when providing external
clock
positive power supply
negative power supply
channel [0]: transmitter output enable
channel [0]: receiver input
channel [0]: transmit data
channel [0]: transmitter clear to send
channel [0]: bus driver enable
(1) main reset input signal, active low. When connected the internal power-on reset function is overridden
(2) if unconnected: an internal reset is generated after power-on.
Reset pulse duration typically 24 us.
test input: scan enable, active high
test input: functional test mode, active high
test input: instruction insertion enable, active high
test outputs:
(1) in production test used as scan chain outputs
(2) in operation: can be used as generic output port, e.g. to drive
LEDs
channel [1]: transmitter output enable
channel [1]: receiver input
channel [1]: transmit data
channel [1]: transmitter clear to send
channel [1]: bus driver enable
oscillator 1 (bus guardian) enable, active low.
positive power supply
negative power supply
analog pad from oscillator / use as input when providing external
clock
analog pad from oscillator / leave open when providing external
clock
positive power supply
negative power supply
Page 4 of 13
TTP/C-C1 Communications Controller Data Sheet
AS8201
Austria Mikro Systeme International AG
63-79
80
81
82
83
84
ROM_ADDRESS[0:16]
ROM_RESETB
ROM_CEB
ROM_OEB
ROM_WEB
ROM_READY
85
86
87-94
95
96
97104
105
106
107117
118
119
120
VDD
VSS
ROM_DATA[0:7]
VDD
VSS
ROM_DATA[8:15]
ROM address bus, range = 2^17 = 128k
ROM reset line, active low
ROM chip enable, active low
ROM output enable, active low
ROM write enable, active low; “read” if high.
ROM ready, signals read operation ready, leave open when unused
P positive power supply
P negative power supply
I/O ROM data bus (lower byte)
P positive power supply
P negative power supply
I/O ROM data bus (higher byte)
VDD
VSS
RAM_ADDRESS[0:10]
P
P
I
positive power supply
negative power supply
DPRAM address bus, range = 2^11 = 2048
RAM_CEB
VDD
VSS
I
P
P
DPRAM chip enable, active low
positive power supply
negative power supply
I
IPU
IPD
O
I/O
P
A
O
O
O
O
O
IPU
Input CMOS
Input CMOS with pull up
Input CMOS with pull down
Output CMOS
Input/Output CMOS tristate
Power Pin
Analog Pin
Electrical Specifications
Absolute Maximum Ratings ( Non Operating)
SYMBOL
VDD
Vin
Iin
Tstrg
PARAMETER
DC Supply Voltage
Input Voltage on any Pin
Input Current on any Pin
Storage Temperature
Tsold
Soldering Temperature
tsold
H
ESD
Soldering Time
Humidity
Electrostatic Discharge
MIN
-0.3 V
- 0.3 V
-100 mA
-55 oC
5%
1000 V
MAX
7.0 V
VDD + 0.3 V
100 mA
150 oC
NOTE
260 oC
10 sec
85 %
1)
25°C
Reflow and Wave
HBM: R = 1.5 kΩ , C = 100 pF
1) 300 oC all ceramic packages and DIL plastic packages, 260 oC for surface mounting plastic packages
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may effect device reliability (e.g. hot carrier degradation).
Rev. NC, October 1999
Page 5 of 13
TTP/C-C1 Communications Controller Data Sheet
AS8201
Austria Mikro Systeme International AG
Recommended Operating Conditions
PARAMETER
DC Supply Voltage
Circuit Ground
Static Supply Current
Operating Supply
Current
Main clock frequency
Bus Guardian clock
frequency
Ambient Temperature
SYMBOL
VDD
VSS
IDDS
IDD
MIN
4.5 V
0.0 V
-------
CLK
CLK2
Ta
TYP
5.0 V
0.0 V
40 µA
110 mA
MAX
5.5 V
0.0 V
100 µA
160 mA
NOTE
5 MHz
4 MHz
20 MHz
16 MHz
oscillator pins XIN0, XOUT0
oscillatpr pins XIN1, XOUT1
-40 oC
+125 oC
1)
1)
2)
fCLK = 20 MHz, VDD = 5.5 V 3)
1) The input and output parameter values in this table are directly related to ambient temperature and DC supply
voltage. A temperature range other Tamin to Tamax or a supply voltage range other than VDDmin to VDDmax will
affect these values and must be evaluated extra.
2) Static supply current IDDS is exclusive of input/output drive requirements and is measured at maximum VDD
with the clocks stopped and all inputs tied to VDD or VSS, configured to draw minimum current.
3) Operating current is exclusive of input/output drive requirements and is measured at maximum VDD and maximum clock frequency 20 MHz.
DC Characteristics and Voltage Levels
CMOS I/O levels for specified voltage and temperature range unless otherwise noted.
Inputs Pins
Pin Name
All inputs and IO pins
(except: ROM_READY,
RXD[0], RXD[1], FTEST,
FTEST_IEN, TEST_SE)
ROM_READY, RXD[0],
RXD[1]
FTEST, FTEST_IEN,
TEST_SE
Vil
max
30%
VDD
Vih
min
70%
VDD
Iil (1)
min
NA
30%
VDD
30%
VDD
70%
VDD
70%
VDD
-50
µA
NA
max
-1.0
µA
-160
µA
NA
Iih(2)
min
NA
NOTE
max
1.0
µA
NA
NA
30
µA
160
µA
CMOS input (3)
CMOS with pull
up (3)
CMOS with pull
down (3)
Notes:
1) Iil ist tested at VDDmax and Vin = 0
2) Iih ist tested at VDDmax and Vin = VDDmax
3) CMOS input levels are in percentage of VDD
4)
Output Pins
Pin Name
All output pins
(except XOUT0,XOUT1)
All I/O pins
Vol
V
0.4
Voh
V
4.0
Iol (1)
mA
4.0
Ioh(2)
mA
-4.0
Ioz(3)
µA
NA
NOTE
0.4
4.0
4.0
-4.0
+/-10
CMOS output, Tristate
CMOS output
1) Vol, Iol is tested at VDD = 4.5V
2) Voh, Ioh is tested at VDD = 4.5V
3) Ioz is tested at VDD = 5.5V
Rev. NC, October 1999
Page 6 of 13
TTP/C-C1 Communications Controller Data Sheet
AS8201
Austria Mikro Systeme International AG
AC Characteristics
Clock applied at XOUT0, resp. XOUT1.
PARAMETER
data in setup
time
data output
valid
SYMBOL
tsetup
PIN
MIN
all IN,
20 ns
all IO
all OUT,
all IO
tdav
MAX
NOTE
vs. Falling edge of clk @XOUT0, XOUT1
35 ns
vs. rising edge of clk @ XOUT0, XOUT1
Application Information
ROM Interface
Pin name
ROM_DATA
ROM_ADDRESS
ROM_CEB
ROM_WEB
ROM_OEB
ROM_READY
ROM_RESETB
mode
inout (tri)
out
out
out
out
in
out
width
16
17
1
1
1
1
1
comment
ROM data bus
ROM address bus
ROM chip enable
ROM write enable
ROM output enable
ROM ready
external reset line
Table 1 ROM Interface Ports
The timing and behaviour of the ROM Interface is designed to operate with the AM29F200
Flash EPROM or compatible devices. For detailed timing information see [AM29F200] 1. Figure
2 shows the connection between TTP/C-C1 controller and the AM29F200 Flash. The contents
of the Flash memory is loaded into the instruction memory by a boot sequencer automatically
after power on.
AM29F200
WE
CE
OE
rom_data
A0-A16
RY/BY
17
RESET
16
DQ0-DQ15
rom_resetb
rom_web
rom_ceb
rom_oeb
rom_address
BYTE
VCC
rom_ready
TTA-C1
Figure 2 ROM Interface2
Host CPU Interface
The host CPU interface also referred as CNI (controller network interface) connects the
application circuitry to the TTP/C network. As shown in Table 2 all RAM_-lines provide
asynchronous read/write access to a dual ported RAM. There are no setup/hold constraints
referred to the microtick (main clock “clk”). The signals have to be applied for certain duration
according to Table 3. So, the applied signals get synchronised with the microtick. The TIME_1
2
[AMD96] Advanced Micro Devices, "Flash Memory Products - 1996 Data Book/Handbook", Advanced Micro Devices Inc., 1996.
The label TTA-C1 stands for TTP/C-C1 in the following diagrams
Rev. NC, October 1999
Page 7 of 13
TTP/C-C1 Communications Controller Data Sheet
AS8201
Austria Mikro Systeme International AG
lines signal to host CPU the global synchronous time of the TTP network and determine when
to deliver, resp. to fetch data from the host interface. One of the lines may be connected to a
interrupt inputs of the host CPU.
Pin Name
RAM_ADDRESS
RAM_DATA
RAM_CEB
RAM_WEB
RAM_OEB
RAM_READYB
TIME_OVERFLOW
TIME_SIGNAL
TIME_TICK
mode
in
inout (tri)
in
in
in
out
out
out
out
width
11
16
1
1
1
1
1
1
1
comment
DPRAM address bus, 11 bit
DPRAM data bus, 16 bit
DPRAM chip enable
DPRAM write enable
DPRAM output enable
DPRAM ready
overflow of global time
CNI time signal
macrotick
Table 2 Host Interface Ports
tct
microtick
trwct
ram_ceb
tce
ram_web
ta
ram_address
ram_data
address stable
XXX
XXX
tdv
Figure 3: Read Cycle Timing
Addresses and RAM_WEB have to be stable before the falling edge of RAM_CEB. RAM_CEB
has to be applied for 2 microticks. Addresses and RAM_WEB have to be applied for 3
microticks. Data can be read from RAM_DATA after 6 microticks. RAM_OEB drives the result
of the (last) read operation to the RAM_DATA bus.
Rev. NC, October 1999
Page 8 of 13
TTP/C-C1 Communications Controller Data Sheet
AS8201
Austria Mikro Systeme International AG
tct
microtick
tce
ram_ceb
ram_web
ta
address stable
ram_address
ram_data
XXX
XXXX
data stable
trwct
Figure 4: Write Cycle Timing
Addresses, data and RAM_WEB have to be stable before the falling edge of RAM_CEB.
RAM_CEB has to be applied for 2 microticks. Addresses, data, and RAM_WEB have to be
applied for 3 microticks.
Parameter
controller cycle time
duration of chip enable
address time
data valid time
read write cycle time
Symbol
tct
tce
ta
tdv
trwct
Min
87.5ns
137.5ns
Typ
50ns
100ns
150ns
300ns
300ns
Max
112.5ns
162.5ns
Table 3: Host Interface Timing
Reset and Oscillator
Pin Name
XIN0
XENA0
XOUT0
XIN1
XOUT1
XENA1
RESETB
MICROTICK
mode
in
in
out
in
out
in
in
out
width
1
1
1
1
1
1
1
1
Comment
controller oscillator input
controller clock enable
controller oscillator output
bus guardian oscillator input
bus guardian oscillator output
bus guardian clock enable
external reset
controller clock (inverted)
Table 4: Reset and Oscillator Ports
External Reset Signal
To issue a reset of the chip the RESETB port has to be driven low for at least 200µs. After
power-up the reset must overlap the build-up time of the oscillator circuit.
Rev. NC, October 1999
Page 9 of 13
TTP/C-C1 Communications Controller Data Sheet
AS8201
Austria Mikro Systeme International AG
Integrated Power-On Reset
An internal Power-On Reset generator is integrated. When The supply voltage ramps up, the
internal reset signal is kept active (low) for about 24 us typical. To activate this function the
RESETB must be left unconnected.
Parameter
supply voltage slope
power on reset active time after VDD >
1,2V
external reset low to internal high
external reset high to internal low
Symbol
dV/dt
tpon_res
Min
250
16
Typ
24
Max
34
Unit
kV/s
us
tres_fall
treset_rise
81
130
118
129
173
104
ns
ns
Oscillator circuitry
The internal oscillator cell requires an external quartz or an external oscillator respectively
(Figure 5, Figure 6). The internal controller clock is available at the port MICROTICK (inverted
to clock signal applied at XOUT0).
20Mhz
16Mhz
VSS
VSS
20Mhz
VSS
16Mhz
VSS
OSC
XENA0
XIN0
XOUT0
XENA1
XIN1
XOUT1
XENA0
XENA0
XIN0
XOUT0
XOUT0
XIN0
OSC
XENA1
XENA1
XIN1
XOUT1
XOUT1
XIN1
TTA-C1
TTA-C1
Figure 5: Quartz Circuit
Figure 6: Oscillator Circuit
TTP/C Bus Interface
Pin Name
CTS
OE
TXD
RXD
BDE
mode
out
in
out
in
out
width
2
2
2
2
2
comment
transmitter clear to send
transmitter output enable
transmit data
receiver input
bus driver enable
Table 5: TTP/C Bus Interface Ports
The controller can be connected to transceivers with recessive state and to transceivers with
three-state outputs, respectively. For safe operation of the device the bus driver enable signal
BDE must be connected with output enable OE. To deactivate the bus guardian the OE signal
has to be tied to VCC. Applications with recessive state transceivers do not use the CTS
signal.
Rev. NC, October 1999
Page 10 of 13
TTP/C-C1 Communications Controller Data Sheet
AS8201
BUS0
BUS0
BUS1
CL
CH
CL
PCA82C250
BDE[0]
Austria Mikro Systeme International AG
OE[0]
TXD
RXD
TXD[0]
RXD[0]
CTS[0]
BUS1
CL
CH
BDE[1]
OE[1]
TXD
RXD
TXD[1]
RXD[1]
CTS[1]
TTA-C1
CH
CL
MAX1487
PCA82C250
BDE[0]
CH
MAX1487
RE
DI
DO
DE
OE[0]
TXD[0]
RXD[0]
CTS[0]
BDE[1]
RE
DI
DO
DE
OE[1]
TXD[1]
RXD[1]
CTS[1]
TTA-C1
Figure 7: Transceivers with Recessive State
Figure 8: Transceivers with Three-State Output
Test Interface
Pin Name
FTEST
FTEST_EIN
LED
TEST_SE
mode
in (pull down)
in (pull down)
out
in (pull down)
width
1
1
7
1
comment
functional test mode
instruction insertion enable
LED vector
scan enable
Table 6: Test Interface Ports
The ports of the test interface support the manufacturing test of the chip. In the application
environment FTEST, FTEST_IEN, and TEST_SE are not connected. The LED bus can be
used as a universal output port. The driver strength of the LED ports is 4mA.
Rev. NC, October 1999
Page 11 of 13
TTP/C-C1 Communications Controller Data Sheet
AS8201
Austria Mikro Systeme International AG
Principles of Operation
The next 2 figures show a typical TTP/C node as it is to be deployed in a TTP/C
communication cluster. The circuit example uses the MAX1487 as driver, the host CPU may
be selected by the user and a 29F200 Flash memory. For detailed information the protocol on
application programming refer to the manuals provided by TTTech Computer Technik GmbH.
Sensor / Actor interface
Host CPU
Controller network interface (CNI)
Boot ROM
(external)
Instruction
memory
TTP/C
Protocol
processor
TTP/C-C1
controller chip
Configuration
memory
(MEDL)
Bus guardian - Rx / Tx
Media Divers
TTP/C bus
Figure 9 Typical node in a TTP/C cluster using the TTP/C-C1
Host
CPU
20 MHz
Quartz
RAM_DATA[15:0]
RAM_ADDRESS[10:0]
RAM_CEB
RAM_OEB
RAM_WEB
RAM_READYB
TIME_OVERFLOW
TIME_SIGNAL
TIME_TICK
MICROTICK
XENA0
XIN0
XOUT0
TTP/C-C1
controller
RESETB
Flash
EPROM
29F200
ROM_ADDRESS[16:0]
ROM_DATA[15:0]
ROM_RESETB
ROM_CEB
ROM_OEB
ROM_WEB
ROM_READY
RE
TXD[0]
RXD[0]
CTS[0]
BDE[0]
OE[0]
DI
DO
DE
Bus0
CL
CH
MAX1487
RE
TXD[1]
RXD[1]
CTS[1]
BDE[1]
OE[1]
XENA1
XIN1
XOUT1
DI
DO
DE
Bus1
CL
CH
MAX1487
16 MHz
Quartz
TEST_SE
FTEST
FTEST_IEN
LED[7:0]
Figure 10 Typical application circuit
Rev. NC, October 1999
Page 12 of 13
TTP/C-C1 Communications Controller Data Sheet
AS8201
Austria Mikro Systeme International AG
Ordering Information
Part Number:
Part Name:
Package:
AS8201
TTP/C-C1 Communications Controller
PQFP 120
Support
Software tools, hardware development boards, evaluation systems and extensive support on
TTP/C system integration as well as consulting is provided by
TTTech Computertechnik GmbH
Time-Triggered Technology
Schönbrunnerstraße 7
A-1040 Vienna
Austria
Voice:
Fax:
email:
web:
+43 1 5853434 - 0
+43 1 5853434 - 90
office@tttech.com
http://www.tttech.com
TTP is a trademark of FTS Computertechnik Ges.m.b.H.
TTTech is a trademark of TTTech Computertechnik GmbH.
(c) 1999 Austria Mikro Systeme International AG and TTTech Computertechnik GmbH.
All rights reserved.
Copyright  1999, Austria Mikro Systeme International AG, Schloß Premstätten, 8141 Unterpremstätten, Austria.
Telefon +43-(0)3136-500-0, Telefax +43-(0)3136-52501, E-Mail info@amsint.com
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any
means, without the prior permission in writing by the copyright holder. To the best of its knowledge, Austria Mikro Systeme International
asserts that the information contained in this publication is accurate and correct.
Rev. NC, October 1999
Page 13 of 13