MITSUBISHI LSIs Preliminary Some of contents are subject to change without notice. MH4V6445BXJJ-5,-6,-5S,-6S HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM DESCRIPTION APPLICATION This is family of 4194304 - word by 64 - bit dynamic RAM module. This consists of four industry standard 4Mx16 dynamic RAMs in TSOP and one industry EEPROM in TSSOP. The mounting of TSOP on a card edge dual in line package provides any application where high densities and large of quantities memory are required. This is a socket-type memory module,suitable for easy interchange of addition of modules. Main memory unit for computer,Microcomputer memory,Refresh memory for CRT. *:Applicable to self refresh version(MH4V645/6445AXJJ-5S,-6S) only FEATURES RAS CAS Address OE access access access access Cycle time time time time time (max.ns) (max.ns) (max.ns) (max.ns) (min.ns) MH4V6445BXJJ-5,5S 50 13 25 13 84 MH4V6445BXJJ-6,6S 60 15 30 15 104 single 3.3V± 0.3V supply Low stand-by power dissipation 7.2mW- - - - - - - - - LVCMOS input level operating power dissipation MH4V6445BXJJ-5,5S - - - - 2016 mW(max.) MH4V6445BXJJ-6,6S - - - - 1872 mW(max.) Self refresh capability* Self refresh current - - - - 1600 uA(max.) All input, output LVTTL compatible and low capacitance Utilizes industry standard 4Mx16 RAMs in TSOP and industry standard EEPROM in TSSOP. Includes decoupling capacitor(0.22uFx4) Hyper page mode , Read-modify-write, CAS before RAS refresh,Hidden refresh capabilities. Early-write mode,OE and W to control output buffer impedance. ADDRESS Part No. MH4V6445BXJJ Row Add. Col Add. A0~A11 MIT-DS-0233-0.0 A0~A9 Refresh /RAS only Ref,Normal R/W CBR Ref,Hidden Ref Refresh Cycle Normal S-Version 4096/64ms 4096/128ms MITSUBISHI ELECTRIC ( 1 / 26 ) 24/Jul./1998 MITSUBISHI LSIs Preliminary MH4V6445BXJJ-5,-6,-5S,-6S Some of contents are subject to change without notice. HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM PIN CONFIGURATION PIN Number Front side Pin Name PIN Number Back side Pin Name PIN Number 1 Vss 2 Vss 73 3 DQ0 4 DQ32 75 5 DQ1 6 DQ33 7 DQ2 8 DQ34 Front side Pin Name PIN Number /OE 74 Vss Back side Pin Name RFU 76 Vss 77 Reserved 78 Reserved 79 Reserved 80 Reserved 9 DQ3 10 DQ35 81 Vcc 82 Vcc 11 Vcc 12 Vcc 83 DQ16 84 DQ48 13 DQ4 14 DQ36 85 DQ17 86 DQ49 15 DQ5 16 DQ37 87 DQ18 88 DQ50 17 DQ6 18 DQ38 89 DQ19 90 DQ51 19 DQ7 20 DQ39 91 Vss 92 Vss 21 Vss 22 Vss 93 DQ20 94 DQ52 23 /CAS0 24 /CAS4 95 DQ21 96 DQ53 25 /CAS1 26 /CAS5 97 DQ22 98 DQ54 27 Vcc 28 Vcc 99 DQ23 100 DQ55 29 A0 30 A3 101 Vcc 102 Vcc 31 A1 32 A4 103 A6 104 A7 33 A2 34 A5 105 A8 106 A11 35 Vss 36 Vss 107 Vss 108 37 DQ8 38 DQ40 109 A9 110 Vss NC 39 DQ9 40 DQ41 111 A10 112 NC 41 DQ10 42 DQ42 113 Vcc 114 Vcc 43 DQ11 44 DQ43 115 /CAS2 116 /CAS6 45 Vcc 46 Vcc 117 /CAS3 118 /CAS7 47 DQ12 48 DQ44 119 Vss 120 Vss 49 DQ13 50 DQ45 121 DQ24 122 DQ56 51 DQ14 52 DQ46 123 DQ25 124 DQ57 53 DQ15 54 DQ47 125 DQ26 126 DQ58 55 Vss 56 Vss 127 DQ27 128 DQ59 57 Reserved 58 Reserved 129 Vcc 130 Vcc 59 Reserved 60 Reserved 131 DQ28 132 DQ60 61 RFU 62 FRU 133 DQ29 134 DQ61 63 Vcc 64 Vcc 135 DQ30 136 DQ62 65 RFU 66 RFU 137 DQ31 138 DQ63 67 /WE 68 RFU 139 Vss 140 Vss 69 /RAS0 70 RFU 141 SDA 142 SCL 71 NC 72 RFU 143 Vcc 144 Vcc RFU:Reserved Future Use NC,RFU,Reserved: NO CONNECTION MIT-DS-0233-0.0 MITSUBISHI ELECTRIC ( 2 / 26 ) 24/Jul./1998 MITSUBISHI LSIs Preliminary MH4V6445BXJJ-5,-6,-5S,-6S Some of contents are subject to change without notice. HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM Block Diagram Address /OE /WE /RAS0 /CAS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 /CAS4 /LCAS /RAS /WE /OE I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 /CAS1 /UCAS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 D0 /CAS2 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 /LCAS /RAS /WE /OE I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 /CAS5 /UCAS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 D2 /CAS6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 /LCAS /RAS /WE /OE I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 /CAS3 /UCAS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 D1 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 /LCAS /RAS /WE /OE I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 /CAS7 /UCAS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 D3 SERIAL PD Vcc D0 to D3 SCL C1~C4 Vss A0 A1 A2 SDA D0 to D3 Vss MIT-DS-0233-0.0 MITSUBISHI ELECTRIC ( 3 / 26 ) 24/Jul./1998 MITSUBISHI LSIs Preliminary MH4V6445BXJJ-5,-6,-5S,-6S Some of contents are subject to change without notice. HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM FUNCTION The MH4V6445BXJJ provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., Hyper page mode, /RAS-only refresh, and delayed-write. The input conditions for each are shown in Table 1. Table 1 Input conditions for each mode Inputs Operation Read Write (Early write) Write (Delayed write) Read-modify-write /RAS-only refresh Hidden refresh /CAS before /RAS refresh Standby Self refresh * /RAS ACT ACT ACT ACT ACT ACT ACT NAC ACT /CAS ACT ACT ACT ACT NAC ACT ACT DNC ACT /W NAC ACT ACT ACT DNC NAC NAC DNC NAC Input/Output Remark Row Column Input Output Refresh /OE address address ACT APD APD OPN VLD YES Hyper DNC APD APD VLD OPN YES page mode DNC APD APD VLD IVD YES identical ACT APD APD VLD VLD YES DNC APD DNC DNC OPN YES ACT APD DNC OPN VLD YES DNC DNC DNC DNC OPN YES DNC DNC DNC DNC OPN NO DNC DNC DNC DNC OPN YES Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open *MH4V6445BXJJ-5S,-6S only MIT-DS-0233-0.0 MITSUBISHI ELECTRIC ( 4 / 26 ) 24/Jul./1998 MITSUBISHI LSIs Preliminary Some of contents are subject to change without notice. MH4V6445BXJJ-5,-6,-5S,-6S HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI VO IO Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Conditions With respect to Vss Ta=25°C RECOMMENDED OPERATING CONDITIONS Symbol Vcc Vss VIH VIL Ratings -0.5~4.6 -0.5~4.6 -0.5~4.6 50 4 0~ 70 -40~ 100 Parameter Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage, all inputs Unit V V V mA W °C °C (Ta=0~ 70°C, unless otherwise noted) (Note 1) Min 3.0 0 2.0 -0.3 Limits Nom 3.3 0 Max 3.6 0 Vcc+0.3 0.8 Unit V V V V Note 1 : All voltage values are with respect to Vss ELECTRICAL CHARACTERISTICS Symbol (Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted) (Note 2) Parameter VOH VOL IOZ II High-level output voltage Low-level output voltage Off-state output current Input current Average supply -5,-5S ICC1 (AV) current from Vcc operating (Note 3,4,5) -6,-6S ICC2 Supply current from Vcc , stand-by Average supply current -5,-5S ICC4(AV) from Vcc Hyper-Page-Mode (Note 3,4,5) -6,-6S Average supply current -5,-5S from Vcc ICC6(AV) /CAS before /RAS refresh (Note 3,5) -6,-6S mode Test conditions IOH=-2.0mA IOL=2.0mA Q floating 0V≤VOUT≤3.6V 0V≤VIN≤3.6V, Other input pins=0V /RAS, /CAS cycling tRC=tWC=min. output open /RAS=/CAS =VIH, output open /RAS=/CAS≥Vcc -0.2, output open /RAS=VIL,/CAS cycling tPC=min. output open /CAS before /RAS refresh cycling tRC=min. output open Min 2.4 0 -10 -40 Limits Typ Max Vcc 0.4 10 40 Unit V V uA uA 560 mA 520 4 2 480 mA mA 440 560 mA 520 Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column address can be changed once or less while /RAS=VIL and /CAS=VOH CAPACITANCE Symbol CI (A) CI C(CAS) C(DQ) C(SDA) C(SCL) (Ta = 0~70°C, Vcc = 3.3V±0.3V, Vss = 0V, unless otherwise noted) Parameter Test conditions Input capacitance, address inputs Input capacitance, clock inputs except CAS Input capacitance, CAS Input/Output capacitance,DATA Input/Output capacitance,SDA Input capacitance, SCL MIT-DS-0233-0.0 VI=Vss f=1MHZ Vi=25mVrms MITSUBISHI ELECTRIC ( 5 / 26 ) Min Limits Typ Max 40 45 25 25 12 12 Unit pF pF pF pF pF pF 24/Jul./1998 Preliminary Some of contents are subject to change without notice. MITSUBISHI LSIs MH4V6445BXJJ-5,-6,-5S,-6S HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM SWITCHING CHARACTERISTICS (Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless Symbol tCAC tRAC tAA tCPA tOEA tOHC tOHR tCLZ tOEZ tWEZ tOFF tREZ tDOH Parameter (Note 7,8) Access time from /CAS (Note 7,9) Access time from /RAS (Note 7,10) Column address access time (Note 7,11) Access time from /CAS precharge (Note 7) Access time from /OE Output hold time /CAS high (Note 13) Output hold time /RAS high Output low impedance time from /CAS low (Note 7) (Note 12) Output disable time after /OE high (Note 12) Output disable time after /WE high (Note 12,13) Output disable time after /CAS high (Note 12,13) Output disable time after /RAS high Output hold time from /CAS low otherwise noted , see notes 6,14,15) Limits -5,-5S -6,-6S Min Max Min Max 13 15 50 60 25 30 28 33 13 15 5 5 5 5 5 5 13 15 13 15 13 15 13 15 5 5 -7,-7S Unit Min Max ns 20 ns 70 ns 35 ns 40 ns 20 5ns 5ns 5ns ns 20 ns 20 ns 20 ns 20 5ns Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing a /RAS clock such as /RAS-Only refresh). Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods (greater than 64 ms) of /RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to 100pF. The reference levels for measuring of output signals are 2.0(VOH)and 0.8(VOL). 8: Assumes that tRCD≥tRCD(max), tASC≥tASC(max) and tCP≥tCP(max). 9: Assumes that tRCD≤tRCD(max) and tRAD≤tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD≥tRAD(max) and tASC≤tASC(max). 11: Assumes that tCP≤tCP(max) and tASC≥tASC(max). 12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT≤ ±10uA) and is not reference to VOH(min) or VOL(max). 13: Output is disable after both /RAS and /CAS go to high TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Hyper-Page Mode Cycles) (Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted ,see notes 14,15) Symbol tREF tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tRDD tCDD tODD tT Parameter Refresh cycle time Refresh cycle time(S-version ONLY) /RAS high pulse width Delay time, /RAS low to /CAS low Delay time, /CAS high to /RAS low Delay time, /RAS high to /CAS low /CAS high pulse width Column address delay time from /RAS low Row address setup time before /RAS low Column address setup time before /CAS low Row address hold time after /RAS low Column address hold time after /CAS low Delay time, data to /CAS low Delay time, data to /OE low Delay time, /RAS high to data Delay time, /CAS high to data Delay time, /OE high to data Transition time (Note16) (Note17) (Note18) (Note19) (Note19) (Note20) (Note20) (Note20) (Note21) Limits -5,-5S -6,-6S Min Max Min Max 64 64 128 128 30 40 14 37 14 45 5 5 0 0 8 10 10 12 25 30 0 0 10 0 0 13 8 10 8 10 0 0 0 0 13 15 13 15 13 15 1 50 1 50 Unit ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 14: The timing requirements are assumed tT =2ns. 15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. . 17: tRAD(max) is specified as a reference point only. If tRAD≥tRAD(max) and tASC≤tASC(max), access time is controlled exclusively by tAA. 18: tASC(max) is specified as a reference point only. If tRCD≥tRCD(max) and tASC≥tASC(max), access time is controlled exclusively by tCAC. 19: Either tDZC or tDZO must be satisfied. 20: Either tRDD or tCDD or tODD must be satisfied. 21: tT is measured between VIH(min) and VIL(max). MIT-DS-0233-0.0 MITSUBISHI ELECTRIC ( 6 / 26 ) 24/Jul./1998 Preliminary Some of contents are subject to change without notice. MITSUBISHI LSIs MH4V6445BXJJ-5,-6,-5S,-6S HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM Read and Refresh Cycles Symbol tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tCAL tORH tOCH Parameter Read cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low Read Setup time after /CAS high Read hold time after /CAS low Read hold time after /RAS low Column address to /RAS hold time Column address to /CAS hold time /RAS hold time after /OE low /CAS hold time after /OE low Limits -5,-5S -6,-6S Unit -7,-7S Min Max Min Max Min Max 84 104 130ns 50 10000 60 10000 70ns 10000 8 10000 10 10000 13ns 10000 35 40 55ns 13 15 20ns 0 0 0ns (Note 22) 0 0 0ns (Note 22) 0 0 10ns 25 30 35ns 13 18 23ns 13 15 20ns 13 15 20ns Unit ns ns ns ns ns ns ns ns ns ns ns ns Note 22: Either tRCH or tRRH must be satisfied for a read cycle. Write Cycle (Early Write and Delayed Write) Symbol tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH Parameter Write cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low (Note 24) Write setup time before /CAS low Write hold time after /CAS low /CAS hold time after /W low /RAS hold time after /W low Write pulse width Data setup time before /CAS low or /W low Data hold time after /CAS low or /W low Limits -5,-5S -6,-6S Unit -7,-7S Min Max Min Max Min Max 84 104 130ns 50 10000 60 10000 70ns 10000 8 10000 10 10000 13ns 10000 35 40 55ns 13 15 20ns 0 0 0ns 8 10 13ns 8 10 13ns 8 10 13ns 8 10 13ns 0 0 0ns 8 10 13ns Unit ns ns ns ns ns ns ns ns ns ns ns ns Read-Write and Read-Modify-Write Cycles Symbol tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tOEH Parameter Read write/read modify write cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low Read setup time before /CAS low Delay time, /CAS low to /W low Delay time, /RAS low to /W low Delay time, address to /W low /OE hold time after /W low (Note21) (Note24) (Note24) (Note24) Limits -5,-5S -6,-6S Min Max Min Max 109 133 75 10000 89 10000 38 10000 44 10000 70 82 38 44 0 0 28 32 65 77 40 47 13 15 Unit -7,-7S Min Max 161 ns 107 ns 10000 ns 10000 57 99 ns 57 ns ns 0 ns 42 92 ns ns 57 ns 20 Unit ns ns ns ns ns ns ns ns ns ns Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. 24:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS≥tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD≥tCWD(min), tRWD≥tRWD (min), tAWD≥tAWD(min) and tCPWD≥tCPWD(min) (for Hyper page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until /CAS or /OE goes back to VIH) is indeterminate. MIT-DS-0233-0.0 MITSUBISHI ELECTRIC ( 7 / 26 ) 24/Jul./1998 Preliminary Some of contents are subject to change without notice. MITSUBISHI LSIs MH4V6445BXJJ-5,-6,-5S,-6S HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM Hyper Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle, Read Write Mix Cycle,Hi-Z control by /OE or /WE) (Note 25) Symbol tHPC tHPRWC tRAS tCP tCPRH tCPWD tCHOL tOEPE tWPE tHCWD tHAWD tHPWD tHCOD tHAOD tHPOD Parameter Hyper page mode read/write cycle time Hyper page mode read write/read modify write cycle time /RAS low pulse width for read write cycle (Note26) /CAS high pulse width (Note27) /RAS hold time after /CAS precharge Delay time, /CAS precharge to /W low (Note24) Hold time to maintain the data Hi-Z until /CAS access /OE Pulse Width (Hi-Z control) /W Pulse Width (Hi-Z control) Delay time, /CAS low to /W low after read Delay time, Address to /W low after read Delay time, /CAS precharge to /W low after read Delay time, /CAS low to /OE high after read Delay time, Address to /OE high after read Delay time, /CAS prechargeto /OE high after read Limits -5,-5S -6,-6S Unit -7,-7S Min Max Min Max Min Max 20 25 30ns 55 66 79ns 65 100000 77 100000 92ns 100000 8 13 10 16 10ns 16 28 33 40ns 43 50 62ns 7 7 7ns 7 7 7ns 7 7 7ns 28 32 42ns 40 47 72ns 43 50 82ns 13 15 20ns 25 30 35ns 28 33 40ns Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective Hyper page mode cycle. 26: tRAS(min) is specified as two cycles of /CAS input are performed. 27: tCP(max) is specified as a reference point only.If tCP≥tCP(max),access time is controlled exclusively by tCAC. /CAS before /RAS Refresh Cycle (Note 28) Symbol tCSR tCHR tRSR tRHR Parameter /CAS setup time before /RAS low /CAS hold time after /RAS low Read setup time before /RAS low Read hold time after /RAS low Limits -5,-5S -6,-6S Min Max Min Max 5 5 10 10 10 10 10 10 -7,-7S Unit Min Max 5ns 15ns 5ns 15ns Unit ns ns ns ns Note 28: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS refresh mode. MIT-DS-0233-0.0 MITSUBISHI ELECTRIC ( 8 / 26 ) 24/Jul./1998 MITSUBISHI LSIs Preliminary MH4V6445BXJJ-5,-6,-5S,-6S Some of contents are subject to change without notice. HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM SELF REFRESH SPECIFICATIONS Self refresh devices are denoted by "S" after speed item,line -5S / -6S. The other characteristics and requirements then below are same as normal device. ELECTRIC CHARACTERISTICS (Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless Symbol Parameter otherwise noted) (Note 2) Test conditions Min Limits Typ Max /RAS=/CAS<0.2V Average supply current ICC9(AV)* from Vcc Self-Refresh mode -5S,-6S /OE=/W=A0~A12(A11)=Vcc-0.2V or (Note 6) 0.2V output=Vcc-0.2V,0.2V or open TIMING REQUIREMENTS 1600 Unit µA (Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted ,see notes 13,14) Limits Symbol Parameter -5S Min tRASS CBR Self Refresh RAS low pulse width tRPS CBR Self Refresh RAS high precharge time tCHS CBR Self Refresh RAS hold time Max -6S Min Max Unit -7S Min Max Unit 100 100 us 100 us 84 104 ns 130 ns - 50 - 50 ns - 50 ns SELF REFRESH ENTRY & EXIT CONDITIONS (1) In case of CBR distributed refresh The last / first full refresh cycles must be made within tNS / tSN before / after self refresh , on the condition of tNS≤ 128 ms and tSN ≤ 128 ms. tSN tNS Self refresh period DISTRIBUTED REFRESH < 128 ms > DISTRIBUTED REFRESH < 128 ms > (2) In case of burst refresh The last / first full refresh cycles must be made within tNS / tSN before / after self refresh , on the condition of tNS ≤ 16ms and tSN ≤ 16 ms. tSN tNS Self refresh period BURST REFRESH < 128 ms > MIT-DS-0233-0.0 BURST REFRESH < 128 ms > MITSUBISHI ELECTRIC ( 9 / 26 ) 24/Jul./1998 MITSUBISHI LSIs Preliminary MH4V6445BXJJ-5,-6,-5S,-6S Some of contents are subject to change without notice. HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM Timing Diagrams Read Cycle (Note 29) tRC tRAS tRP VIH /RAS VIL tCSH tCRP tRCD tCRP tRSH tCAS VIH /CAS VIL tRAL tCAL tRAD tASR VIH Address VIL tRAH tASC ROW ADDRESS tASR tCAH ROW ADDRESS COLUMN ADDRESS tRRH tRCH tRCS VIH /W VIL tCDD tDZC tRDD VIH DQ (INPUTS) Hi-Z VIL tREZ tCAC tAA tOHR tCLZ DQ (OUTPUTS) tWEZ tOFF tOHC VOH Hi-Z VOL Hi-Z DATA VALID tRAC tDZO tOEA tOCH tOEZ tODD VIH /OE VIL tORH Note 29 Indicates the don't care input. VIH(min)≤VIN≤VIH(max) or VIL(min)≤VIN≤VIL(max) Indicates the invalid output. MIT-DS-0233-0.0 MITSUBISHI ELECTRIC ( 10 / 26 ) 24/Jul./1998 MITSUBISHI LSIs Preliminary MH4V6445BXJJ-5,-6,-5S,-6S Some of contents are subject to change without notice. HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM Early Write Cycle tWC tRAS tRP VIH /RAS VIL tCSH tCRP tRCD tRSH tCAS tCRP VIH /CAS VIL tASR VIH Address VIL tASR tRAH tASC tCAH ROW ADDRESS COLUMN ADDRESS ROW ADDRESS tWCS tWCH VIH /W VIL tDH tDS DQ (INPUTS) DQ (OUTPUTS) VIH DATA VALID VIL VOH Hi-Z VOL VIH /OE VIL MIT-DS-0233-0.0 MITSUBISHI ELECTRIC ( 11 / 26 ) 24/Jul./1998 MITSUBISHI LSIs Preliminary MH4V6445BXJJ-5,-6,-5S,-6S Some of contents are subject to change without notice. HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM Delayed Write Cycle tWC tRP tRAS VIH /RAS VIL tCRP tCSH tCRP tRSH tRCD tCAS VIH /CAS VIL tASR VIH Address VIL tRAH tCAH tASC ROW ADDRESS tASR ROW ADDRESS COLUMN ADDRESS tCWL tRWL tWP tRCS VIH /W VIL tWCH tDZC VIH DQ (INPUTS) tDS tDH DATA VALID Hi-Z VIL tCLZ DQ (OUTPUTS) VOH Hi-Z Hi-Z VOL tDZO tOEZ tOEH tODD /OE VIH VIL MIT-DS-0233-0.0 MITSUBISHI ELECTRIC ( 12 / 26 ) 24/Jul./1998 MITSUBISHI LSIs Preliminary MH4V6445BXJJ-5,-6,-5S,-6S Some of contents are subject to change without notice. HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM Read-Write, Read-Modify-Write Cycle tRWC tRAS tRP VIH /RAS VIL tCRP tCSH tRCD tCRP tRSH tCAS VIH /CAS VIL tRAD tASR VIH Address VIL tRAH tCAH tASC tASR COLUMN ADDRESS ROW ADDRESS ROW ADDRESS tAWD tCWD tRWD tRCS tCWL tRWL tWP VIH /W VIL tDH tDS tDZC DQ (INPUTS) VIH Hi-Z VIL DATA VALID tCAC tAA tCLZ DQ (OUTPUTS) VOH DATA VALID Hi-Z VOL tRAC Hi-Z tODD tDZO tOEA tOEH tOEZ /OE VIH VIL MIT-DS-0233-0.0 MITSUBISHI ELECTRIC ( 13 / 26 ) 24/Jul./1998 MITSUBISHI LSIs Preliminary Some of contents are subject to change without notice. MH4V6445BXJJ-5,-6,-5S,-6S HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM Hyper Page Mode Read Cycle tRAS tRP VIH /RAS VIL tCSH tCRP tCAS tRCD tCP tHPC tCAS tCP tRSH tCAS tASC tCAH tASC VIH /CAS VIL tRAD tASR VIH Address VIL tRAH ROW ADDRESS tCAH tASC COLUMN-2 COLUMN-1 tCPRH tCAH tASR ROW ADDRESS COLUMN-3 tRCS tRRH tCAL tCAL tCAL tRCH VIH /W VIL tWEZ tDZC DQ (INPUTS) tRDD tCDD VIH Hi-Z tCAC VIL tAA tCLZ DQ (OUTPUTS) VOH VOL VIL /OE tAA tAA tDOH tDOH DATA VALID-1 Hi-Z tRAC tDZO tCAC tCAC tCPA DATA VALID-2 tREZ tOHR tOFF tOHC DATA VALID-3 tCPA tOEA tOCH tOEZ VIH tODD MIT-DS-0233-0.0 MITSUBISHI ELECTRIC ( 14 / 26 ) 24/Jul./1998 MITSUBISHI LSIs Preliminary MH4V6445BXJJ-5,-6,-5S,-6S Some of contents are subject to change without notice. HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM Hyper Page Mode Early Write Cycle tRAS tRP VIH /RAS VIL tCSH tCRP tCAS tRCD tHPC tCAS tCP tRSH tCP tCAS tCRP VIH /CAS VIL tCAL tASR VIH Address VIL tRAH ROW ADDRESS tASC tCAH tASC COLUMN-2 COLUMN-1 tWCS tWCH tCAH tWCS tWCH tASC tCAL tCAH COLUMN-3 tWCS tASR ROW ADDRESS tWCH VIH /W VIL tDS DQ (INPUTS) DQ (OUTPUTS) VIH VIL tDH tDS tDH DATA VALID-2 DATA VALID-1 tDS tDH DATA VALID-3 VOH Hi-Z VOL VIL /OE MIT-DS-0233-0.0 VIH MITSUBISHI ELECTRIC (15 / 26 ) 24/Jul./1998 MITSUBISHI LSIs Preliminary MH4V6445BXJJ-5,-6,-5S,-6S Some of contents are subject to change without notice. HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM Hyper Page Mode Read-Write,Read-Modify-Write Cycle tRAS tRP VIH /RAS VIL tCSH tCRP tRCD tRWL tCRP tHPRWC tCAS tCAS tCP VIH /CAS VIL tRAD tASR VIH Address VIL tRAH tCAH tASC ROW ADDRESS tASC COLUMN-1 tASR ROW ADDRESS COLUMN-2 tAWD tRCS tCWL tCAH tAWD tCWL tCWD tRCS tCWD tWP tWP VIH /W VIL tRWD tCPWD tDZC DQ (INPUTS) VIH tDZC tCLZ tCLZ VOH DATA VALID-1 Hi-Z VOL tRAC tDZO DATA VALID-2 Hi-Z tODD tOEA tCPA tDZO tOEZ VIH /OE DATA VALID-2 Hi-Z tCAC tAA tAA DQ (OUTPUTS) tDH tDS DATA VALID-1 Hi-Z tCAC VIL tDH tDS tOEA Hi-Z tODD tOEH tOEZ VIL MIT-DS-0233-0.0 MITSUBISHI ELECTRIC ( 16 / 26 ) 24/Jul./1998 MITSUBISHI LSIs Preliminary Some of contents are subject to change without notice. MH4V6445BXJJ-5,-6,-5S,-6S HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM Hyper Page Mode Mix Cycle (1) tRP tRAS /RAS tRWL VIH VIL tCRP tCSH tHPC tCRP tCAS tRCD tHPRWC tCAS tCP tCP tCAS VIH tCWL /CAS VIL tRAD tASR VIH Address VIL tRAH ROW ADDRESS tASC tCAH tASC tCAL ROW ADDRESS COLUMN-3 tCPWD tAWD tWCH tWCS tASR tASC tCAH COLUMN-2 COLUMN-1 tRCS /W tCAH tCAL tCWD tWP VIH VIL tDZC DQ (INPUTS) VIH tDZ tDS C DATA VALID-2 tCAC VIL tDH tDS DATA VALID-3 tAA tCAC tAA tWEZ tCLZ DQ (OUTPUTS) VOH DATA VALID-3 VOL tRAC tDZO tCPA tOEA tOEZ VIL /OE tCLZ DATA VALID-1 Hi-Z tDH tDZO tOEA tOEZ tOEH tOCH VIH tODD tODD Note30: /OE=L; /W Hi-Z control /OE=H; OE Hi-Z control MIT-DS-0233-0.0 MITSUBISHI ELECTRIC ( 17 / 26 ) 24/Jul./1998 MITSUBISHI LSIs Preliminary Some of contents are subject to change without notice. MH4V6445BXJJ-5,-6,-5S,-6S HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM Hyper Page Mode Mix Cycle (2) VIH /RAS VIL tHPC VIH /CAS VIL tCP tASC tCAS tCAS tCAH tASC tCAH tASC tCAH VIH COLUMN-1 Address COLUMN-2 COLUMN-3 VIL tCAL tRCH tCAL tWCS tWCH VIH /W tHCWD VIL tHAWD tDH tDS tHPWD VIH DQ (INPUTS) DATA VALID-2 Hi-Z tCAC VIL tDZC tAA tCAC Hi-Z tAA tCPA tWEZ tCPA tCLZ DQ (OUTPUTS) VOH DATA VALID-1 VOL DATA VALID-3 Hi-Z tHCOD VIL /OE tDZC tOEZ tHAOD tOEA tODD tHPOD VIH Note30: /OE=L; /W Hi-Z control /OE=H; OE Hi-Z control MIT-DS-0233-0.0 MITSUBISHI ELECTRIC ( 18 / 26 ) 24/Jul./1998 MITSUBISHI LSIs Preliminary MH4V6445BXJJ-5,-6,-5S,-6S Some of contents are subject to change without notice. HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM Hyper Page Mode Read Cycle ( Hi-Z control by OE ) tRAS tRP VIH /RAS VIL tCSH tCRP tCAS tRCD tCP tHPC tCAS tRSH tCAS tCP tCRP VIH /CAS VIL tRAD tASR VIH Address VIL tRAH tASC ROW ADDRESS tASC tCAH COLUMN-1 tCAH tASC COLUMN-2 tCPRH tCAH tASR ROW ADDRESS COLUMN-3 tRAL tRRH tRCS tRCH VIH /W VIL tWEZ tDZC tRDD tCDD VIH DQ (INPUTS) tCAC tCAC VIL tAA tCLZ DQ (OUTPUTS) VOH DATA VALID-1 Hi-Z VOL tRAC tDZO VIL /OE tAA tCAC tAA tDOH tCLZ DATA VALID-1 DATA VALID-2 tOEA tOCH Hi-Z tREZ tOHR tOFF tOHC DATA VALID-3 tCPA tCPA tOEZ tCHOL tOEZ tOEZ tOEA VIH tOEPE MIT-DS-0233-0.0 Hi-Z MITSUBISHI ELECTRIC ( 19 / 26 ) tOEPE tODD 24/Jul./1998 MITSUBISHI LSIs Preliminary Some of contents are subject to change without notice. MH4V6445BXJJ-5,-6,-5S,-6S HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM Hyper Page Mode Read Cycle ( Hi-Z control by W ) tRAS /RAS tRP VIH VIL tCSH tCRP tCAS tRCD tHPC tCAS tCP tRSH tCAS tCP tCRP VIH /CAS VIL tRAD tASR VIH Address VIL tRAH ROW ADDRESS tASC tCAH tASC tASC tCAH COLUMN-2 COLUMN-1 tCPRH tCAH tRCH tRCS /W ROW ADDRESS COLUMN-3 tRAL tRCS tASR tRRH tRCH VIH VIL tDZC DQ (INPUTS) tWPE VIH tCAC tCAC VIL tAA tDOH VOH VIL /OE tCAC tAA tWEZ DATA VALID-2 DATA VALID-1 Hi-Z VOL tRAC tDZO Hi-Z tAA tCLZ DQ (OUTPUTS) tRDD tCDD tCPA tOEA tOCH tCLZ Hi-Z tREZ tOHR tOFF tOHC DATA VALID-3 tCPA tOEZ VIH tODD MIT-DS-0233-0.0 MITSUBISHI ELECTRIC ( 20 / 26 ) 24/Jul./1998 MITSUBISHI LSIs Preliminary MH4V6445BXJJ-5,-6,-5S,-6S Some of contents are subject to change without notice. HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM RAS-only Refresh Cycle tRC tRAS /RAS tRP VIH VIL tRPC tCRP tCRP /CAS VIH VIL tASR Address VIH VIL /W tRAH tASR ROW ADDRESS ROW ADDRESS VIH VIL DQ (INPUTS) DQ (OUTPUTS) VIH VIL VOH Hi-Z VOL VIH /OE MIT-DS-0233-0.0 VIL MITSUBISHI ELECTRIC ( 21 / 26 ) 24/Jul./1998 MITSUBISHI LSIs Preliminary MH4V6445BXJJ-5,-6,-5S,-6S Some of contents are subject to change without notice. HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM /CAS before /RAS Refresh Cycle tRC tRP /RAS tRC tRAS tRAS tRP VIH VIL tRPC tCSR /CAS tCHR tRPC tCSR tCHR tRPC tCRP VIH VIL tCPN tASR Address VIH ROW ADDRESS VIL COLUMN ADDRESS tRRH tRCH /W tRCS VIH VIL DQ (INPUTS) VIH VIL DQ (OUTPUTS) tREZ tOHR tOFF tOHC VOH Hi-Z VOL tOEZ VIH /OE VIL MIT-DS-0233-0.0 MITSUBISHI ELECTRIC ( 22 / 26 ) 24/Jul./1998 MITSUBISHI LSIs Preliminary MH4V6445BXJJ-5,-6,-5S,-6S Some of contents are subject to change without notice. HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM Hidden Refresh Cycle (Read) (Note 30) tRC tRAS tRC tRP tRAS tRP VIH /RAS VIL tCRP tRCD tRSH tCHR VIH /CAS VIL tRAD tASR VIH Address VIL tRAH tASC tASR tCAH COLUMN ADDRESS ROW ADDRESS tRCS ROW ADDRESS tRRH tRAL tRCH VIH /W VIL tCDD tDZC tRDD VIH DQ (INPUTS) Hi-Z VIL tCAC tAA tOFF tOHC tCLZ DQ (OUTPUTS) tREZ tOHR VOH Hi-Z Hi-Z DATA VALID VOL tRAC tDZO tOEA tORH tOEZ tODD VIH /OE VIL Note 31: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above. MIT-DS-0233-0.0 MITSUBISHI ELECTRIC ( 23 / 26 ) 24/Jul./1998 MITSUBISHI LSIs Preliminary MH4V6445BXJJ-5,-6,-5S,-6S Some of contents are subject to change without notice. HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM Self Refresh Cycle tRASS tRP /RAS tRPS VIH VIL tRPC tRPC tCSR /CAS tCHS tCRP VIH VIL tCPN tASR VIH ROW ADDRESS Address VIL tRRH tRCS tRCH /W VIH VIL tRDD tCDD DQ (INPUTS) VIH VIL DQ (OUTPUTS) Hi-Z tREZ tOHR tOFF tOHC Hi-Z VOH VOL tOEZ tODD VIH /OE VIL MIT-DS-0233-0.0 MITSUBISHI ELECTRIC ( 24 / 26 ) 24/Jul./1998 MITSUBISHI LSIs Preliminary MH4V6445BXJJ-5,-6,-5S,-6S Some of contents are subject to change without notice. HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM Outline 3.63MAX 20 25.40 67.6 3.3 23.2 29 3.7 23.2 MIT-DS-0233-0.0 4.6 32.8 1.00 32.8 MITSUBISHI ELECTRIC ( 25 / 26 ) 24/Jul./1998 MITSUBISHI LSIs Preliminary Some of contents are subject to change without notice. MH4V6445BXJJ-5,-6,-5S,-6S HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable,but there is always the possibility that trouble may occur with them. Trouble with semiconductors consideration to safety when making your circuit designs,with appropriate measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1.These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application;they do not convey any license under any intellectual property rights,or any other rights,belonging to Mitsubishi Electric Corporation or a third party. 2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights,originating in the use of any product data,diagrams,charts or circuit application examples contained in these materials. 3.All information contained in these materials,including product data, diagrams and charts,represent information on products at the time of publication of these materials,and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. 4.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for special applications,such as apparatus or systems for transportation, vehicular,medical,aerospace,nuclear,or undersea repeater use. 5.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. 6.If these products or technologies are subject the Japanese export control restrictions,they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. MIT-DS-0233-0.0 MITSUBISHI ELECTRIC ( 26 / 26 ) 24/Jul./1998