ETC CXK79M36C165GB

SONY ΣRAM
CXK79M72C165GB
CXK79M36C165GB
CXK79M18C165GB
18Mb 1x1Dp LVCMOS High Speed Synchronous SRAMs (256Kb x 72 or 512Kb x 36 or 1Mb x 18)
33/4/5
Preliminary
Description
The CXK79M72C165GB (organized as 262,144 words by 72 bits), CXK79M36C165GB (organized as 524,288 words by 36
bits), and the CXK79M18C165GB (organized as 1,048,576 words by 18 bits) are high speed CMOS synchronous static RAMs
with common I/O pins. They are manufactured in compliance with the JEDEC-standard 209 pin BGA package pinouts defined
for SigmaRAMs. They integrate input registers, high speed RAM, output registers, and a two-deep write buffer onto a single
monolithic IC. Single Data Rate (SDR) Pipelined (PL) read operations and Double Late Write (DLW) write operations are supported, providing a high-performance user interface. Positive and negative output clocks are provided for applications requiring
source-synchronous operation.
All address and control input signals are registered on the rising edge of the CK input clock.
During read operations, output data is driven valid once, from the rising edge of CK, one full cycle after the address and control
signals are registered.
During write operations, input data is registered once, on the rising edge of CK, two full cycles after the address and control
signals are registered.
Output drivers are series-terminated, and output impedance is selectable via the ZQ control pin. When ZQ is tied “low”, the
impedance of the SRAM’s output drivers is set to ~25Ω. When ZQ is tied “high” or left unconnected, the impedance of the
SRAM’s output drivers is set to ~50Ω.
300 MHz operation (300 Mbps) is obtained from a single 1.8V power supply. JTAG boundary scan interface is provided using
a subset of IEEE standard 1149.1 protocol.
Features
•
3 Speed Bins
Cycle Time / Data Access Time
-33
3.3ns / 1.8ns
-4
4.0ns / 2.1ns
-5
5.0ns / 2.3ns
• Single 1.8V power supply (VDD): 1.7V (min) to 1.95V (max)
• Dedicated output supply voltage (VDDQ): 1.4V (min) to VDD (max)
• LVCMOS-compatible I/O interface
• Common I/O
• Single Data Rate (SDR) data transfers
• Pipelined (PL) read operations
• Double Late Write (DLW) write operations
• Burst capability with internally controlled Linear Burst address sequencing
• Burst length of two, three, or four, with automatic address wrap
• Full read/write data coherency
• Byte write capability
• Single-ended input clock (CK)
• Data-referenced output clocks (CQ1, CQ1, CQ2, CQ2)
• Selectable output driver impedance via dedicated control pin (ZQ)
• Depth expansion capability (2 or 4 banks) via programmable chip enables (E2, E3, EP2, EP3)
• JTAG boundary scan (subset of IEEE standard 1149.1)
• 209 pin (11x19), 1mm pitch, 14mm x 22mm Ball Grid Array (BGA) package
18Mb 1x1Dp, LVCMOS, rev 1.0
1 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Preliminary
256Kb x 72 Pin Assignment (Top View)
1
2
3
4
5
6
7
8
9
10
11
A
DQg
DQg
A
E2
A
ADV
A
E3
A
DQb
DQb
B
DQg
DQg
Bc
Bg
NC
(x36)
W
A
Bb
Bf
DQb
DQb
C
DQg
DQg
Bh
Bd
NC
(144M)
E1
NC
(x18)
Be
Ba
DQb
DQb
D
DQg
DQg
VSS
NC
NC
MCL
NC
NC
VSS
DQb
DQb
E
DQg
DQc
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQf
DQb
F
DQc
DQc
VSS
VSS
VSS
ZQ
VSS
VSS
VSS
DQf
DQf
G
DQc
DQc
VDDQ
VDDQ
VDD
EP2
VDD
VDDQ
VDDQ
DQf
DQf
H
DQc
DQc
VSS
VSS
VSS
EP3
VSS
VSS
VSS
DQf
DQf
J
DQc
DQc
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQf
DQf
K
CQ2
CQ2
CK
NC
VSS
MCL
VSS
NC
NC
CQ1
CQ1
L
DQh
DQh
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQa
DQa
M
DQh
DQh
VSS
VSS
VSS
MCL
VSS
VSS
VSS
DQa
DQa
N
DQh
DQh
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQa
DQa
P
DQh
DQh
VSS
VSS
VSS
MCL
VSS
VSS
VSS
DQa
DQa
R
DQd
DQh
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQa
DQe
T
DQd
DQd
VSS
NC
NC
MCL
NC
NC
VSS
DQe
DQe
U
DQd
DQd
NC
A
NC
(72M)
A
NC
(36M)
A
NC
DQe
DQe
V
DQd
DQd
A
A
A
A1
A
A
A
DQe
DQe
W
DQd
DQd
TMS
TDI
A
A0
A
TDO
TCK
DQe
DQe
18Mb 1x1Dp, LVCMOS, rev 1.0
2 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Preliminary
512Kb x 36 Pin Assignment (Top View)
1
2
3
4
5
6
7
8
9
10
11
A
NC
NC
A
E2
A
ADV
A
E3
A
DQb
DQb
B
NC
NC
Bc
NC
A
(x36)
W
A
Bb
NC
DQb
DQb
C
NC
NC
NC
Bd
NC
(144M)
E1
NC
(x18)
NC
Ba
DQb
DQb
D
NC
NC
VSS
NC
NC
MCL
NC
NC
VSS
DQb
DQb
E
NC
DQc
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
NC
DQb
F
DQc
DQc
VSS
VSS
VSS
ZQ
VSS
VSS
VSS
NC
NC
G
DQc
DQc
VDDQ
VDDQ
VDD
EP2
VDD
VDDQ
VDDQ
NC
NC
H
DQc
DQc
VSS
VSS
VSS
EP3
VSS
VSS
VSS
NC
NC
J
DQc
DQc
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
NC
NC
K
CQ2
CQ2
CK
NC
VSS
MCL
VSS
NC
NC
CQ1
CQ1
L
NC
NC
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQa
DQa
M
NC
NC
VSS
VSS
VSS
MCL
VSS
VSS
VSS
DQa
DQa
N
NC
NC
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQa
DQa
P
NC
NC
VSS
VSS
VSS
MCL
VSS
VSS
VSS
DQa
DQa
R
DQd
NC
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQa
NC
T
DQd
DQd
VSS
NC
NC
MCL
NC
NC
VSS
NC
NC
U
DQd
DQd
NC
A
NC
(72M)
A
NC
(36M)
A
NC
NC
NC
V
DQd
DQd
A
A
A
A1
A
A
A
NC
NC
W
DQd
DQd
TMS
TDI
A
A0
A
TDO
TCK
NC
NC
18Mb 1x1Dp, LVCMOS, rev 1.0
3 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Preliminary
1Mb x 18 Pin Assignment (Top View)
1
2
3
4
5
6
7
8
9
10
11
A
NC
NC
A
E2
A
ADV
A
E3
A
NC
NC
B
NC
NC
Bb
NC
A
(x36)
W
A
NC
NC
NC
NC
C
NC
NC
NC
NC
NC
(144M)
E1
A
(x18)
NC
Ba
NC
NC
D
NC
NC
VSS
NC
NC
MCL
NC
NC
VSS
NC
NC
E
NC
DQb
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
NC
NC
F
DQb
DQb
VSS
VSS
VSS
ZQ
VSS
VSS
VSS
NC
NC
G
DQb
DQb
VDDQ
VDDQ
VDD
EP2
VDD
VDDQ
VDDQ
NC
NC
H
DQb
DQb
VSS
VSS
VSS
EP3
VSS
VSS
VSS
NC
NC
J
DQb
DQb
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
NC
NC
K
CQ2
CQ2
CK
NC
VSS
MCL
VSS
NC
NC
CQ1
CQ1
L
NC
NC
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQa
DQa
M
NC
NC
VSS
VSS
VSS
MCL
VSS
VSS
VSS
DQa
DQa
N
NC
NC
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQa
DQa
P
NC
NC
VSS
VSS
VSS
MCL
VSS
VSS
VSS
DQa
DQa
R
NC
NC
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQa
NC
T
NC
NC
VSS
NC
NC
MCL
NC
NC
VSS
NC
NC
U
NC
NC
NC
A
NC
(72M)
A
NC
(36M)
A
NC
NC
NC
V
NC
NC
A
A
A
A1
A
A
A
NC
NC
W
NC
NC
TMS
TDI
A
A0
A
TDO
TCK
NC
NC
18Mb 1x1Dp, LVCMOS, rev 1.0
4 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Preliminary
Pin Description
Symbol
Type
Quantity
Description
A
Input
x72 = 16
x36 = 17
x18 = 18
Address Inputs - Registered on the rising edge of CK.
A1, A0
Input
2
DQa, DQb
DQc, DQd
DQe, DQf
DQg, DQh
I/O
CK
Input
1
Input Clock
CQ1, CQ1
CQ2, CQ2
Output
4
Output Clocks
E1
Input
1
Chip Enable Control Input - Registered on the rising edge of CK.
E1 = 0 enables the device to accept read and write commands.
E1 = 1 disables the device.
See the Clock Truth Table section for further information.
E2, E3
Input
2
Programmable Chip Enable Control Inputs - Registered on the rising edge of CK. See
the Clock Truth Table and Depth Expansion sections for further information.
EP2, EP3
Input
2
Programmable Chip Enable Active-Level Select Inputs - These pins must be tied
“high” or “low” at power-up. See the Clock Truth Table and Depth Expansion sections for further information.
ADV
Input
1
Address Advance Control Input - Registered on the rising edge of CK.
ADV = 0 loads a new address and begins a new operation when the device is
enabled.
ADV = 1 increments the address and continues the previous operation when the
device is enabled.
See the Clock Truth Table section for further information.
W
Input
1
Write Enable Control Input - Registered on the rising edge of CK.
W = 0 specifies a write operation when ADV = 0 and the device is enabled.
W = 1 specifies a read operation when ADV = 0 and the device is enabled.
See the Clock Truth Table section for further information.
Ba, Bb, Bc
Bd, Be, Bf
Bg, Bh
Input
x72 = 8
x36 = 4
x18 = 2
ZQ
Input
1
18Mb 1x1Dp, LVCMOS, rev 1.0
x72 = 72
x36 = 36
x18 = 18
Address Inputs 1,0 - Registered on the rising edge of CK. Initialize burst counter.
Data Inputs / Outputs - Registered on the rising edge of CK during write operations.
Driven from the rising edge of CK during read operations.
DQa - indicates Data Byte a
DQb - indicates Data Byte b
DQc - indicates Data Byte c
DQd - indicates Data Byte d
DQe - indicates Data Byte e
DQf - indicates Data Byte f
DQg - indicates Data Byte g
DQh - indicates Data Byte h
Byte Write Enable Control Inputs - Registered on the rising edge of CK.
Ba = 0
specifies write Data Byte a during a write operation
Bb = 0
specifies write Data Byte b during a write operation
Bc = 0
specifies write Data Byte c during a write operation
Bd = 0
specifies write Data Byte d during a write operation
Be = 0
specifies write Data Byte e during a write operation
Bf = 0
specifies write Data Byte f during a write operation
Bg = 0
specifies write Data Byte g during a write operation
Bh = 0
specifies write Data Byte h during a write operation
See the Clock Truth Table section for further information.
Output Impedance Control Input - This pin must be tied “high” or “low” at power-up.
ZQ = 0 selects ~25Ω output impedance
ZQ = 1 selects ~50Ω output impedance
Note: This pin can also be left unconnected. It is weakly pulled “high” internally.
5 / 30
July 19, 2002
SONY® ΣRAM
Symbol
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Type
Quantity
Description
VDD
14
1.8V Core Power Supply - Core supply voltage.
VDDQ
24
Output Power Supply - Output buffer supply voltage.
VSS
30
Ground
TCK
Input
1
JTAG Clock
TMS
Input
1
JTAG Mode Select - Weakly pulled “high” internally.
TDI
Input
1
JTAG Data In - Weakly pulled “high” internally.
TDO
Output
1
JTAG Data Out
MCL
*Input*
5
Must Connect “Low” - May not be actual input pins.
MCH
*Input*
3
Must Connect “High” - May not be actual input pins.
NC
18Mb 1x1Dp, LVCMOS, rev 1.0
x72 = 18
x36 = 57
x18 = 76
Preliminary
No Connect - These pins are true no-connects, i.e. there is no internal chip connection
to these pins. They can be left unconnected or tied directly to VDD, VDDQ, or VSS.
6 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Preliminary
Clock Truth Table
CK
E1 E ADV W B
(tn) (tn) (tn) (tn) (tn)
Previous
Operation
DQ/CQ
(tn)
DQ/CQ
(tn+1)
DQ/CQ
(tn+2)
Bank Deselect
***
Hi-Z
---
Bank Deselect (Continue)
Hi-Z
Hi-Z
---
Deselect
***
Hi-Z/CQ
---
Hi-Z/CQ
Hi-Z/CQ
---
Current Operation
↑
X
F
0
X
X
X
↑
X
X
1
X
X
Bank Deselect
↑
1
T
0
X
X
X
↑
X
X
1
X
X
Deselect
↑
0
T
0
0
T
X
Write
Loads new address
Stores DQx if Bx = 0
***
Hi-Z/CQ
D1/---
↑
0
T
0
0
F
X
Write (Abort)
Loads new address
No data stored
***
Hi-Z/CQ
X/---
↑
X
X
1
X
T
Write
Write Continue
Increments address by 1
Stores DQx if Bx = 0
Hi-Z/CQ
D1/CQ
D2/---
↑
X
X
1
X
F
Write
Write Continue (Abort)
Increments address by 1
No data stored
Hi-Z/CQ
D1/CQ
X/---
↑
0
T
0
1
X
X
***
Q1/CQ
---
↑
X
X
1
X
X
Read
Q1/CQ
Q2/CQ
---
Deselect (Continue)
Read
Loads new address
Read Continue
Increments address by 1
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. “***” indicates that the DQ input requirement or output state and the CQ output state are determined by the previous operation.
3. “---” indicates that the DQ input requirement or output state and the CQ output state are determined by the next operation.
4. If E2 = EP2 and E3 = EP3 then E = “T” else E = “F”.
5. If one or more Bx = 0 then B = “T” else B = “F”.
6. DQs are tri-stated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.
7. CQs are tri-stated in response to Bank Deselect commands only, one full cycle after the command is sampled.
8. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four
(4) distinct pieces of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial external (base) address.
18Mb 1x1Dp, LVCMOS, rev 1.0
7 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Preliminary
State Diagram
X,F,0,X or X,X,1,X
Bank
Deselect
0,T,0,1
0,T,0,0
1,T,0,X
X,F,0,X
Deselect
0,T,0,1
0,T,0,0
1,T,0,X or X,X,1,X
1,T,0,X
1,T,0,X
0,T,0,0
Read
Write
0,T,0,1
X,F,0,X
0,T,0,1
X,X,1,X
X,X,1,X
0,T,0,1
1,T,0,X
X,F,0,X
Read
Continue
X,F,0,X
0,T,0,0
0,T,0,0
0,T,0,0 0,T,0,1
X,X,1,X
Write
Continue
1,T,0,X
X,F,0,X
X,X,1,X
Notes:
1. The notation “X,X,X,X” controlling the state transitions above indicate the states of inputs E1, E, ADV, and W respectively.
2. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
3. If E2 = EP2 and E3 = EP3 then E = “T” else E = “F”.
18Mb 1x1Dp, LVCMOS, rev 1.0
8 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Preliminary
•Burst (Continue) Operations
Burst operations follow the Linear Burst address sequence depicted in the table below:
A(1:0)
Sequence Key
1st (Base) Address
00
01
10
11
A1, A0
2nd Address
01
10
11
00
(A1 xor A0), A0
3rd Address
10
11
00
01
A1, A0
4th Address
11
00
01
10
(A1 xor A0), A0
Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four
(4) distinct pieces of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial external (base) address.
•Depth Expansion
Depth expansion in these devices is supported via programmable chip enables E2 and E3. The active levels of E2 and E3 are
programmable through the static inputs EP2 and EP3 respectively. When EP2 is tied “high”, E2 functions as an active-high
input. When EP2 is tied “low”, E2 functions as an active-low input. Similarly, when EP3 is tied “high”, E3 functions as an
active-high input. And, when EP3 is tied “low”, E3 functions as an active-low input.
The programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By
programming E2 and E3 of four devices in a binary sequence (00, 01, 10, 11), and by driving E2 and E3 with external address
signals, the four devices can be made to look like one larger device.
When these devices are deselected via chip enable E1, the output clocks continue to toggle. However, when these devices
are deselected via programmable chip enables E2 or E3, the output clocks are forced to a Hi-Z state. See the Clock Truth
Table for further information.
•Output Driver Impedance Control
The impedance of the data and clock output drivers in these devices can be controlled via the static input ZQ. When ZQ is
tied “low”, output driver impedance is set to ~25Ω. When ZQ is tied “high” or left unconnected, output driver impedance is
set to ~50Ω. See the DC Electrical Characteristics section for further information.
•Power-Up Sequence
For reliability purposes, Sony recommends that power supplies power up in the following sequence: VSS, VDD, VDDQ, and
Inputs. VDDQ should never exceed VDD. If this power supply sequence cannot be met, a large bypass diode may be required
between VDD and VDDQ. Please contact Sony Memory Application Department for further information.
18Mb 1x1Dp, LVCMOS, rev 1.0
9 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Preliminary
•Absolute Maximum Ratings
Parameter
Symbol
Rating
Units
Supply Voltage
VDD
-0.5 to +2.5
V
Output Supply Voltage
VDDQ
-0.5 to +2.3
V
VIN
-0.5 to VDDQ+0.5 (2.3V max)
V
Input Voltage (EP2, EP3, MCL, MCH, ZQ)
VMIN
-0.5 to VDD+0.5 (2.5V max)
V
Input Voltage (TCK, TMS, TDI)
VTIN
-0.5 to VDD+0.5 (2.5V max)
V
Operating Temperature
TA
0 to 85
°C
Junction Temperature
TJ
0 to 110
°C
Storage Temperature
TSTG
-55 to 150
°C
Input Voltage (Address, Control, Data, Clock)
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
•BGA Package Thermal Characteristics
Parameter
Junction to Case Temperature
Symbol
Rating
Units
ΘJC
3.6
°C/W
•I/O Capacitance
(TA = 25oC, f = 1 MHz)
Parameter
Input Capacitance
Symbol
Test conditions
Min
Max
Units
Address
CIN
VIN = 0V
---
3.5
pF
Control
CIN
VIN = 0V
---
3.5
pF
CK Clock
CKIN
VKIN = 0V
---
4.0
pF
Data
COUT
VOUT = 0V
---
4.5
pF
CQ Clock
COUT
VOUT = 0V
---
4.5
pF
Output Capacitance
Note: These parameters are sampled and are not 100% tested.
18Mb 1x1Dp, LVCMOS, rev 1.0
10 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
•DC Recommended Operating Conditions
Parameter
Preliminary
(VSS = 0V, TA = 0 to 85oC)
Symbol
Min
Typ
Max
Units
Notes
Supply Voltage
VDD
1.7
1.8
1.95
V
Output Supply Voltage
VDDQ
1.4
---
VDD
V
Input High Voltage
(Address, Control, Data, Clock)
VIH
VDDQ/2 + 0.3
---
VDDQ + 0.3
V
1
Input Low Voltage
(Address, Control, Data, Clock)
VIL
-0.3
---
VDDQ/2 - 0.3
V
2
Input High Voltage
(EP2, EP3, MCH, ZQ)
VMIH
VDDQ/2 + 0.4
---
VDD + 0.3
V
Input Low Voltage
(EP2, EP3, MCL, ZQ)
VMIL
-0.3
---
VDDQ/2 - 0.4
V
1. VIH (max) AC = VDDQ + 0.9V for pulse widths less than one-quarter of the cycle time (tCYC/4).
2. VIL (min) AC = -0.9V for pulse widths less than one-quarter of the cycle time (tCYC/4).
18Mb 1x1Dp, LVCMOS, rev 1.0
11 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
•DC Electrical Characteristics
Parameter
Symbol
Input Leakage Current
(Address, Control, Clock)
ILI
Input Leakage Current
(EP2, EP3)
Preliminary
(VDD = 1.8V ± 0.1V, VSS = 0V, TA = 0 to 85oC)
Test Conditions
Min
Typ
Max
Units
VIN = VSS to VDDQ
-5
---
5
uA
IMLI1
VMIN = VSS to VDD
-10
---
10
uA
Input Leakage Current
(MCH)
IMLI2
VMIN = VMIH (min) to VDD
-10
---
10
uA
Input Leakage Current
(MCL)
IMLI3
VMIN = VSS to VMIL (max)
-10
---
10
uA
VOUT = VSS to VDDQ
-10
---
10
uA
Output Leakage Current
ILO
Average Power Supply
Operating Current (x72)
IDD-33
IDD-4
IDD-5
IOUT = 0 mA
VIN = VIH or VIL
-------
-------
750
650
550
mA
Average Power Supply
Operating Current (x36)
IDD-33
IDD-4
IDD-5
IOUT = 0 mA
VIN = VIH or VIL
-------
-------
580
500
420
mA
Average Power Supply
Operating Current (x18)
IDD-33
IDD-4
IDD-5
IOUT = 0 mA
VIN = VIH or VIL
-------
-------
490
430
380
mA
Power Supply Deselect
Operating Current
IDD2
IOUT = 0 mA
VIN = VIH or VIL
---
---
250
mA
Output High Voltage
VOH
IOH = -6.0 mA
ZQ = VIH
VDDQ - 0.4
---
---
V
Output Low Voltage
VOL
IOL = 6.0 mA
ZQ = VIH
---
---
0.4
V
VOH, VOL = VDDQ/2
ZQ = VIL
17
25
33
Ω
VOH, VOL = VDDQ/2
ZQ = VIH
35
50
65
Ω
Output Driver Impedance
18Mb 1x1Dp, LVCMOS, rev 1.0
ROUT
12 / 30
Notes
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
•AC Electrical Characteristics
(VDD = 1.8V ± 0.1V, VSS = 0V, TA = 0 to 85oC)
-33
Parameter
Preliminary
-4
-5
Symbol
Units Notes
Min
Max
Min
Max
Min
Max
Input Clock Cycle Time
tKHKH
3.3
---
4.0
---
5.0
---
ns
Input Clock High Pulse Width
tKHKL
1.3
---
1.5
---
2.0
---
ns
Input Clock Low Pulse Width
tKLKH
1.3
---
1.5
---
2.0
---
ns
Address Input Setup Time
tAVKH
0.7
---
0.8
---
1.0
---
ns
Address Input Hold Time
tKHAX
0.4
---
0.5
---
0.5
---
ns
Control Input Setup Time
tBVKH
0.7
---
0.8
---
1.0
---
ns
1
Control Input Hold Time
tKHBX
0.4
---
0.5
---
0.5
---
ns
1
Data Input Setup Time
tDVKH
0.7
---
0.8
---
1.0
---
ns
Data Input Hold Time
tKHDX
0.4
---
0.5
---
0.5
---
ns
Input Clock High to Output Data Valid
tKHQV
---
1.8
---
2.1
---
2.3
ns
Input Clock High to Output Data Hold
tKHQX
0.5
---
0.5
---
0.5
---
ns
2
Input Clock High to Output Data Low-Z
tKHQX1
0.5
---
0.5
---
0.5
---
ns
2,3
Input Clock High to Output Data High-Z
tKHQZ
---
1.8
---
2.1
---
2.3
ns
2,3
Input Clock High to Output Clock High
tKHCH
0.5
1.8
0.5
2.1
0.5
2.3
ns
Input Clock High to Output Clock Low-Z
tKHCX1
0.5
---
0.5
---
0.5
---
ns
2,3
Input Clock High to Output Clock High-Z
tKHCZ
---
1.8
---
2.1
---
2.3
ns
2,3
Output Clock High to Output Data Valid
tCHQV
---
0.4
---
0.5
---
0.6
ns
2
Output Clock High to Output Data Hold
tCHQX
-0.4
---
-0.5
---
-0.6
---
ns
2
Output Clock High Pulse Width
tCHCL
tKHKL ± 0.2
tKHKL ± 0.2
tKHKL ± 0.2
ns
2
Output Clock Low Pulse Width
tCLCH
tKLKH ± 0.2
tKLKH ± 0.2
tKLKH ± 0.2
ns
2
All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal, unless otherwise noted.
1. These parameters apply to control inputs E1, E2, E3, ADV, W, and Bx.
2. These parameters are guaranteed by design through extensive corner lot characterization.
3. These parameters are measured at ± 50mV from steady state voltage.
18Mb 1x1Dp, LVCMOS, rev 1.0
13 / 30
July 19, 2002
SONY® ΣRAM
Preliminary
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
•AC Electrical Characteristics (Note)
The two AC timing parameters listed below are tested according to specific combinations of Output Clocks (CQs) and Output Data (DQs):
1. tCHQV -
Output Clock High to Output Data Valid (max)
2. tCHQX -
Output Clock High to Output Data Hold (min)
The specific CQ / DQ combinations are defined as follows:
256Kb x 72
512Kb x 36
CQs
DQs
CQs
1K, 2K
1A, 2A, 1B, 2B, 1C, 2C,
1D, 2D, 1E, 2E, 1F, 2F,
1G, 2G, 1H, 2H, 1J, 2J, 1L,
2L, 1M, 2M, 1N, 2N, 1P,
2P, 2R, 1R, 1T, 2T,
1U, 2U, 1V, 2V, 1W, 2W
1K, 2K
10K, 11K 10A, 11A, 10B, 11B,
10C, 11C, 10D, 11D, 11E,
10E, 10F, 11F, 10G, 11G,
10H, 11H, 10J, 11J,
10L, 11L, 10M, 11M,
10N, 11N, 10P, 11P, 10R,
11R, 10T, 11T, 10U, 11U,
10V, 11V, 10W, 11W
18Mb 1x1Dp, LVCMOS, rev 1.0
DQs
2E, 1F, 2F, 1G, 2G, 1H,
2H, 1J, 2J, 1R, 1T, 2T,
1U, 2U, 1V, 2V, 1W, 2W
10K, 11K 10A, 11A, 10B, 11B,
10C, 11C, 10D, 11D, 11E,
10L, 11L, 10M, 11M,
10N, 11N, 10P, 11P, 10R
14 / 30
1Mb x 18
CQs
1K, 2K
DQs
2E, 1F, 2F, 1G, 2G, 1H,
2H, 1J, 2J
10K, 11K 10L, 11L, 10M, 11M,
10N, 11N, 10P, 11P, 10R
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
•AC Test Conditions (VDDQ = 1.8V)
Parameter
Preliminary
(VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V, TA = 0 to 85°C)
Symbol
Conditions
Units
Input High Level
VIH
1.4
V
Input Low Level
VIL
0.4
V
Input Rise & Fall Time
2.0
V/ns
Input Reference Level
0.9
V
Clock Input High Voltage
VKIH
1.4
V
Clock Input Low Voltage
VKIL
0.4
V
Clock Input Rise & Fall Time
2.0
V/ns
Clock Input Reference Level
0.9
V
Output Reference Level
0.9
V
Output Load Conditions
ZQ = VIH
Notes
See Figure 1
below
Figure 1: AC Test Output Load (VDDQ = 1.8V)
0.9 V
16.7 Ω
50 Ω
50 Ω
5 pF
DQ
16.7 Ω
0.9 V
16.7 Ω
50 Ω
50 Ω
5 pF
18Mb 1x1Dp, LVCMOS, rev 1.0
15 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
•AC Test Conditions (VDDQ = 1.5V)
Parameter
Preliminary
(VDD = 1.8V ± 0.1V, VDDQ = 1.5V ± 0.1V, TA = 0 to 85°C)
Symbol
Conditions
Units
Input High Level
VIH
1.25
V
Input Low Level
VIL
0.25
V
Input Rise & Fall Time
2.0
V/ns
Input Reference Level
0.75
V
Clock Input High Voltage
VKIH
1.25
V
Clock Input Low Voltage
VKIL
0.25
V
Clock Input Rise & Fall Time
2.0
V/ns
Clock Input Reference Level
0.75
V
Output Reference Level
0.75
V
Output Load Conditions
ZQ = VIH
Notes
See Figure 2
below
Figure 2: AC Test Output Load (VDDQ = 1.5V)
0.75 V
16.7 Ω
50 Ω
50 Ω
5 pF
DQ
16.7 Ω
0.75 V
16.7 Ω
50 Ω
50 Ω
5 pF
18Mb 1x1Dp, LVCMOS, rev 1.0
16 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Preliminary
One Bank Read-Write-Read Timing Diagram
Figure 3
Read
Read
Continue
Read
Deselect
Write
Continue
Write
Write
Deselect
Read
Deselect
Deselect
(Continue)
CK
tAVKH tKHAX
A A1
A2
tKHKH
A3
tKHKL tKLKH
A4
A5
tBVKH tKHBX
E1
ADV
W
Bx
tKHQV
tKHQZ
tKHQX
DQ
Q11
Q12
tKHQX1
tDVKH tKHDX
Q21
D31
tCHQX
D32
D41
Q51
tKHCH tCHCL tCLCH
tCHQV
CQ
CQ
Note: In the diagram above, a Deselect operation is inserted between Read and Write operations to control the data bus transition from
output to input. Similarly, a Deselect operation is inserted between Write and Read operations to control the data bus transition from input
to output. This depiction is for clarity purposes only. It is NOT a requirement. Depending on the application, these Deselect operations
may not be necessary.
Note: E1 = EP1 and E2 = EP2 in this example (not shown).
18Mb 1x1Dp, LVCMOS, rev 1.0
17 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Preliminary
Two Bank Read-Write-Read Timing Diagram
Figure 4
B1:
B2:
Read
B-Deselect B-Deselect B-Deselect B-Deselect
R-Continue B-Deselect Deselect B-Deselect B-Deselect
Write
B-Deselect B-Deselect
Read
B-Deselect
Write
W-Continue B-Deselect Deselect
Read
Deselect
Deselect
CK
A A1
A2
A3
A4
A5
E2
E1
ADV
W
Bx
DQ (B1)
Q11
Q12
D41
D31
Q21
DQ (B2)
tKHCZ
D32
Q51
tKHCX1
CQ (B1)
CQ (B1)
CQ (B2)
CQ (B2)
Note: In the diagram above, a Deselect operation is inserted between Read and Write operations to control the data bus transition from
output to input. Similarly, a Deselect operation is inserted between Write and Read operations to control the data bus transition from input
to output. This depiction is for clarity purposes only. It is NOT a requirement. Depending on the application, these Deselect operations
may not be necessary.
Note: Bank 1 EP1 = “low”, Bank 2 EP1 “high”, and Bank 1 and Bank 2 E2 = EP2 in this example (not shown).
18Mb 1x1Dp, LVCMOS, rev 1.0
18 / 30
July 19, 2002
SONY® ΣRAM
Preliminary
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
•Test Mode Description
These devices provide a JTAG Test Access Port (TAP) and Boundary Scan interface using a limited set of IEEE std. 1149.1
functions. This test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller, etc.), SRAMs, other components, and the printed circuit board.
In conformance with a subset of IEEE std. 1149.1, these devices contain a TAP Controller and four TAP Registers. The TAP
Registers consist of one Instruction Register and three Data Registers (ID, Bypass, and Boundary Scan Registers).
The TAP consists of the following four signals:
TCK:
TMS:
TDI:
TDO:
Test Clock
Test Mode Select
Test Data In
Test Data Out
Induces (clocks) TAP Controller state transitions.
Inputs commands to the TAP Controller. Sampled on the rising edge of TCK.
Inputs data serially to the TAP Registers. Sampled on the rising edge of TCK.
Outputs data serially from the TAP Registers. Driven from the falling edge of TCK.
Disabling the TAP
When JTAG is not used, TCK should be tied “low” to prevent clocking the SRAM. TMS and TDI should either be tied “high”
through a pull-up resistor or left unconnected. TDO should be left unconnected.
Note: Operation of the TAP does not disrupt normal SRAM operation except when the EXTEST-A or SAMPLE-Z instruction is selected. Consequently, TCK, TMS, and TDI can be controlled any number of ways without adversely affecting the
functionality of the device.
JTAG DC Recommended Operating Conditions
(VDD = 1.8V ± 0.1V, TA = 0 to 85°C)
Parameter
Symbol
Test Conditions
Min
Max
Units
JTAG Input High Voltage (TCK, TMS, TDI)
VTIH
---
VDD/2 + 0.3
VDD + 0.3
V
JTAG Input Low Voltage (TCK, TMS, TDI)
VTIL
---
-0.3
VDD/2 - 0.3
V
JTAG Output High Voltage (TDO)
VTOH
ITOH = -100uA
VDD - 0.1
---
V
JTAG Output Low Voltage (TDO)
VTOL
ITOL = 100uA
---
0.1
V
JTAG Output High Voltage (TDO)
VTOH
ITOH = -8mA
VDD - 0.4
---
V
JTAG Output Low Voltage (TDO)
VTOL
ITOL = 8mA
---
0.4
V
JTAG Input Leakage Current
ITLI
VTIN = VSS to VDD
-20
10
uA
JTAG Output Leakage Current
ITLO
VTOUT = VSS to VDD
-10
10
uA
(VDD = 1.8V ± 0.1V, TA = 0 to 85°C)
JTAG AC Test Conditions
Parameter
Symbol
Conditions
Units
JTAG Input High Level
VTIH
1.8
V
JTAG Input Low Level
VTIL
0.0
V
JTAG Input Rise & Fall Time
1.0
V/ns
JTAG Input Reference Level
0.9
V
JTAG Output Reference Level
0.9
V
JTAG Output Load Condition
18Mb 1x1Dp, LVCMOS, rev 1.0
Notes
See Fig. 1 (page 15)
19 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Preliminary
JTAG AC Electrical Characteristics
Parameter
Symbol
Min
Max
Units
TCK Cycle Time
tTHTH
50
ns
TCK High Pulse Width
tTHTL
20
ns
TCK Low Pulse Width
tTLTH
20
ns
TMS Setup Time
tMVTH
5
ns
TMS Hold Time
tTHMX
5
ns
TDI Setup Time
tDVTH
5
ns
TDI Hold Time
tTHDX
5
ns
Capture Setup Time (Address, Control, Data, Clock)
tCS
5
ns
Capture Hold Time (Address, Control, Data, Clock)
tCH
5
ns
TCK Low to TDO Valid
tTLQV
TCK Low to TDO Hold
tTLQX
10
0
ns
ns
JTAG Timing Diagram
Figure 5
tTHTL
tTLTH
tTHTH
TCK
tMVTH
tTHMX
TMS
tDVTH tTHDX
TDI
tTLQV
tTLQX
TDO
18Mb 1x1Dp, LVCMOS, rev 1.0
20 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Preliminary
TAP Controller
The TAP Controller is a 16-state state machine that controls access to the various TAP Registers and executes the operations
associated with each TAP Instruction (see Figure 7 below). State transitions are controlled by TMS and occur on the rising
edge of TCK.
The TAP Controller enters the “Test-Logic Reset” state in one of two ways:
1. At power up.
2. When a logic “1” is applied to TMS for at least 5 consecutive rising edges of TCK.
The TDI input receiver is sampled only when the TAP Controller is in either the “Shift-IR” state or the “Shift-DR” state.
The TDO output driver is active only when the TAP Controller is in either the “Shift-IR” state or the “Shift-DR” state.
TAP Controller State Diagram
Figure 6
1
Test-Logic Reset
0
0
Run-Test / Idle
1
Select DR-Scan
1
Select IR-Scan
0
1
0
1
Capture-DR
Capture-IR
0
0
0
Shift-DR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1
0
Exit2-IR
1
18Mb 1x1Dp, LVCMOS, rev 1.0
0
21 / 30
0
1
Update-DR
1
0
Pause-IR
1
Exit2-DR
0
Shift-IR
1
1
1
Update-IR
1
0
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Preliminary
TAP Registers
TAP Registers are serial shift registers that capture serial input data (from TDI) on the rising edge of TCK, and drive serial
output data (to TDO) on the subsequent falling edge of TCK. They are divided into two groups: “Instruction Registers” (IR),
which are manipulated via the “IR” states in the TAP Controller, and “Data Registers” (DR), which are manipulated via the
“DR” states in the TAP Controller.
Instruction Register (IR - 3 bits)
The Instruction Register stores the various TAP Instructions supported by these devices. It is loaded with the IDCODE instruction at power-up, and when the TAP Controller is in the “Test-Logic Reset” and “Capture-IR” states. It is inserted between TDI and TDO when the TAP Controller is in the “Shift-IR” state, at which time it can be loaded with a new instruction.
However, newly loaded instructions are not executed until the TAP Controller has reached the “Update-IR” state.
The Instruction Register is 3 bits wide, and is encoded as follows:
Code
(2:0)
Instruction
Description
000
EXTEST-A
Loads the individual logic states of all signals composing the SRAM’s I/O ring into the
Boundary Scan Register when the TAP Controller is in the “Capture-DR” state, and inserts the
B-Scan Register between TDI and TDO when the TAP Controller is in the “Shift-DR” state.
Also enables the SRAM’s data and clock output drivers, and moves the contents of the B-Scan
Register associated with the data and clock output signals to the input side of the SRAM’s output register. The SRAM’s input clock can then be used to transfer the B-Scan Register contents
directly to the data and clock output pins (the input clock controls the SRAM’s output register). Note that newly captured and/or shifted B-Scan Register contents do not appear at the
input side of the SRAM’s output register until the TAP Controller has reached the “UpdateDR” state.
See the Boundary Scan Register description for more information.
001
IDCODE
Loads a predefined device- and manufacturer-specific identification code into the ID Register
when the TAP Controller is in the “Capture-DR” state, and inserts the ID Register between
TDI and TDO when the TAP Controller is in the “Shift-DR” state.
See the ID Register description for more information.
010
SAMPLE-Z
Loads the individual logic states of all signals composing the SRAM’s I/O ring into the
Boundary Scan Register when the TAP Controller is in the “Capture-DR” state, and inserts the
B-Scan Register between TDI and TDO when the TAP Controller is in the “Shift-DR” state.
Also disables the SRAM’s data and clock output drivers.
See the Boundary Scan Register description for more information.
011
PRIVATE
Do not use. Reserved for manufacturer use only.
100
SAMPLE
Loads the individual logic states of all signals composing the SRAM’s I/O ring into the
Boundary Scan Register when the TAP Controller is in the “Capture-DR” state, and inserts the
Boundary Scan Register between TDI and TDO when the TAP Controller is in the “Shift-DR”
state.
See the Boundary Scan Register description for more information.
101
PRIVATE
Do not use. Reserved for manufacturer use only.
110
PRIVATE
Do not use. Reserved for manufacturer use only.
111
BYPASS
Loads a logic “0” into the Bypass Register when the TAP Controller is in the “Capture-DR”
state, and inserts the Bypass Register between TDI and TDO when the TAP Controller is in the
“Shift-DR” state.
See the Bypass Register description for more information.
Bit 0 is the LSB of the Instruction Register, and Bit 2 is the MSB. When the Instruction Register is selected, TDI serially
shifts data into the MSB, and the LSB serially shifts data out through TDO.
18Mb 1x1Dp, LVCMOS, rev 1.0
22 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Preliminary
Bypass Register (DR - 1 bit)
The Bypass Register is one bit wide, and provides the minimum length serial path between TDI and TDO. It is loaded with
a logic “0” when the BYPASS instruction has been loaded in the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted between TDI and TDO when the BYPASS instruction has been loaded into the Instruction Register and the TAP Controller is in the “Shift-DR” state.
ID Register (DR - 32 bits)
The ID Register is loaded with a predetermined device- and manufacturer-specific identification code when the IDCODE
instruction has been loaded into the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted
between TDI and TDO when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller
is in the “Shift-DR” state.
The ID Register is 32 bits wide, and is encoded as follows:
Device
Revision Number
(31:28)
Part Number
(27:12)
Sony ID
(11:1)
Start Bit
(0)
256Kb x 72
xxxx
0000 0000 0101 1000
0000 1110 001
1
512Kb x 36
xxxx
0000 0000 0101 1110
0000 1110 001
1
1Mb x 18
xxxx
0000 0000 0110 0100
0000 1110 001
1
Bit 0 is the LSB of the ID Register, and Bit 31 is the MSB. When the ID Register is selected, TDI serially shifts data into the
MSB, and the LSB serially shifts data out through TDO.
Boundary Scan Register (DR - 123 bits for x72, 84 bits for x36, 65 bits for x18)
The Boundary Scan Register is equal in length to the number of active signal connections to the SRAM (excluding the TAP
pins) plus a number of place holder locations reserved for functional and/or density upgrades. It is loaded with the individual
logic states of all signals composing the SRAM’s I/O ring when the EXTEST-A, SAMPLE, or SAMPLE-Z instruction has
been loaded into the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted between TDI and
TDO when the EXTEST-A, SAMPLE, or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP
Controller is in the “Shift-DR” state.
The Boundary Scan Register contains the following bits:
256Kb x 72
512Kb x 36
1Mb x 18
DQx
72
DQx
36
DQx
18
A, A1, A0
18
A, A1, A0
19
A, A1, A0
20
CK
1
CK
1
CK
1
CQ1, CQ2, CQ1, CQ2
4
CQ1, CQ2, CQ1, CQ2
4
CQ1, CQ2, CQ1, CQ2
4
E1, ADV, W, Bx
11
E1, ADV, W, Bx
7
E1, ADV, W, Bx
5
E2, E3, EP2, EP3
4
E2, E3, EP2, EP3
4
E2, E3, EP2, EP3
4
ZQ
1
ZQ
1
ZQ
1
Place Holder
12
Place Holder
12
Place Holder
12
18Mb 1x1Dp, LVCMOS, rev 1.0
23 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Preliminary
Boundary Scan Register Bit Order Assignments
The tables below depict the order in which the bits are arranged in the Boundary Scan Register. Bit 1 is the LSB and bit 123
(for x72) or bit 84 (for x36) or bit 65 (for x18) is the MSB. When the Boundary Scan Register is selected, TDI serially shifts
data into the MSB, and the LSB serially shifts data out through TDO.
256Kb x 72
Bit
Signal
Pad
Bit
Signal
Pad
Bit
Signal
Pad
Bit
Signal
Pad
1
NC (1)
5C
36
DQf
11G
71
DQg
1A
106
DQd
2V
2
NC (1)
5U
37
DQf
10F
72
DQg
1B
107
DQd
1V
3
(1)
NC
7U
38
DQf
11F
73
DQg
2B
108
DQd
1W
MCL
(1)
6D
39
DQf
10E
74
DQg
1C
109
DQd
2W
5
MCL
(1)
6K
40
DQb
11E
75
DQg
2C
110
MCH
6J
6
MCL (1)
6P
41
DQb
10D
76
DQg
1D
111
A
3V
7
MCL (1)
6T
42
DQb
11D
77
DQg
2D
112
A
4V
8
(2)
6N
43
DQb
10C
78
DQg
1E
113
A
4U
4
MCH
9
MCL
6M
44
DQb
11C
79
DQc
2E
114
A
5V
10
MCH
6L
45
DQb
10B
80
DQc
1F
115
A
6U
11
DQe
10W
46
DQb
11B
81
DQc
2F
116
A
5W
12
DQe
11W
47
DQb
11A
82
DQc
1G
117
A0
6W
13
DQe
11V
48
DQb
10A
83
DQc
2G
118
A1
6V
14
DQe
10V
49
Bf
9B
84
DQc
1H
119
A
7V
15
DQe
11U
50
Ba
9C
85
DQc
2H
120
A
8V
16
DQe
10U
51
Bb
8B
86
DQc
1J
121
A
7W
17
DQe
11T
52
Be
8C
87
DQc
2J
122
A
8U
18
DQe
10T
53
EP3
6H
88
CQ2
1K
123
A
9V
19
DQe
11R
54
EP2
6G
89
CK
3K
20
DQa
21
22
NC
(1)
10R
55
A
9A
90
DQa
11P
56
E3
8A
91
CQ2
2K
DQa
10P
57
A
7B
92
DQh
2L
22
DQa
11N
58
A
7A
93
DQh
1L
24
DQa
10N
59
W
6B
94
DQh
2M
25
DQa
11M
60
ADV
6A
95
DQh
1M
26
DQa
10M
61
E1
6C
96
DQh
2N
27
DQa
11L
62
A
5A
97
DQh
1N
28
DQa
10L
63
E2
4A
98
DQh
2P
29
CQ1
11K
64
A
3A
99
DQh
1P
30
CQ1
10K
65
ZQ
6F
100
DQh
2R
31
DQf
10J
66
Bd
4C
101
DQd
1R
32
DQf
11J
67
Bg
4B
102
DQd
2T
33
DQf
10H
68
Bh
3C
103
DQd
1T
34
DQf
11H
69
Bc
3B
104
DQd
2U
35
DQf
10G
70
DQg
2A
105
DQd
1U
4K
Note 1: NC and MCL pins at pad locations 5C, 5U, 7U, 6D, 6K, 6P, 6T, and 4K are connected to VSS internally, regardless
of pin connection externally.
Note 2: MCH pin at pad location 6N is connected to VDD internally, regardless of pin connection externally.
18Mb 1x1Dp, LVCMOS, rev 1.0
24 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Preliminary
.
512Kb x 36
Bit
Signal
Pad
Bit
Signal
Pad
Bit
Signal
1
Pad
NC (1)
5C
36
E3
8A
71
MCH
6J
2
NC (1)
5U
37
A
7B
72
A
3V
3
NC (1)
7U
38
A
7A
73
A
4V
MCL
(1)
6D
39
W
6B
74
A
4U
5
MCL
(1)
6K
40
ADV
6A
75
A
5V
6
MCL (1)
6P
41
E1
6C
76
A
6U
7
MCL
(1)
6T
42
A
5A
77
A
5W
MCH
(2)
6N
43
A
5B
78
A0
6W
4
8
9
MCL
6M
44
E2
4A
79
A1
6V
10
MCH
6L
45
A
3A
80
A
7V
11
DQa
10R
46
ZQ
6F
81
A
8V
12
DQa
11P
47
Bd
4C
82
A
7W
13
DQa
10P
48
Bc
3B
83
A
8U
14
DQa
11N
49
DQc
2E
84
A
9V
15
DQa
10N
50
DQc
1F
16
DQa
11M
51
DQc
2F
17
DQa
10M
52
DQc
1G
18
DQa
11L
53
DQc
2G
19
DQa
10L
54
DQc
1H
20
CQ1
11K
55
DQc
2H
21
CQ1
10K
56
DQc
1J
22
DQb
11E
57
DQc
2J
22
DQb
10D
58
CQ2
1K
24
DQb
11D
59
CK
3K
NC
(1)
25
DQb
10C
60
26
DQb
11C
61
CQ2
2K
27
DQb
10B
62
DQd
1R
28
DQb
11B
63
DQd
2T
29
DQb
11A
64
DQd
1T
30
DQb
10A
65
DQd
2U
31
Ba
9C
66
DQd
1U
32
Bb
8B
67
DQd
2V
4K
33
EP3
6H
68
DQd
1V
34
EP2
6G
69
DQd
1W
35
A
9A
70
DQd
2W
Note 1: NC and MCL pins at pad locations 5C, 5U, 7U, 6D, 6K, 6P, 6T, and 4K are connected to VSS internally, regardless
of pin connection externally.
Note 2: MCH pin at pad location 6N is connected to VDD internally, regardless of pin connection externally.
18Mb 1x1Dp, LVCMOS, rev 1.0
25 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Preliminary
.
1Mb x 18
Bit
Signal
1
NC (1)
5C
2
NC (1)
5U
3
(1)
NC
Pad
Bit
Signal
Pad
36
A
3A
37
ZQ
6F
7U
38
Bb
3B
MCL
(1)
6D
39
DQb
2E
5
MCL
(1)
6K
40
DQb
1F
6
MCL (1)
6P
41
DQb
2F
7
MCL
(1)
6T
42
DQb
1G
MCH
(2)
6N
43
DQb
2G
4
8
9
MCL
6M
44
DQb
1H
10
MCH
6L
45
DQb
2H
11
DQa
10R
46
DQb
1J
12
DQa
11P
47
DQb
2J
13
DQa
10P
48
CQ2
1K
14
DQa
11N
49
CK
3K
15
DQa
10N
50
NC (1)
4K
16
DQa
11M
51
CQ2
2K
17
DQa
10M
52
MCH
6J
18
DQa
11L
53
A
3V
19
DQa
10L
54
A
4V
20
CQ1
11K
55
A
4U
21
CQ1
10K
56
A
5V
22
Ba
9C
57
A
6U
22
EP3
6H
58
A
5W
24
EP2
6G
59
A0
6W
25
A
9A
60
A1
6V
26
E3
8a
61
A
7V
27
A
7C
62
A
8V
28
A
7B
63
A
7W
29
A
7A
64
A
8U
30
W
6B
65
A
9V
31
ADV
6A
32
E1
6C
33
A
5A
34
A
5B
35
E2
4A
Note 1: NC and MCL pins at pad locations 5C, 5U, 7U, 6D, 6K, 6P, 6T, and 4K are connected to VSS internally, regardless
of pin connection externally.
Note 2: MCH pin at pad location 6N is connected to VDD internally, regardless of pin connection externally.
18Mb 1x1Dp, LVCMOS, rev 1.0
26 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Preliminary
•Ordering Information
VDD
I/O Type
Configuration
Speed
(Cycle Time / Data Access Time)
CXK79M72C165GB-33
1.8V
LVCMOS
256Kb x 72
3.3ns / 1.8ns
CXK79M72C165GB-4
1.8V
LVCMOS
256Kb x 72
4.0ns / 2.1ns
CXK79M72C165GB-5
1.8V
LVCMOS
256Kb x 72
5.0ns / 2.3ns
CXK79M36C165GB-33
1.8V
LVCMOS
512Kb x 36
3.3ns / 1.8ns
CXK79M36C165GB-4
1.8V
LVCMOS
512Kb x 36
4.0ns / 2.1ns
CXK79M36C165GB-5
1.8V
LVCMOS
512Kb x 36
5.0ns / 2.3ns
CXK79M18C165GB-33
1.8V
LVCMOS
1Mb x 18
3.3ns / 1.8ns
CXK79M18C165GB-4
1.8V
LVCMOS
1Mb x 18
4.0ns / 2.1ns
CXK79M18C165GB-5
1.8V
LVCMOS
1Mb x 18
5.0ns / 2.3ns
Part Number
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license
by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
18Mb 1x1Dp, LVCMOS, rev 1.0
27 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Preliminary
•(11x19) 209 Pin BGA Package Dimensions
209PIN BGA (PLASTIC)
2.0 ± 0.3
14.0
0.30
S
A
13.0
0
.
C1
3-
x4
0.20
C1
.
S
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
S
5
0.15
B
2.0
0.35
21.0
22.0
0.30 S B
7
1.
C
4PIN 1 INDEX
2.0
A
1.0
X
1.0
0.5 ± 0.1
1 2 3 4 5 6 7 8 9 10 11
209 - φ 0.6 ± 0.1
0.10 M
S
AB
S
DETAIL X
PACKAGE STRUCTURE
PRELIMINARY
SONY CODE
BGA-209P-01
JEITA CODE
P-BGA209-14X22-1.0
JEDEC CODE
18Mb 1x1Dp, LVCMOS, rev 1.0
PACKAGE MATERIAL
EPOXY RESIN
TERMINAL TREATMENT
COPPER-CLAD LAMINATE
TERMINAL MATERIAL
SOLDER
PACKAGE MASS
1.1g
28 / 30
July 19, 2002
SONY® ΣRAM
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Preliminary
•Revision History
Rev. #
Rev. Date
Description of Modifications
rev 0.0
06/23/00
Initial Version.
rev 0.1
02/23/01
1. Added Sony Part Numbers for each device.
2. Removed Asynchronous Output Enable (G) support. Pin 6D now defined as “MCL”.
3. Modified DC Recommended Operating Conditions section (p. 10).
VMIH-1.8 (min)
1.2V to 1.3V
VMIH-1.5 (min)
1.2V to 1.1V
VMIL-1.8 (max)
0.3V to 0.5V
VMIL-1.5 (max)
0.3V to 0.4V
3. Modified DC Electrical Characteristics section (p. 11).
Added IDD-4 Average Power Supply Operating Current specifications.
Added IDD2 Power Supply Deselect Operating Current specification.
4. Modified AC Electrical Characteristics section (p. 12).
Removed “-5” bin. Added “-44” bin.
All Bins Removed tKLCL specifications
-33
tAVKH, tBVKH, tDVKH
0.4ns to 0.7ns
tKHQV, tKHQZ
1.85ns to 1.8ns
tKHCH, tKHCZ
1.65ns to 1.7ns
tCHQV
0.2ns to 0.4ns
tCHQX
-0.2ns to -0.4ns
tCHCL
tKHKL ± 0.1 to tKHKL ± 0.2
tCLCH
tKLKH ± 0.1 to tKLKH ± 0.2
-4
tAVKH, tBVKH, tDVKH
0.5ns to 0.8ns
tKHQV, tKHQZ
2.25ns to 2.1ns
tCHQV
0.2ns to 0.5ns
tCHQX
-0.2ns to -0.5ns
tCHCL
tKHKL ± 0.1 to tKHKL ± 0.25
tCLCH
tKLKH ± 0.1 to tKLKH ± 0.25
5. Updated the size and content of the Boundary Scan Registers (p. 21).
rev 0.2
07/06/01
1. Modified DC Electrical Characteristics section (p. 11).
Added IDD-33 and IDD-44 Average Power Supply Operating Current specifications.
2. Added Slow Down pin (SD) and associated AC Electrical Characteristics section (p. 12).
3. Added 209 Pin BGA Package Dimensions (p. 26).
rev 0.3
02/22/02
1. Added BGA Package Thermal Characteristics (p. 10).
2. Removed Slow Down pin (SD) and associated AC Electrical Characteristics section (p. 13).
3. Modified AC Electrical Characteristics section (p. 13).
Removed “-44” bin. Added “-5” bin.
-4
tCHCL
tKHKL ± 0.25 to tKHKL ± 0.2
tCLCH
tKLKH ± 0.25 to tKLKH ± 0.2
4. Added JTAG ID Codes (p. 23).
5. Added JTAG Boundary Scan Register Bit Order Assignments (pp. 24-26).
rev 1.0
07/19/02
1. Modified Pin Assignment section (p. 2-4).
Byte Write Enable Control Inputs
Pin 1K
Pin 2K
Pin 10K
Pin 11K
Pin 6J
Pin 6L
Pin 6M
18Mb 1x1Dp, LVCMOS, rev 1.0
29 / 30
BWx to Bx
CQ to CQ2
CQ to CQ2
CQ to CQ1
CQ to CQ1
M4 to MCH
M2 to MCH
M3 to MCL
July 19, 2002
SONY® ΣRAM
Rev. #
CXK79M72C165GB / CXK79M36C165GB / CXK79M18C165GB
Rev. Date
Preliminary
Description of Modifications
2. Modified I/O Capacitance section (p. 10).
CKIN
3.5pF to 4.0pF
3. Modified DC Recommended Operating Conditions section (p. 11).
Combined -1.8 and -1.5 line items into one for VDDQ, VIH, VIL, VMIH, and VMIL.
VIH (min)
1.0V to VDDQ/2 + 0.3V
VIL (max)
0.6V to VDDQ/2 - 0.3V
VMIH (min)
1.1V to VDDQ/2 + 0.4V
VMIL (max)
0.5V to VDDQ/2 - 0.4V
Removed notes 1 and 2.
4. Modified DC Electrical Characteristics section (p. 12).
Added MCH and MCL Input Leakage Current specifications.
Reduced x72 Average Power Supply Operating Currents by 100mA.
Reduced x36 Average Power Supply Operating Currents by 50mA.
Reduced x18 Average Power Supply Operating Currents by 20mA.
5. Modified AC Electrical Characteristics section (p. 13).
-33
tKHCH (max), tKHCZ
1.7ns to 1.8ns
-4
tKHCH (max), tKHCZ
2.0ns to 2.1ns
-5
tKHCH (max), tKHCZ
2.2ns to 2.3ns
6. Modified JTAG DC Recommended Operating Conditions section (p. 19).
VTIH (min)
1.2V to VDD/2 + 0.3V
VTIL (max)
0.6V to VDD/2 - 0.3V
ITLI (min)
-10uA to -20uA
7. Modified JTAG AC Electrical Characteristics section (p. 20).
tTHTH
20ns to 50ns
tTHTL, tTLTH
8ns to 20ns
Added tCS Capture Setup and tCH Capture Hold specifications.
8. Modified TAP Registers section (p. 22).
Instruction Register Codes 011, 110
Bypass to Private
9. Modified Boundary Scan Register Bit Order Assignments section (p. 24-25).
x72
Bit 47
10A to 11A
x72
Bit 48
11A to 10A
x36
Bit 29
10A to 11A
x36
Bit 30
11A to 10A
18Mb 1x1Dp, LVCMOS, rev 1.0
30 / 30
July 19, 2002