CY29658 2.5V or 3.3V 200-MHz 10-Output Zero Delay Buffer Features • • • • • • • • • • • • • Description Output frequency range: 50 MHz to 200 MHz Input frequency range: 50 MHz to 200 MHz 2.5V or 3.3V operation Ten clock outputs: drive up to 20 clock lines One Feedback output LVPECL reference clock input 150-ps max output-output skew Phase-locked loop (PLL) bypass mode Spread Aware™ Output enable/disable Pin-compatible with MPC9658 and MPC958 Industrial temperature range: –40°C to +85°C 32-Pin 1.0mm TQFP package The CY29658 is a low-voltage high-performance 200-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. The CY29658 features an LVPECL reference clock input and provides ten outputs plus one feedback output. VCO output divides by two or four per VCO_SEL setting (see Function Table). Each LVCMOS-compatible output can drive 50Ω series- or parallel-terminated transmission lines. For series-terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:20. The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 50 MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider (see Frequency Table). When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. When BYPASS# is set LOW, PLL and output dividers are bypassed resulting in a 1:11 LVPECL to LVCMOS high performance fanout buffer. For normal PLL operation, both PLL_EN and BYPASS# are set HIGH. VCO_SEL VDDQ FB_OUT VSS Q0 VDD Q1 VSS 30 29 28 27 26 25 12 13 14 15 16 VSS Q7 VDDQ Q6 MR/OE# Q8 LPF VCO_SEL BYPASS# C Y 29658 11 Q9 VCO 200-480M 24 23 22 21 20 19 18 17 VDDQ /2 1 2 3 4 5 6 7 8 9 AVDD F B _IN BYPASS# P LL_E N M R /O E# P E C L_C LK P E C L_C LK # A V SS Q(0:8) 10 FB_IN /2 Phase Detector Q9 PECL_CLK# VSS PECL_CLK 31 FB_OUT 32 Pin Configuration Block Diagram Q2 VDDQ Q3 VSS Q4 VDDQ Q5 VSS PLL_EN Cypress Semiconductor Corporation Document #: 38-07478 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised May 14, 2003 CY29658 Pin Description[1] Pin Name I/O Type Description 6 PECL_CLK I, PU LVPECL LVPECL reference clock input. 7 PECL_CLK# I, PU LVPECL LVPECL reference clock input. Pull-up to VDD/2. 10, 12, 14, Q(9:0) 16, 18, 20, 22, 24, 26, 28 O LVCMOS Clock output. 30 FB_OUT O LVCMOS Feedback clock output. Connect to FB_IN for normal operation. 2 FB_IN I, PU LVCMOS Feedback clock input. Connect to FB_OUT for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. 5 MR/OE# I, PD LVCMOS Output enable/disable input. See Table 2. 4 PLL_EN I, PU LVCMOS PLL enable/disable input. See Table 2. 3 BYPASS# I, PU LVCMOS PLL and output divider bypass select input. See Table 2. 32 VCO_SEL I, PU LVCMOS VCO divider select input. See Table 2. 11, 15, 19, 23, 31 VDDQ Supply VDD 2.5V or 3.3V power supply for output clocks.[2,3] 1 AVDD Supply VDD 2.5V or 3.3V power supply for PLL.[2,3] 27 VDD Supply VDD 2.5V or 3.3V power supply for core and inputs.[2,3] 8 AVSS Supply Ground Analog ground. Supply Ground Common ground. 9, 13, 17, 21, VSS 25, 29 Table 1. Frequency Table Feedback Output Divider Input Frequency Range (AVDD = 3.3V) VCO Input Frequency Range (AVDD = 2.5V) ÷2 Input Clock * 2 100 MHz to 200 MHz 100 MHz to 200 MHz ÷4 Input Clock * 4 50 MHz to 125 MHz 50 MHz to 100 MHz Table 2. Function Table Control Default 0 1 VCO_SEL 1 PLL_EN 1 Bypass mode, PLL disabled. The input PLL enabled. The VCO output connects to the clock connects to the output dividers output dividers VCO ÷ 1 VCO ÷ 2 BYPASS# 1 Bypass mode with PLL and output dividers bypassed. The input clock connects to the outputs. Selects the output dividers MR/OE# 0 Outputs enabled Outputs disabled (three-state), VCO running at its minimum frequency Notes: 1. PU = Internal pull-up, PD = Internal pull-down. 2. A 0.1-µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their high-frequency filtering characteristics will be cancelled by the lead inductance of the traces. 3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQ power supply pin. Document #: 38-07478 Rev. ** Page 2 of 7 CY29658 Absolute Maximum Conditions Parameter Description Condition VDD DC Supply Voltage VDD DC Operating Voltage Functional VIN DC Input Voltage VOUT DC Output Voltage VTT Output termination Voltage LU Latch Up Immunity Min. Max. Unit –0.3 5.5 V 2.375 3.465 V Relative to VSS -0.3 VDD + 0.3 V Relative to VSS –0.3 VDD + 0.3 V Functional 200 VDD ÷ 2 V mA RPS Power Supply Ripple Ripple frequency < 100 kHz 150 mVp-p TS Temperature, Storage Non-functional –65 +150 °C TA Temperature, Operating Ambient Functional –40 +85 °C TJ Temperature, Junction Functional 150 °C ØJC Dissipation, Junction to Case Functional 42 °C/W ØJA Dissipation, Junction to Ambient Functional 105 °C/W ESDH ESD Protection (Human Body Model) FIT Failure in Time 2000 V Manufacturing test 10 ppm DC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C) Min. Typ. Max. Unit VIL Parameter Input Voltage, Low Description LVCMOS Condition – – 0.7 V VIH Input Voltage, High LVCMOS 1.7 – VDD + 0.3 V VPP Peak-Peak Input Voltage LVPECL 250 – 1000 mV Range[4] LVPECL 1.0 – VDD – 0.6 V – – 0.6 V 1.8 – – V µA VCMR Common Mode VOL Output Voltage, Low[5] IOL = 15 mA VOH Output Voltage, High[5] IOH = –15 mA Input Current, Low[6] VIL = VSS – – –100 IIH Input Current, High[6] VIL = VDD – – 100 µA IDDA PLL Supply Current AVDD only – – 7 mA IDDQ Quiescent Supply Current All VDD pins except AVDD – – 4 mA IDD Dynamic Supply Current Outputs loaded @ 100 MHz – 245 – mA CIN Input Pin Capacitance – 4 – pF ZOUT Output Impedance 14 18 22 Ω Min. Typ. Max. Unit IIL DC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C) Parameter Description Condition VIL Input Voltage, Low LVCMOS – – 0.8 V VIH Input Voltage, High LVCMOS 2.0 – VDD + 0.3 V VPP Peak-Peak Input Voltage LVPECL 250 – 1000 mV Common Mode Range[4] LVPECL 1.0 – VDD – 0.6 V Output Voltage, Low[5] IOL = 24 mA – – 0.55 V IOL = 12 mA – – 0.30 2.4 – – VCMR VOL VOH Output Voltage, High[5] IOH = –24 mA V Notes: 4. VCMR (DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the VCMR range and the input swing is within the VPP (DC) specification. 5. Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 Ω series terminated transmission lines. 6. Inputs have pull-up or pull-down resistors that affect the input current. Document #: 38-07478 Rev. ** Page 3 of 7 CY29658 DC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C) (continued) Parameter Description Min. Typ. Max. Unit VIL = VSS – – –100 µA VIL = VDD – – 100 µA PLL Supply Current AVDD only – – 7 mA Quiescent Supply Current All VDD pins except AVDD – – 4 mA IDD Dynamic Supply Current Outputs loaded @ 100 MHz CIN Input Pin Capacitance IIL [6] Input Current, Low IIH Input Current, High[6] IDDA IDDQ ZOUT Condition Output Impedance AC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C) Parameter Description fVCO VCO Frequency fin Input Frequency – 330 – mA – 4 – pF 12 15 18 Ω Min. Typ. Max. Unit 200 – 400 MHz MHz [7] Condition ÷2 Feedback 100 – 200 ÷4 Feedback 50 – 100 Bypass mode (BYPASS# = 0) 0 – 200 40 – 60 % frefDC Input Duty Cycle VPP Peak-Peak Input Voltage LVPECL 500 – 1000 mV VCMR Common Mode Range[8] LVPECL 1.2 – VDD – 0.6 V fMAX Maximum Output Frequency ÷2 Output 100 – 200 MHz ÷4 Output 50 – 100 45 – 55 % 0.1 – 1.0 ns –200 – 225 ps 4.1 5.5 6.9 ns DC Output Duty Cycle tr, tf Output Rise/Fall times 0.6V to 1.8V t(φ) Propagation Delay (static phase offset) PCLK to FB_IN, same VDD tPD Propagation Delay (PLL and divider bypass) PCLK to Q0 – Q9 BYPASS# = 0 tsk(O) Output-to-Output Skew – – 150 ps tPLZ, HZ Output Disable Time – – 6 ns tPZL, ZH Output Enable Time – – 6 ns BW PLL Closed Loop Bandwidth (–3dB) ÷2 Feedback – 1.9 – 2.2 – MHz ÷4 Feedback – 1.8 – 2.1 – tJIT(CC) Cycle-to-Cycle Jitter – – 100 ps tJIT(PER) Period Jitter – – 75 ps tJIT(φ) I/O Phase Jitter – – 150 ps tLOCK Maximum PLL Lock Time – – 1 ms Min. Typ. Max. Unit 200 – 500 MHz ÷2 Feedback 100 – 200 MHz ÷4 Feedback 50 – 125 Bypass mode (BYPASS# = 0) 0 – 200 I/O same VDD AC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C) Parameter Description fVCO VCO Frequency fin Input Frequency [7] Condition Notes: 7. AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested. 8. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(φ). Document #: 38-07478 Rev. ** Page 4 of 7 CY29658 AC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C) (continued)[7] Parameter Description Condition Min. Typ. Max. Unit frefDC Input Duty Cycle 40 – 60 % VPP Peak-Peak Input Voltage LVPECL 500 – 1000 mV VCMR Common Mode Range[8] LVPECL 1.2 – VDD - 0.9 V fMAX Maximum Output Frequency ÷2 Output 100 – 200 MHz DC Output Duty Cycle tr , tf Output Rise/Fall times 0.55V to 2.4V t(φ) Propagation Delay (static phase offset) PCLK to FB_IN, same VDD tPD Propagation Delay (PLL and divider bypass) PCLK to Q0 – Q9 BYPASS# = 0 tsk(O) ÷4 Output 50 – 125 45 – 55 % 0.1 – 1.0 ns –200 – 225 ps 3.6 4.8 6.0 ns Output-to-Output Skew – – 150 ps tPLZ, HZ Output Disable Time – – 6 ns tPZL, ZH Output Enable Time – – 6 ns BW PLL Closed Loop Bandwidth (–3dB) ÷2 Feedback – 1.9 – 2.2 – MHz ÷4 Feedback – 1.8 – 2.1 – tJIT(CC) Cycle-to-Cycle Jitter – – 100 ps tJIT(PER) Period Jitter – – 75 ps tJIT(φ) I/O Phase Jitter – – 150 ps tLOCK Maximum PLL Lock Time – – 1 ms I/O same VDD Zo = 50 ohm Differential Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm R T = 50 ohm VTT R T = 50 ohm VTT Figure 1. AC Test Reference for VDD = 3.3V / 2.5V PECL_CLK PECL_CLK PECL_CLK V PP VCMR PECL_CLK V PP VDD VDD Qn FB_IN t (φ) Figure 2. Propagation Delay t(φ), Static Phase Offset Document #: 38-07478 Rev. ** VDD/2 VDD/2 GND VCMR tPD GND Figure 3. Propagation Delay tPD, PLL Bypass Page 5 of 7 CY29658 tP VDD VDD VDD/2 VDD/2 GND GND VDD T0 VDD/2 DC = tP / T0 x 100% GND tSK(O) Figure 4. Output Duty Cycle (DC) Figure 5. Output-to-Output Skew tsk(O) Ordering Information Part Number Package Type Product Flow CY29658AI 32-pin TQFP Industrial, –40°C to +85°C CY29658AIT 32-pin TQFP – Tape and Reel Industrial, –40°C to 85°C Package Drawing and Dimension 32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.0mm A32 51-85063-*B Spread Aware is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07478 Rev. ** Page 6 of 7 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY29658 Document History Page Document Title:CY29658 2.5V or 3.3V 200-MHz 10-Output Zero Delay Buffer Document Number: 38-07478 Rev. ECN No. Issue Date Orig. of Change ** 126716 05/19/03 RGL Document #: 38-07478 Rev. ** Description of Change New Data Sheet Page 7 of 7