TI DRV8824

DRV8824
SLVSA06E – OCTOBER 2009 – REVISED AUGUST 2011
www.ti.com
STEPPER MOTOR CONTROLLER IC
Check for Samples: DRV8824
FEATURES
APPLICATIONS
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PWM Microstepping Motor Driver
– Built-In Microstepping Indexer
– Five-Bit Winding Current Control Allows Up
to 32 Current Levels
– Low MOSFET On-Resistance
1.6-A Maximum Drive Current at 24 V, 25°C
Built-In 3.3-V Reference Output
8-V to 45-V Operating Supply Voltage Range
Thermally Enhanced Surface Mount Package
Automatic Teller Machines
Money Handling Machines
Video Security Cameras
Printers
Scanners
Office Automation Machines
Gaming Machines
Factory Automation
Robotics
DESCRIPTION
The DRV8824 provides an integrated motor driver solution for printers, scanners, and other automated
equipment applications. The device has two H-bridge drivers and a microstepping indexer, and is intended to
drive a bipolar stepper motor. The output driver block for each consists of N-channel power MOSFET’s
configured as full H-bridges to drive the motor windings. The DRV8824 is capable of driving up to 1.6-A of output
current (with proper heatsinking, at 24 V and 25°C).
A simple step/direction interface allows easy interfacing to controller circuits. Pins allow configuration of the
motor in full-step up to 1/32-step modes. Decay mode is programmable.
Internal shutdown functions are provided for overcurrent protection, short circuit protection, undervoltage lockout
and overtemperature.
The DRV8824 is available in a 28-pin HTSSOP package with PowerPAD™ (Eco-friendly: RoHS & no Sb/Br).
ORDERING INFORMATION (1)
PACKAGE (2)
PowerPAD™ (HTSSOP) - PWP
(1)
(2)
Reel of 2000
ORDERABLE PART
NUMBER
TOP-SIDE
MARKING
DRV8824PWPR
8824
For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2011, Texas Instruments Incorporated
DRV8824
SLVSA06E – OCTOBER 2009 – REVISED AUGUST 2011
www.ti.com
DEVICE INFORMATION
Functional Block Diagram
VM
VM
Int. VCC
Internal
CP1
Reference &
LS Gate
Regs
Drive
0.01uF
Charge
V3P3OUT
CP2
VM
Pump
3.3V
3.3V
VCP
Thermal
0.1uF
Shut down
HS Gate
Drive
AVREF
VM
VMA
BVREF
AOUT1
+
nENBL
Motor
Step
Driver A
Motor
AOUT2
STEP
-
DIR
+
ISENA
-
DECAY
MODE0
MODE1
MODE2
Indexer /
VM
Control
VMB
Logic
nRESET
BOUT1
nSLEEP
Motor
Driver B
nHOME
BOUT2
nFAULT
ISENB
GND
2
GND
Copyright © 2009–2011, Texas Instruments Incorporated
DRV8824
SLVSA06E – OCTOBER 2009 – REVISED AUGUST 2011
www.ti.com
Table 1. TERMINAL FUNCTIONS
NAME
PIN
I/O (1)
EXTERNAL COMPONENTS
OR CONNECTIONS
DESCRIPTION
POWER AND GROUND
GND
14, 28
-
Device ground
VMA
4
-
Bridge A power supply
VMB
11
-
Bridge B power supply
V3P3OUT
15
O
3.3-V regulator output
CP1
1
IO
Charge pump flying capacitor
CP2
2
IO
Charge pump flying capacitor
VCP
3
IO
High-side gate drive voltage
Connect a 0.1-μF 16-V ceramic capacitor to
VM.
nENBL
21
I
Enable input
Logic high to disable device outputs and
indexer operation, logic low to enable. Internal
pulldown.
nSLEEP
17
I
Sleep mode input
Logic high to enable device, logic low to enter
low-power sleep mode. Internal pulldown.
STEP
22
I
Step input
Rising edge causes the indexer to move one
step. Internal pulldown.
DIR
20
I
Direction input
Level sets the direction of stepping. Internal
pulldown.
MODE0
24
I
Microstep mode 0
MODE1
25
I
Microstep mode 1
MODE2
26
I
Microstep mode 2
DECAY
19
I
Decay mode
Low = slow decay, open = mixed decay,
high = fast decay. Internal pulldown and
pullup.
nRESET
16
I
Reset input
Active-low reset input initializes the indexer
logic and disables the H-bridge outputs.
Internal pulldown.
AVREF
12
I
Bridge A current set reference input
BVREF
13
I
Bridge B current set reference input
NC
23
Connect to motor supply (8 - 45 V). Both pins
must be connected to same supply.
Bypass to GND with a 0.47-μF 6.3-V ceramic
capacitor. Can be used to supply VREF.
Connect a 0.01-μF 50-V capacitor between
CP1 and CP2.
CONTROL
MODE0 - MODE2 set the step mode - full,
1/2, 1/4, 1/8/ 1/16, or 1/32 step. Internal
pulldown.
Reference voltage for winding current set.
Normally AVREF and BVREF are connected
to the same voltage. Can be connected to
V3P3OUT. A 0.01-µF bypass capacitor to
GND is recommended.
No connect
Leave this pin unconnected.
STATUS
nHOME
27
OD
Home position
Logic low when at home state of step table
nFAULT
18
OD
Fault
Logic low when in fault condition (overtemp,
overcurrent)
ISENA
6
IO
Bridge A ground / Isense
Connect to current sense resistor for bridge A.
ISENB
9
IO
Bridge B ground / Isense
Connect to current sense resistor for bridge B.
AOUT1
5
O
Bridge A output 1
AOUT2
7
O
Bridge A output 2
Connect to bipolar stepper motor winding A.
Positive current is AOUT1 → AOUT2
BOUT1
10
O
Bridge B output 1
BOUT2
8
O
Bridge B output 2
OUTPUT
(1)
Connect to bipolar stepper motor winding B.
Positive current is BOUT1 → BOUT2
Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output
Copyright © 2009–2011, Texas Instruments Incorporated
3
DRV8824
SLVSA06E – OCTOBER 2009 – REVISED AUGUST 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VMx
VREF
(1) (2)
VALUE
UNIT
Power supply voltage range
–0.3 to 47
V
Digital pin voltage range
–0.5 to 7
V
Input voltage
–0.3 to 4
V
–0.3 to 0.8
V
Peak motor drive output current, t < 1 μS
Internally limited
A
Continuous motor drive output current (3)
1.6
A
ISENSEx pin voltage
ESD rating
Continuous total power dissipation
HBD (human body model)
2000
CDM (charged device model)
500
V
See Thermal Information table
TJ
Operating virtual junction temperature range
–40 to 150
°C
Tstg
Storage temperature range
–60 to 150
°C
(1)
(2)
(3)
4
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
Power dissipation and thermal limits must be observed.
Copyright © 2009–2011, Texas Instruments Incorporated
DRV8824
SLVSA06E – OCTOBER 2009 – REVISED AUGUST 2011
www.ti.com
THERMAL INFORMATION
DRV8824
THERMAL METRIC
PWP
UNITS
28 PINS
Junction-to-ambient thermal resistance (1)
θJA
38.9
(2)
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (3)
21.2
ψJT
Junction-to-top characterization parameter (4)
0.8
ψJB
Junction-to-board characterization parameter (5)
20.9
θJCbot
Junction-to-case (bottom) thermal resistance (6)
2.6
(1)
(2)
(3)
(4)
(5)
(6)
23.3
°C/W
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
MIN
Motor power supply voltage range (1)
VM
(2)
VREF
VREF input voltage
IV3P3
V3P3OUT load current
(1)
(2)
NOM
MAX
8.2
45
1
3.5
UNIT
V
V
1
mA
All VM pins must be connected to the same supply voltage.
Operational at VREF between 0 V and 1 V, but accuracy is degraded.
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range of -40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES
IVM
VM operating supply current
VM = 24 V, fPWM < 50 kHz
5
8
mA
IVMQ
VM sleep mode supply current
VM = 24 V
10
20
μA
VUVLO
VM undervoltage lockout voltage
VM rising
7.8
8.2
V
V3P3OUT REGULATOR
V3P3
V3P3OUT voltage
IOUT = 0 to 1 mA, VM = 24 V, TJ = 25°C
3.18
3.30
3.42
IOUT = 0 to 1 mA
3.10
3.30
3.50
V
LOGIC-LEVEL INPUTS
VIL
Input low voltage
VIH
Input high voltage
VHYS
Input hysteresis
IIL
Input low current
VIN = 0
IIH
Input high current
VIN = 3.3 V
RPD
Internal pulldown resistance
0.6
2
0.7
V
5.25
V
0.45
nENBL, nRESET, DIR, STEP, MODEx
nSLEEP
–20
V
20
100
μA
μA
100
kΩ
1
MΩ
nHOME, nFAULT OUTPUTS (OPEN-DRAIN OUTPUTS)
VOL
Output low voltage
IO = 5 mA
IOH
Output high leakage current
VO = 3.3 V
0.5
V
1
μA
DECAY INPUT
Copyright © 2009–2011, Texas Instruments Incorporated
5
DRV8824
SLVSA06E – OCTOBER 2009 – REVISED AUGUST 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range of -40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIL
Input low threshold voltage
For slow decay mode
VIH
Input high threshold voltage
For fast decay mode
IIN
Input current
RPU
Internal pullup resistance
RPD
Internal pulldown resistance
MIN
TYP
MAX
UNIT
0.8
V
±40
µA
2
V
130
kΩ
80
kΩ
H-BRIDGE FETS
RDS(ON)
HS FET on resistance
RDS(ON)
LS FET on resistance
IOFF
Off-state leakage current
VM = 24 V, I O = 1 A, TJ = 25°C
0.63
VM = 24 V, IO = 1 A, TJ = 85°C
0.76
VM = 24 V, IO = 1 A, TJ = 25°C
0.65
VM = 24 V, IO = 1 A, TJ = 85°C
0.78
–20
0.90
0.90
20
Ω
Ω
μA
MOTOR DRIVER
fPWM
Internal PWM frequency
tBLANK
Current sense blanking time
50
kHz
tR
Rise time
VM = 24 V
100
360
ns
tF
Fall time
VM = 24 V
80
250
ns
tDEAD
Dead time
μs
3.75
400
ns
PROTECTION CIRCUITS
IOCP
Overcurrent protection trip level
tTSD
Thermal shutdown temperature
1.8
Die temperature
150
5
A
160
180
°C
3
μA
660
685
mV
CURRENT CONTROL
–3
IREF
xVREF input current
xVREF = 3.3 V
VTRIP
xISENSE trip voltage
xVREF = 3.3 V, 100% current setting
635
xVREF = 3.3 V , 5% current setting
–25
25
xVREF = 3.3 V , 10% - 34% current
setting
–15
15
xVREF = 3.3 V, 38% - 67% current
setting
–10
10
xVREF = 3.3 V, 71% - 100% current
setting
–5
5
ΔITRIP
AISENSE
6
Current trip accuracy
(relative to programmed value)
Current sense amplifier gain
Reference only
5
%
V/V
Copyright © 2009–2011, Texas Instruments Incorporated
DRV8824
SLVSA06E – OCTOBER 2009 – REVISED AUGUST 2011
www.ti.com
TIMING REQUIREMENTS
MIN
MAX
UNIT
250
kHz
1
fSTEP
Step frequency
2
tWH(STEP)
Pulse duration, STEP high
1.9
μs
3
tWL(STEP)
Pulse duration, STEP low
1.9
μs
4
tSU(STEP)
Setup time, command to STEP rising
200
ns
5
tH(STEP)
Hold time, command to STEP rising
200
ns
6
tENBL
Enable time, nENBL active to STEP
200
ns
7
tWAKE
Wakeup time, nSLEEP inactive to STEP
1
ms
Figure 1. Timing Diagram
Copyright © 2009–2011, Texas Instruments Incorporated
7
DRV8824
SLVSA06E – OCTOBER 2009 – REVISED AUGUST 2011
www.ti.com
FUNCTIONAL DESCRIPTION
PWM Motor Drivers
The DRV8824 contains two H-bridge motor drivers with current-control PWM circuitry. A block diagram of the
motor control circuitry is shown in Figure 2.
Figure 2. Motor Control Circuitry
Note that there are multiple VM motor power supply pins. All VM pins must be connected together to the motor
supply voltage.
8
Copyright © 2009–2011, Texas Instruments Incorporated
DRV8824
SLVSA06E – OCTOBER 2009 – REVISED AUGUST 2011
www.ti.com
Current Regulation
The current through the motor windings is regulated by a fixed-frequency PWM current regulation, or current
chopping. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage
and inductance of the winding. Once the current hits the current chopping threshold, the bridge disables the
current until the beginning of the next PWM cycle.
In stepping motors, current regulation is used to vary the current in the two windings in a semi-sinusoidal fashion
to provide smooth motion.
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor
connected to the xISEN pins, multiplied by a factor of 5, with a reference voltage. The reference voltage is input
from the xVREF pins.
The full-scale (100%) chopping current is calculated in Equation 1.
VREFX
ICHOP = 5¾
· RISENSE
(1)
Example:
If a 0.5-Ω sense resistor is used and the VREFx pin is 3.3 V, the full-scale (100%) chopping current will be
3.3 V / (5 x 0.5 Ω) = 1.32 A.
The reference voltage is scaled by an internal DAC that allows fractional stepping of a bipolar stepper motor, as
described in the microstepping indexer section below.
Decay Mode
During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM
current chopping threshold is reached. This is shown in Figure 3 as case 1. The current flow direction shown
indicates positive current flow.
Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or
slow decay.
In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to
allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is
disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 3 as case 2.
In slow decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is
shown in Figure 3 as case 3.
Figure 3. Decay Mode
Copyright © 2009–2011, Texas Instruments Incorporated
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DRV8824
SLVSA06E – OCTOBER 2009 – REVISED AUGUST 2011
www.ti.com
The DRV8824 supports fast decay, slow decay and a mixed decay mode. Slow, fast, or mixed decay mode is
selected by the state of the DECAY pin - logic low selects slow decay, open selects mixed decay operation, and
logic high sets fast decay mode. The DECAY pin has both an internal pullup resistor of approximately 130 kΩ
and an internal pulldown resistor of approximately 80 kΩ. This sets the mixed decay mode if the pin is left open
or undriven.
Mixed decay mode begins as fast decay, but at a fixed period of time (75% of the PWM cycle) switches to slow
decay mode for the remainder of the fixed PWM period. This occurs only if the current through the winding is
decreasing (per the indexer step table); if the current is increasing, then slow decay is used.
Blanking Time
After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a fixed period of time
before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. Note that the blanking time also
sets the minimum on time of the PWM.
Microstepping Indexer
Built-in indexer logic in the DRV8824 allows a number of different stepping configurations. The MODE0 - MODE2
pins are used to configure the stepping format as shown in Table 2.
Table 2. Stepping Format
MODE2
MODE1
MODE0
0
0
0
Full step (2-phase excitation) with 71% current
STEP MODE
0
0
1
1/2 step (1-2 phase excitation)
0
1
0
1/4 step (W1-2 phase excitation)
0
1
1
8 microsteps / step
1
0
0
16 microsteps / step
1
0
1
32 microsteps / step
1
1
0
32 microsteps / step
1
1
1
32 microsteps / step
Table 3 shows the relative current and step directions for different settings of MODEx. At each rising edge of the
STEP input, the indexer travels to the next state in the table. The direction is shown with the DIR pin high; if the
DIR pin is low the sequence is reversed. Positive current is defined as xOUT1 = positive with respect to xOUT2.
Note that if the step mode is changed while stepping, the indexer will advance to the next valid state for the new
MODEx setting at the rising edge of STEP.
The home state is 45°. This state is entered at power-up or application of nRESET. This is shown in Table 3 by
the shaded cells. The logic inputs DIR, STEP, nRESET and MODEx have an internal pulldown resistors of
100 kΩ
Table 3. Relative Current and Step Directions
1/32 STEP 1/16 STEP
1
1
1/8 STEP
1/4 STEP
1/2 STEP
1
1
1
2
3
2
4
5
3
2
6
7
4
8
9
10
10
5
3
2
FULL
STEP
70%
WINDING
CURRENT
A
WINDING
CURRENT
B
ELECTRICAL
ANGLE
100%
0%
0
100%
5%
3
100%
10%
6
99%
15%
8
98%
20%
11
97%
24%
14
96%
29%
17
94%
34%
20
92%
38%
23
90%
43%
25
Copyright © 2009–2011, Texas Instruments Incorporated
DRV8824
SLVSA06E – OCTOBER 2009 – REVISED AUGUST 2011
www.ti.com
Table 3. Relative Current and Step Directions (continued)
1/32 STEP 1/16 STEP
11
1/8 STEP
1/4 STEP
1/2 STEP
FULL
STEP
70%
6
12
13
7
4
14
15
8
16
17
9
5
3
2
1
18
19
10
20
21
11
6
22
23
12
24
25
13
7
4
26
27
14
28
29
15
8
30
31
16
32
33
17
9
5
3
34
35
18
36
37
19
10
38
39
20
40
41
21
11
6
42
43
22
44
45
23
12
46
47
24
48
49
25
13
7
50
51
26
52
53
27
14
54
55
28
56
Copyright © 2009–2011, Texas Instruments Incorporated
4
2
WINDING
CURRENT
A
WINDING
CURRENT
B
ELECTRICAL
ANGLE
88%
47%
28
86%
51%
31
83%
56%
34
80%
60%
37
77%
63%
39
74%
67%
42
71%
71%
45
67%
74%
48
63%
77%
51
60%
80%
53
56%
83%
56
51%
86%
59
47%
88%
62
43%
90%
65
38%
92%
68
34%
94%
70
29%
96%
73
24%
97%
76
20%
98%
79
15%
99%
82
10%
100%
84
5%
100%
87
0%
100%
90
–5%
100%
93
–10%
100%
96
–15%
99%
98
–20%
98%
101
–24%
97%
104
–29%
96%
107
–34%
94%
110
–38%
92%
113
–43%
90%
115
–47%
88%
118
–51%
86%
121
–56%
83%
124
–60%
80%
127
–63%
77%
129
–67%
74%
132
–71%
71%
135
–74%
67%
138
–77%
63%
141
–80%
60%
143
–83%
56%
146
–86%
51%
149
–88%
47%
152
–90%
43%
155
11
DRV8824
SLVSA06E – OCTOBER 2009 – REVISED AUGUST 2011
www.ti.com
Table 3. Relative Current and Step Directions (continued)
1/32 STEP 1/16 STEP
57
29
1/8 STEP
1/4 STEP
15
8
1/2 STEP
FULL
STEP
70%
58
59
30
60
61
31
16
62
63
32
64
65
33
17
9
5
66
67
34
68
69
35
18
70
71
36
72
73
37
19
10
74
75
38
76
77
39
20
78
79
40
80
81
41
21
11
6
82
83
42
84
85
43
22
86
87
44
88
89
45
23
12
90
91
46
92
93
47
24
94
95
48
96
97
49
25
98
99
50
100
101
102
12
51
26
13
7
3
WINDING
CURRENT
A
WINDING
CURRENT
B
ELECTRICAL
ANGLE
–92%
38%
158
–94%
34%
160
–96%
29%
163
–97%
24%
166
–98%
20%
169
–99%
15%
172
–100%
10%
174
–100%
5%
177
–100%
0%
180
–100%
–5%
183
–100%
–10%
186
–99%
–15%
188
–98%
–20%
191
–97%
–24%
194
–96%
–29%
197
–94%
–34%
200
–92%
–38%
203
–90%
–43%
205
–88%
–47%
208
–86%
–51%
211
–83%
–56%
214
–80%
–60%
217
–77%
–63%
219
–74%
–67%
222
–71%
–71%
225
–67%
–74%
228
–63%
–77%
231
–60%
–80%
233
–56%
–83%
236
–51%
–86%
239
–47%
–88%
242
–43%
–90%
245
–38%
–92%
248
–34%
–94%
250
–29%
–96%
253
–24%
–97%
256
–20%
–98%
259
–15%
–99%
262
–10%
–100%
264
–5%
–100%
267
0%
–100%
270
5%
–100%
273
10%
–100%
276
15%
–99%
278
20%
–98%
281
24%
–97%
284
Copyright © 2009–2011, Texas Instruments Incorporated
DRV8824
SLVSA06E – OCTOBER 2009 – REVISED AUGUST 2011
www.ti.com
Table 3. Relative Current and Step Directions (continued)
1/32 STEP 1/16 STEP
103
1/8 STEP
1/4 STEP
1/2 STEP
FULL
STEP
70%
52
104
105
53
27
14
106
107
54
108
109
55
28
110
111
56
112
113
57
29
15
8
114
115
58
116
117
59
30
118
119
60
120
121
61
31
16
122
123
62
124
125
63
32
126
127
64
128
4
WINDING
CURRENT
A
WINDING
CURRENT
B
ELECTRICAL
ANGLE
29%
–96%
287
34%
–94%
290
38%
–92%
293
43%
–90%
295
47%
–88%
298
51%
–86%
301
56%
–83%
304
60%
–80%
307
63%
–77%
309
67%
–74%
312
71%
–71%
315
74%
–67%
318
77%
–63%
321
80%
–60%
323
83%
–56%
326
86%
–51%
329
88%
–47%
332
90%
–43%
335
92%
–38%
338
94%
–34%
340
96%
–29%
343
97%
–24%
346
98%
–20%
349
99%
–15%
352
100%
–10%
354
100%
–5%
357
nRESET, nENBLE and nSLEEP Operation
The nRESET pin, when driven active low, resets internal logic, and resets the step table to the home position. It
also disables the H-bridge drivers. The STEP input is ignored while nRESET is active.
The nENBL pin is used to control the output drivers and enable/disable operation of the indexer. When nENBL is
low, the output H-bridges are enabled, and rising edges on the STEP pin are recognized. When nENBL is high,
the H-bridges are disabled, the outputs are in a high-impedance state, and the STEP input is ignored.
Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the
gate drive charge pump is stopped, the V3P3OUT regulator is disabled, and all internal clocks are stopped. In
this state all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time
(approximately 1 ms) needs to pass before applying a STEP input, to allow the internal circuitry to stabilize.
The nRESET and nENABLE pins have internal pulldown resistors of 100 kΩ. The nSLEEP pin has an internal
pulldown resistor of 1 MΩ.
Protection Circuits
The DRV8824 is fully protected against undervoltage, overcurrent and overtemperature events.
Copyright © 2009–2011, Texas Instruments Incorporated
13
DRV8824
SLVSA06E – OCTOBER 2009 – REVISED AUGUST 2011
www.ti.com
Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled and the
nFAULT pin will be driven low. The device will remain disabled until either nRESET pin is applied, or VM is
removed and re-applied.
Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor
winding will all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense
circuitry used for PWM current control, and is independent of the ISENSE resistor value or VREF voltage.
Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be
driven low. Once the die temperature has fallen to a safe level operation will automatically resume.
Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the
device will be disabled and internal logic will be reset. Operation will resume when VM rises above the UVLO
threshold.
14
Copyright © 2009–2011, Texas Instruments Incorporated
DRV8824
SLVSA06E – OCTOBER 2009 – REVISED AUGUST 2011
www.ti.com
THERMAL INFORMATION
Thermal Protection
The DRV8824 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately
150°C, the device will be disabled until the temperature drops to a safe level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
Power Dissipation
Power dissipation in the DRV8824 is dominated by the power dissipated in the output FET resistance, or RDS(ON).
Average power dissipation when running a stepper motor can be roughly estimated by Equation 2.
PTOT = 4 · RDS(ON) · (IOUT(RMS))
2
(2)
where PTOT is the total power dissipation, RDS(ON) is the resistance of each FET, and IOUT(RMS) is the RMS output
current being applied to each winding. IOUT(RMS) is equal to the approximately 0.7x the full-scale output current
setting. The factor of 4 comes from the fact that there are two motor windings, and at any instant two FETs are
conducting winding current for each winding (one high-side and one low-side).
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must
be taken into consideration when sizing the heatsink.
Heatsinking
The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad
must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,
this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs
without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area
is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and
bottom layers.
For details about how to design the PCB, refer to TI application report SLMA002, " PowerPAD™ Thermally
Enhanced Package" and TI application brief SLMA004, " PowerPAD™ Made Easy", available at www.ti.com.
In general, the more copper area that can be provided, the more power can be dissipated. It can be seen that the
heatsink effectiveness increases rapidly to about 20 cm2, then levels off somewhat for larger areas.
Copyright © 2009–2011, Texas Instruments Incorporated
15
PACKAGE OPTION ADDENDUM
www.ti.com
12-Aug-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
DRV8824PWP
ACTIVE
HTSSOP
PWP
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
DRV8824PWPR
ACTIVE
HTSSOP
PWP
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(3)
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DRV8824PWPR
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
28
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.2
1.8
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV8824PWPR
HTSSOP
PWP
28
2000
367.0
367.0
38.0
Pack Materials-Page 2
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