HYM72V32M636(L)T6M Revision History 1st Originated 9/11/2001 32Mx64 bits PC133 SDRAM SO DIMM based on 16Mx16 SDRAM with LVTTL, 4 banks & 8K Refresh HYM72V32M636(L)T6M Series DESCRIPTION The Hynix HYM72V32M636T6M Series are 32Mx64bits Synchronous DRAM Modules. The modules are composed of eight 16Mx16bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 144pin glass-epoxy printed circuit board. Two 0.33uF and one 0.1uF decoupling capacitors per each SDRAM are mounted on the PCB. The Hynix HYM72V32M636T6M Series are Dual In-line Memory Modules suitable for easy interchange and addition of 256Mbytes memory. The Hynix HYM72V32M636T6M Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. FEATURES • PC133/PC100MHz support • SDRAM internal banks : four banks • 144pin SDRAM SO DIMM • Module bank : two physical bank • Serial Presence Detect with EEPROM • Auto refresh and self refresh • 1.25” (31.75mm) Height PCB with double sided components • 8192 refresh cycles / 64ms • Programmable Burst Length and Burst Type • Single 3.3±0.3V power supply • All device pins are compatible with LVTTL interface • Data mask function by DQM - 1, 2, 4 or 8 or Full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst • Programmable CAS Latency ; 2, 3 Clocks ORDERING INFORMATION Part No. Clock Frequency Internal Bank Ref. Power SDRAM Package Plating TSOP-II Gold HYM72V32M636T6M-HP Normal HYM72V32M636T6M-H 133MHz 4 Banks 4K HYM72V32M636LT6M-HP Low Power HYM72V32M636LT6M-H This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0/Sep. 01 PC133 SDRAM SO DIMM HYM72V32M636(L)T6M Series PIN DESCRIPTION PIN PIN NAME DESCRIPTION CK0, CK1 Clock Inputs The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK CKE0, CKE1 Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh /S0, /S1 Chip Select Enables or disables all inputs except CK, CKE and DQM BA0, BA1 SDRAM Bank Address Selects bank to be activated during /RAS activity Selects bank to be read/written during /CAS activity A0 ~ A12 Address Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8 Auto-precharge flag : A10 /RAS, /CAS, /WE Row Address Strobe, Column Address Strobe, Write Enable /RAS, /CAS and /WE define the operation Refer function truth table for details DQM0~DQM7 Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ63 Data Input/Output Multiplexed data input / output pin VCC Power Supply (3.3V) Power supply for internal circuits and input buffers VSS Ground Ground SCL SPD Clock Input Serial Presence Detect Clock input SDA SPD Data Input/Output Serial Presence Detect Data input/output SA0~2 SPD Address Input Serial Presence Detect Address Input WP Write Protect for SPD Write Protect for Serial Presence Detect on DIMM NC No Connection No connection Rev. 1.0/Sep. 01 3 PC133 SDRAM SO DIMM HYM72V32M636(L)T6M Series PIN ASSIGNMENTS FRONT SIDE BACK SIDE PIN NO. NAME PIN NO. 1 VSS 3 DQ0 5 7 FRONT SIDE BACK SIDE NAME PIN NO. NAME PIN NO. 2 VSS 71 /S1 72 NC 4 DQ32 73 NC 74 CK1 DQ1 6 DQ33 75 VSS 76 VSS DQ2 8 DQ34 77 NC 78 NC 9 DQ3 10 DQ35 79 NC 80 NC 11 VCC 12 VCC 81 VCC 82 VCC 13 DQ4 14 DQ36 83 DQ16 84 DQ48 15 DQ5 16 DQ37 85 DQ17 86 DQ49 17 DQ6 18 DQ38 87 DQ18 88 DQ50 19 DQ7 20 DQ39 89 DQ19 90 DQ51 21 VSS 22 VSS 91 VSS 92 VSS 23 DQM0 24 DQM4 93 DQ20 94 DQ52 25 DQM1 26 DQM5 95 DQ21 96 DQ53 27 VCC 28 VCC 97 DQ22 98 DQ54 29 A0 30 A3 99 DQ23 100 DQ55 31 A1 32 A4 101 VCC 102 VCC 33 A2 34 A5 103 A6 104 A7 35 VSS 36 VSS 105 A8 106 BA0 37 DQ8 38 DQ40 107 VSS 108 VSS 39 DQ9 40 DQ41 109 A9 110 BA1 41 DQ10 42 DQ42 111 A10/AP 112 A11 43 DQ11 44 DQ43 113 VCC 114 VCC 45 VCC 46 VCC 115 DQM2 116 DQM6 47 DQ12 48 DQ44 117 DQM3 118 DQM7 49 DQ13 50 DQ45 119 VSS 120 VSS 51 DQ14 52 DQ46 121 DQ24 122 DQ56 53 DQ15 54 DQ47 123 DQ25 124 DQ57 55 VSS 56 VSS 125 DQ26 126 DQ58 57 NC 58 NC 127 DQ27 128 DQ59 59 NC 60 NC 129 VCC 130 VCC 131 DQ28 132 DQ60 DQ61 Voltage Key NAME 133 DQ29 134 61 CK0 62 CKE0 135 DQ30 136 DQ62 63 VCC 64 VCC 137 DQ31 138 DQ63 65 /RAS 66 /CAS 139 VSS 140 VSS 67 /WE 68 CKE1 141 SDA 142 SCL 69 /S0 70 NC 143 VCC 144 VCC Rev. 1.0/Sep. 01 4 PC133 SDRAM SO DIMM HYM72V32M636(L)T6M Series BLOCK DIAGRAM S0 S1 DQMB0 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQML DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQMB1 DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39 DQMU DQMB2 DQ 16 DQ17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 DQML DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQMB3 DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ53 DQ 54 DQ 55 DQMU CS U0 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 CS U1 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 DQML DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQMU DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 DQML DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQMU DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 CS U4 CS U5 DQMB4 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 DQML DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQMB5 DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47 DQMU DQMB6 DQ 24 DQ25 DQ26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31 DQML DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQMB7 DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63 DQMU U0 - U7 U0 - U7 CK0 4 SDRAMS CAS U0 - U7 CK1 4SDRAMS WE U0 - U7 CKE0 U0 - U3 CKE1 U4 - U7 SCL U0 ~ U7 VSS U0 ~ U7 DQMU DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 DQML DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 CS U3 DQMU DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 RAS Capacitor two 0.33uF and one 0.1uF per SDRAM U2 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 A0 ~ A11, BA0,1 VCC DQML DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 CS U4 SERIAL PD A0 A1 CS U6 CS U7 SDA A2 VSS Note : 1. The serial resistor values of DQs are 10ohms Rev. 1.0/Sep. 01 5 PC133 SDRAM SO DIMM HYM72V32M636(L)T6M Series SERIAL PRESENCE DETECT BYTE NUMBER FUNCTION DESCRIPTION FUNCTION VALUE NOTE -H -HP -H -HP BYTE0 # of Bytes Written into Serial Memory at Module Manufacturer 128 Bytes 80h BYTE1 Total # of Bytes of SPD Memory Device 256 Bytes 08h BYTE2 Fundamental Memory Type BYTE3 # of Row Addresses on This Assembly SDRAM 04h 13 0Dh BYTE4 # of Column Addresses on This Assembly 9 09h BYTE5 # of Module Banks on This Assembly 2 Bank 02h BYTE6 Data Width of This Assembly 64 Bits 40h BYTE7 Data Width of This Assembly (Continued) - 00h BYTE8 Voltage Interface Standard of This Assembly BYTE9 SDRAM Cycle Time @/CAS Latency=3 7.5ns 7.5ns 75h BYTE10 Access Time from Clock @/CAS Latency=3 5.4ns 5.4ns 54h BYTE11 DIMM Configuration Type BYTE12 Refresh Rate/Type BYTE13 Primary SDRAM Width BYTE14 Error Checking SDRAM Width BYTE15 Minimum Clock Delay Back to Back Random Column Address LVTTL 1 01h 75h 54h None 00h 7.8125us / Self Refresh Supported 82h x16 10h None 00h tCCD = 1 CLK 01h 1,2,4,8,Full Page 8Fh 4 Banks 04h /CAS Latency=2,3 06h BYTE16 Burst Lenth Supported BYTE17 # of Banks on Each SDRAM Device BYTE18 SDRAM Device Attributes, /CAS Lataency BYTE19 SDRAM Device Attributes, /CS Lataency /CS Latency=0 01h BYTE20 SDRAM Device Attributes, /WE Lataency /WE Latency=0 01h BYTE21 SDRAM Module Attributes Neither Buffered nor Registered 00h +/- 10% voltage tolerence, Burst Read Single Bit Write, Precharge All, Auto Precharge, Early RAS Precharge 0Eh 2 BYTE22 SDRAM Device Attributes, General BYTE23 SDRAM Cycle Time @/CAS Latency=2 10ns - A0h 00h BYTE24 Access Time from Clock @/CAS Latency=2 5.4ns - 54h 00h BYTE25 SDRAM Cycle Time @/CAS Latency=1 - - 00h 00h BYTE26 Access Time from Clock @/CAS Latency=1 - - 00h 00h BYTE27 Minimum Row Precharge Time (tRP) 20ns 20ns 14h 14h BYTE28 Minimum Row Active to Row Active Delay (tRRD) 15ns 15ns 0Fh 0Fh BYTE29 Minimum /RAS to /CAS Delay (tRCD) 20ns 20ns 14h 14h BYTE30 Minimum /RAS Pulse Width (tRAS) 45ns 45ns 2Dh 2Dh BYTE31 Module Bank Density BYTE32 Command and Address Signal Input Setup Time 1.5ns 1.5ns 15h 15h BYTE33 Command and Address Signal Input Hold Time 0.8ns 0.8ns 08h 08h BYTE34 Data Signal Input Setup Time 1.5ns 1.5ns 15h 15h BYTE35 Data Signal Input Hold Time 0.8ns 0.8ns 08h BYTE36 ~61 Superset Information (may be used in future) BYTE62 SPD Revision BYTE63 Checksum for Byte 0~62 BYTE64 Manufacturer JEDEC ID Code BYTE65 ~71 ....Manufacturer JEDEC ID Code BYTE72 Manufacturing Location Rev. 1.0/Sep. 01 128MB 20h Intel SPD 1.2B - 08h 00h 12h 3, 8 BAh AEh Hynix JEDED ID ADh Unused FFh Hynix (Korea Area) HSA (United States Area) HSE (Europe Area) HSJ (Japan Area) ASIA Area 0*h 1*h 2*h 3*h 4*h 9 6 PC133 SDRAM SO DIMM HYM72V32M636(L)T6M Series Continued BYTE FUNCTION NUMBER DESCRIPTION BYTE73 Manufacturer’s Part Number (Component) BYTE74 Manufacturer’s Part Number (128Mb based) BYTE75 Manufacturer’s Part Number (Voltage Interface) BYTE76 FUNCTION VALUE NOTE -H -HP -H -HP 7 (SDRAM) 37h 4, 5 2 32h 4, 5 V (3.3V, LVTTL) 56h 4, 5 Manufacturer’s Part Number (Memory Width) 3 33h 4, 5 BYTE77 ....Manufacturer’s Part Number (Memory Width) 2 32h 4, 5 BYTE78 Manufacturer’s Part Number (Module Type) M(SODIMM) 4Dh 4, 5 BYTE79 Manufacturer’s Part Number (Data Width) 6 36h 4, 5 BYTE80 ....Manufacturer’s Part Number (Data Width) 5 35h 4, 5 BYTE81 Manufacturer’s Part Number (Refresh, SDRAM Bank) 6 (8K Refresh, 4Banks) 36h 4, 5 BYTE82 Manufacturer’s Part Number (Package Type) BYTE83 Manufacturer’s Part Number (Component Configuration) BYTE84 Manufacturer’s Part Number (PCB Revision) BYTE85 Manufacturer’s Part Number ( Hyphen) BYTE86 Manufacturer’s Part Number (Min. Cycle Time) H H 42h 42h 4, 5 BYTE87 ...Manufacturer’s Part Number (Min. Cycle Timet) P Blanks 50h 20h 4, 5 BYTE88 ~90 Manufacturer’s Part Number T 54h 4, 5 6 (x16 based) 36h 4, 5 M 4Dh - (Hyphen) 2Dh 4, 5 Blanks 20h 4, 5 BYTE91 Revision Code (for Component) Process Code - 4, 6 BYTE92 ....Revision Code (for PCB) Process Code - 4, 6 BYTE93 Manufacturing Date Work Week - 3, 6 BYTE94 ....Manufacturing Date Year - 3, 6 Serial Number - 6 None 00h BYTE95 ~98 BYTE99 ~125 Assembly Serial Number Manufacturer Specific Data (may be used in future) BYTE126 Reserved BYTE127 Intel Specification Details for 100MHz Support 100MHz BYTE128 ~256 Unused Storage Locations 64h Refer to Note7 A7h - 7, 8, 9 A5h 7, 8, 9 00h Note : 1. The bank address is excluded 2. 1, 2, 4, 8 for Interleave Burst Type 3. BCD adopted 4. ASCII adopted 5. Basically Hynix writes Part No. except for ‘H YM’ in Byte 73~90 to use the limited 18 bytes from byte 73 to byte 90 6. Not fixed but dependent 7. CK0, CK1 connected to DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge support 8. Refer to the most recent Intel and JEDEC SPD Specification 9. These values are applied to PC100 applications only per Intel PC SDRAM specification 10. Refer to HEI Web site. Byte 83~87 for L-Part BYTE NUMBER FUNCTION DESCRIPTION FUNCTION VALUE NOTE -HP -H -HP -H BYTE83 Manufacturer’s Part Number (Power) L 4Ch 4, 5 BYTE84 Manufacturer’s Part Number (Package Type) T 54h 4, 5 BYTE85 Manufacturer’s Part Number (Component Configuration) 6 (x16 based) 36h 4, 5 BYTE86 Manufacturer’s Part Number (Module Revision) M 4Dh 4, 5 - (Hyphen) 2Dh 4, 5 BYTE87 Manufacturer’s Part Number (Hyphent) BYTE88 Manufacturer’s Part Number (Module Revision) H H 42h 42h 4, 5 BYTE89 Manufacturer’s Part Number (Module Revision) P Blanks 50h 20h 4, 5 Rev. 1.0/Sep. 01 7 PC133 SDRAM SO DIMM HYM72V32M636(L)T6M Series ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Ambient Temperature TA 0 ~ 70 °C Storage Temperature TSTG -55 ~ 125 °C Voltage on Any Pin relative to V S S V IN , V O U T -1.0 ~ 4.6 V Voltage on V D D relative to V S S V DD, V D D Q -1.0 ~ 4.6 V Short Circuit Output Current IO S 50 mA Power Dissipation PD 1 W Soldering Temperature ⋅ Time TSOLDER 260 ⋅ 10 ° C ⋅ Sec Note : Operation at above absolute maximum rating can adversely affect device reliability. DC OPERATING CONDITION Parameter (T A =0 to 70 ° C ) Symbol Min Typ Max Unit Note Power Supply Voltage VDD, VDDQ 3.0 3.3 3.6 V 1 Input High voltage V IH 2.0 3.0 V D D Q + 0.3 V 1,2 Input Low voltage V IL -0.3 0 0.8 V 1,3 Note Note : 1.All voltages are referenced to V SS = 0V 2.V IH (max) is acceptable 5.6V AC pulse width with <=3ns of duration. 3.V IL (min) is acceptable -2.0V AC pulse width with <=3ns of duration. AC OPERATING TEST CONDITION (T A =0 to 70 ° C , V D D =3.3 ± 0.3V, V SS =0V) Parameter Symbol Value Unit AC Input High / Low Level Voltage V IH / V IL 2.4/0.4 V Vtrip 1.4 V tR / tF 1 ns Voutref 1.4 V CL 50 pF Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement 1 Note : 1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output load circuit Rev. 1.0/Sep. 01 8 PC133 SDRAM SO DIMM HYM72V32M636(L)T6M Series CAPACITANCE (TA=25 ° C , f=1MHz) -HP/H Parameter Pin Symbol Unit Min Max CK0, CK1 C I1 30 40 pF CKE0, CKE1 C I2 20 30 pF /S0, /S1 C I3 20 35 pF A0~11, BA0, BA1 C I4 30 55 pF /RAS, /CAS, /WE C I5 30 55 pF DQM0~DQM7 CI 6 5 20 pF DQ0 ~ DQ63 C I/O 10 20 pF Input Capacitance Data Input / Output Capacitance OUTPUT LOAD CIRCUIT Vtt=1.4V RT=250 Ω Output Output 50pF DC Output Load Circuit Rev. 1.0/Sep. 01 50pF AC Output Load Circuit 9 PC133 SDRAM SO DIMM HYM72V32M636(L)T6M Series (TA=0 to 70 ° C , V D D =3.3 ± 0.3V) DC CHARACTERISTICS I Parameter Symbol Min. Max Unit Note Input Leakage Current I LI -8 8 uA 1 Output Leakage Current IL O -1 1 uA 2 Output High Voltage VOH 2.4 - V I O H = -4mA Output Low Voltage VOL - 0.4 V I O L = +4mA Note : 1.V IN = 0 to 3.6V, All other pins are not tested under V IN =0V 2.D O U T is disabled, V O U T =0 to 3.6 DC CHARACTERISTICS II Speed Parameter Symbol Test Condition -HP -H 600 600 ID D 1 Burst length=1, One bank active t R C ≥ t R C (min), I OL =0mA ID D 2 P C K E ≤ V IL (max), t C K = 15ns 16 ID D 2 P S C K E ≤ V IL (max), t C K = ∞ 16 ID D 2 N C K E ≥ V IH (min), CS ≥ V IH (min), t C K = 15ns Input signals are changed one time during 30ns. All other pins ≥ V D D -0.2V or ≤ 0.2V ID D 2 N S C K E ≥ V IH (min), t C K = ∞ Input signals are stable. 80 ID D 3 P C K E ≤ V IL (max), t C K = 15ns 56 ID D 3 P S C K E ≤ V IL (max), t C K = ∞ 56 ID D 3 N C K E ≥ V IH (min), CS ≥ V IH (min), t C K = 15ns Input signals are changed one time during 30ns. All other pins ≥ V D D -0.2V or ≤ 0.2V 320 ID D 3 N S C K E ≥ V IH (min), t C K = ∞ Input signals are stable. 320 Burst Mode Operating Current ID D 4 t C K ≥ t C K (min), I OL =0mA All banks active Auto Refresh Current ID D 5 t R R C ≥ t R R C (min), All banks active Self Refresh Current ID D 6 C K E ≤ 0.2V Operating Current Precharge Standby Current in Power Down Mode Note mA 1 mA Precharge Standby Current in Non Power Down Mode Active Standby Current in Power Down Mode Unit 160 mA mA Active Standby Current in Non Power Down Mode mA CL=3 800 800 CL=2 800 720 1920 1760 mA 1 mA 2 24 mA 3 12 mA 4 Note : 1. I D D 1 and I D D 4 depend on output loading and cycle rates. Specified values are measured with the output open 2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3.HYM72V32M636T6M-HP/H 4.HYM72V32M636LT6M-HP/H Rev. 1.0/Sep. 01 10 PC133 SDRAM SO DIMM HYM72V32M636(L)T6M Series AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) HP Parameter Unit Min System Clock Cycle Time C A S Latency = 3 -H Symbol tCK3 Max 7.5 Min 7.5 1000 C A S Latency = 2 Note Max ns 1000 tCK2 10 Clock High Pulse Width tCHW 2.5 - 2.5 - ns 1 Clock Low Pulse Width tCLW 2.5 - 2.5 - ns 1 C A S Latency = 3 tAC3 - 5.4 - 5.4 ns C A S Latency = 2 tAC2 - 6 - 6 ns Data-Out Hold Time tOH 2.7 - 2.7 - ns Data-Input Setup Time tDS 1.5 - 1.5 - ns 1 Data-Input Hold Time tDH 0.8 - 0.8 - ns 1 Address Setup Time tAS 1.5 - 1.5 - ns 1 Address Hold Time tAH 0.8 - 0.8 - ns 1 CKE Setup Time tCKS 1.5 - 1.5 - ns 1 CKE Hold Time tCKH 0.8 - 0.8 - ns 1 Command Setup Time tCS 1.5 - 1.5 - ns 1 Command Hold Time tCH 0.8 - 0.8 - ns 1 CLK to Data Output in Low-Z Time tOLZ 1 - 1 - ns Access Time From Clock CLK to Data Output in High-Z Time 10 ns 2 C A S Latency = 3 tOHZ3 2.7 5.4 2.7 5.4 ns C A S Latency = 2 tOHZ2 2.7 5.4 3 6 ns Note : 1.Assume tR / tF (input rise and fall time ) is 1ns If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter 2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter Rev. 1.0/Sep. 01 11 PC133 SDRAM SO DIMM HYM72V32M636(L)T6M Series AC CHARACTERISTICS II -HP Parameter -H Symbol Unit Min Max Min Max Operation tRC 60 - 65 - ns Auto Refresh tRRC 60 - 65 - ns R A S to C A S Delay tRCD 15 - 20 - ns R A S Active Time tRAS 45 100K 45 100K ns R A S Precharge Time tRP 15 - 20 - ns R A S to R A S Bank Active Delay tRRD 15 - 15 - ns C A S to C A S Delay tCCD 1 - 1 - CLK Write Command to Data-In Delay tWTL 0 - 0 - CLK Data-In to Precharge Command tDPL 2 - 2 - CLK Data-In to Active Command tDAL 4 - 5 - CLK DQM to Data-Out Hi-Z tDQZ 2 - 2 - CLK DQM to Data-In Mask tDQM 0 - 0 - CLK MRS to New Command tMRD 2 - 2 - CLK C A S Latency = 3 tPROZ3 3 - 3 - CLK C A S Latency = 2 tPROZ2 2 - 2 - CLK Power Down Exit Time tPDE 1 - 1 - CLK Self Refresh Exit Time tSRE 1 - 1 - CLK Refresh Time tREF - 64 - 64 ms Note R A S Cycle Time Precharge to Data Output Hi-Z 1 Note : 1. A new command can be given tRRC after self refresh exit Rev. 1.0/Sep. 01 12 PC133 SDRAM SO DIMM HYM72V32M636(L)T6M Series DEVICE OPERATING OPTION TABLE HYM72V32M636(L)T6M-HP CAS Latency tRCD tRAS tRC tRP tAC tOH 133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns HYM72V32M636(L)T6M-H CAS Latency tRCD tRAS tRC tRP tAC tOH 133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns Rev. 1.0/Sep. 01 13 PC133 SDRAM SO DIMM HYM72V32M636(L)T6M Series COMMAND TRUTH TABLE Command A10/ AP CKEn-1 CKEn CS RAS CAS WE DQM Mode Register Set H X L L L L X OP code No Operation H X X X Bank Active H ADDR H X X X L H H H X L L H H X H X L H L H X CA H X L H L L X CA H X L L H L X X Burst Stop H X L H H L X X DQM H V X Auto Refresh H H L L H Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst-Read-SingleWRITE Self Refresh1 X L L H X Entry H L L L L H X Exit L H Entry H L Exit L H Entry H L Exit L H X X X L H H H H X X X L H H H H X X X L H H H H X X X L V V V X L H V V H X L V X L H L H A9 Pin High (Other Pins OP code) X X Note V X H Precharge power down Clock Suspend L RA BA X X X X X X X Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation Rev. 1.0/Sep. 01 14 PC133 SDRAM SO DIMM HYM72V32M636(L)T6M Series PACKAGE DEMENSION Rev. 1.0/Sep. 01 15