ETC HYM7V73A801BTFG-75

8Mx72 bits
PC133 SDRAM Unbuffered DIMM
based on 8Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM7V73A801B F-Series
DESCRIPTION
The Hynix HYM7V73A801B F-Series are 8Mx72bits ECC Synchronous DRAM Modules. The modules are composed of
nine 8Mx8bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP
package on a 168pin glass-epoxy printed circuit board. A 0.33uF and a 0.1uF decoupling capacitors per each SDRAM
are mounted on the PCB.
The HYM7V73A801B F-Series are Dual In-line Memory Modules suitable for easy interchange and addition of 64Mbytes
memory. The HYM7V75A801B F-Series are offering fully synchronous operation referenced to a positive edge of the
clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally
pipelined to achieve very high bandwidth.
FEATURES
• PC133/100MHz support
• SDRAM internal banks : four banks
• 168pin SDRAM Unbuffered DIMM
• Module bank : one physical bank
• Serial Presence Detect with EEPROM
• Auto refresh and self refresh
• 1.375” (34.93mm) Height PCB with Single Sided
components
• 4096 refresh cycles / 64ms
• Single 3.3 ± 0.3V power supply
• All devices pins are compatible with LVTTL interface
• Data mask function by DQM
• Programmable Burst Length and Burst Type
-. 1, 2, 4, 8, or Full Page for Sequential Burst
-. 1, 2, 4 or 8 for Interleave Burst
• Programmable /CAS Latency
-. 2, 3 clocks
ORDERING INFORMATION
PART NO.
MAX.
FREQUENCY
INTERNAL
BANK
REF.
POWER
SDRAM
PACKAGE
PLATING
HYM7V73A801BTFG-75
133MHz
4 Banks
4K
Normal
TSOP-II
Gold
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1/Apr.01
1999 Hyundai Electronics
PC133 SDRAM Unbuffered DIMM
HYM7V73A801B F-Series
PIN DESCRIPTION
PIN NAME
DESCRIPTION
CK0~CK3
Clock Inputs
The System Clock Input. All other inputs are registered to the
SDRAM on the rising edge of CLK.
CKE0
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
/S0, /S2
Chip Select
Enables or disables all inputs except CK, CKE and DQM.
BA0, BA1
SDRAM Bank Address
A0~A11
Address Inputs
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
Write Enable
DQM0~DQM7
Data Input/Output Mask
Controls output buffers in read mode and masks input data in
write mode.
DQ0~DQ63
Data Input/Output
Multiplexed data input/output pins
CB0~CB7
ECC Data Input/Output
Error Checking and Correction Bits
VCC
Power Supply (3.3V)
Power supply for internal circuits and input/output buffers
VSS
Ground
Ground
SCL
SPD Clock Input
Serial Presence Detect Clock Input
SDA
SPD Data Input/Output
Serial Presence Detect Data input/output
SA0~SA2
SPD Address Input
Serial Presence Detect Address input
WP
Write Protect for SPD
Write Protect for Serial Presence Detect on DIMM
NC
No Connect
No Connect or Don’t Use
Rev. 1.1/Apr.01
Select bank to be activated during /RAS activity.
Select bank to be read/written during /CAS activity
Row address : RA0~RA11, Column address : CA0~CA8
Auto-precharge flag : A10
/RAS define the operation.
Refer to the function truth table for details.
/CAS define the operation.
Refer to the function truth table for details.
/WE define the operation.
Refer to the function truth table for details.
2
PC133 SDRAM Unbuffered DIMM
HYM7V73A801B F-Series
PIN ASSIGNMENTS
FRONT SIDE
PIN NO.
NAME
1
2
3
4
5
6
7
8
9
10
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
BACK SIDE
PIN NO.
NAME
85
86
87
88
89
90
91
92
93
94
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
Architecture Key
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
CB0
CB1
VSS
NC
NC
VCC
/WE
DQM0
DQM1
/S0
NC
VSS
A0
A2
A4
A6
A8
A10/AP
BA1
VCC
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
Voltage Key
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
CB4
CB5
VSS
NC
NC
VCC
/CAS
DQM4
DQM5
NC
/RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VCC
FRONT SIDE
PIN NO.
NAME
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
VCC
CK0
VSS
NC
/S2
DQM2
DQM3
NC
VCC
NC
NC
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VCC
DQ20
NC
NC
NC
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
CK2
NC
WP
SDA
SCL
VCC
BACK SIDE
PIN NO.
NAME
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
*CK1
NC
VSS
CKE0
NC
DQM6
DQM7
NC
VCC
NC
NC
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VCC
DQ52
NC
NC
NC
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
*CK3
NC
SA0
SA1
SA2
VCC
Note : *. CK1, CK3 are connected with termination R/C. (Refer to the Block Diagram.)
Rev. 1.1/Apr.01
3
PC133 SDRAM Unbuffered DIMM
HYM7V73A801B F-Series
BLOCK DIAGRAM
Note : 1. The serial resistor values of DQs are 10 Ohms.
2. The padding capacitance of termination R/C for CK1, CK3 is 10pF.
Rev. 1.1/Apr.01
4
PC133 SDRAM Unbuffered DIMM
HYM7V73A801B F-Series
SERIAL PRESENCE DETECT
BYTE
FUNCTION
FUNCTION
VALUE
NUMBER
DESCRIBED
-75
-75
BYTE0
# of Bytes Written into Serial Memory
at Module Manufacturer
128 Bytes
80h
BYTE1
Total # of Bytes of SPD Memory Device
256 Bytes
08h
BYTE2
Fundamental Memory Type
BYTE3
SDRAM
04h
# of Row Addresses on This Assembly
12
0Ch
BYTE4
# of Column Addresses on This Assembly
9
09h
BYTE5
# of Module Banks on This Assembly
1 Bank
01h
BYTE6
Data Width of This Assembly
72 Bits
48h
BYTE7
Data Width of This Assembly (Continued)
-
00h
BYTE8
Voltage Interface Standard of This Assembly
LVTTL
01h
BYTE9
SDRAM Cycle Time @ /CAS Latency=3
7.5ns
75h
BYTE10
Access Time from Clock @ /CAS Latency=3
5.4ns
54h
BYTE11
DIMM Configuration Type
ECC
02h
15.625µs
/ Self Refresh Supported
80h
BYTE12
Refresh Rate/Type
BYTE13
Primary SDRAM Width
x8
08h
BYTE14
Error Checking SDRAM Width
x8
08h
BYTE15
Minimum Clock Delay Back to Back Random
Column Address
BYTE16
Burst Lengths Supported
BYTE17
# of Banks on Each SDRAM Device
BYTE18
SDRAM Device Attributes, CAS # Latency
BYTE19
SDRAM Device Attributes, CS # Latency
BYTE20
SDRAM Device Attributes, Write Latency
BYTE21
SDRAM Module Attributes
tCCD = 1 CLK
01h
1,2,4,8,Full Page
8Fh
4 Banks
04h
/CAS Latency=2,3
06h
/CS Latency=0
01h
/WE Latency=0
01h
Neither Buffered nor Registered
00h
+/-10% voltage tolerance, Burst
Read Single bit Write, Precharge
All, Auto Precharge, Early RAS
Precharge
0Eh
BYTE22
SDRAM Device Attributes, General
BYTE23
SDRAM Cycle Time @ /CAS Latency=2
10ns
A0h
BYTE24
Access Time from Clock @ /CAS Latency=2
6ns
60h
BYTE25
SDRAM Cycle Time @ /CAS Latency=1
-
00h
BYTE26
Access Time from Clock @ /CAS Latency=1
-
00h
BYTE27
Minimum Row Precharge Time (tRP)
20ns
14h
BYTE28
Minimum Row Active to Row Active Delay (tRRD)
15ns
0Fh
BYTE29
Minimum /RAS to /CAS Delay (tRCD)
20ns
14h
BYTE30
Minimum /RAS Pulse width (tRAS)
45ns
2Dh
BYTE31
Module Bank Density
64MB
10h
BYTE32
Command and Address Signal Input Setup Time
1.5ns
15h
BYTE33
Command and Address Signal Input Hold Time
0.8ns
08h
BYTE34
Data Signal Input Setup Time
1.5ns
15h
BYTE35
Data Signal Input Hold Time
0.8ns
08h
BYTE36
–61
Superset Information (may be used in future)
-
00h
BYTE62
SPD Revision
Intel SPD 1.2
12h
BYTE63
Checksum for Bytes 0~62
-
B0h
BYTE64
Manufacturer JEDEC ID Code
Hynix JEDEC ID
ADh
BYTE65
~71
....Manufacturer JEDEC ID Code
Unused
FFh
BYTE72
Manufacturing Location
Rev. 1.1/Apr.01
Hynix (Korea Area)
0*h
HSA (United States Area)
HSU (Europe Area)
1*h
2*h
HSJ (Japan Area)
Asia Area
3*h
4*h
NOTE
1
2
3, 4
9
5
PC133 SDRAM Unbuffered DIMM
HYM7V73A801B F-Series
Continued
BYTE
FUNCTION
FUNCTION
VALUE
NUMBER
DESCRIBED
-75
-75
BYTE73
Manufacturer’s Part Number (Component)
BYTE74
Manufacturer’s Part Number (Voltage Interface)
BYTE75
NOTE
7 (SDRAM)
37h
5, 6
V (3.3V, LVTTL)
56h
5, 6
Manufacturer’s Part Number (Data Width)
7
37h
5, 6
BYTE76
....Manufacturer’s Part Number (Data Width)
3
33h
5, 6
BYTE77
Manufacturer’s Part Number (ECC)
A
41h
5, 6
BYTE78
Manufacturer’s Part Number (Memory Depth)
8
38h
5, 6
BYTE79
Manufacturer’s Part Number (Refresh)
0 (4K Refresh)
30h
5, 6
BYTE80
Manufacturer’s Part Number (Internal Banks)
1 (4 Banks)
31h
5, 6
BYTE81
Manufacturer’s Part Number (Generation)
B
42h
5, 6
BYTE82
Manufacturer’s Part Number (Package Type)
T (TSOPII)
54h
5, 6
BYTE83
Manufacturer’s Part Number (Module Type)
F (x8 based Unbuffered DIMM)
46h
5, 6
BYTE84
Manufacturer’s Part Number (Plating Type)
G (Gold)
47h
5, 6
BYTE85
Manufacturer’s Part Number (Hyphen)
- (Hyphen)
2Dh
5, 6
BYTE86
Manufacturer’s Part Number (Min. Cycle Time)
7
37h
5, 6
BYTE87
....Manufacturer’s Part Number (Min. Cycle Time)
5
35h
5, 6
BYTE88
~90
Manufacturer’s Part Number
Blanks
20h
5, 6
BYTE91
Revision Code (for Component)
Process Code
-
5, 7
BYTE92
....Revision Code (for PCB)
Process Code
-
5, 7
BYTE93
Manufacturing Date
Work Week
-
3, 7
BYTE94
....Manufacturing Date
Year
-
3, 7
Serial Number
-
7
None
00h
BYTE95
~98
Assembly Serial Number
BYTE99
~125
Manufacturer Specific Data (may be used in
future)
BYTE126
Reserved
Refer to Note8
64h
4, 8
BYTE127
Intel specification details 100MHZ support
Refer to Note8
A7h
4, 8
BYTE128
~256
Unused Storage Locations
-
00h
Note: 1. The bank address is excluded.
2. 1,2,4,8 for Interleave Burst Type
3. BCD adopted.
4. Refer to the most recent version of the Intel and JEDEC SPD Specification.
5. ASCII adopted.
6. Basically Hynix writes Part No. except for ` HYM ` in Byte 73-90 to use the limited 18 bytes from byte 73 to 90 efficiently.
7. Not fixed but dependent.
8. These values apply to PC100 applications only, per Intel PC SDRAM SPD specification
9. Refer to Hynix Web Site
Rev. 1.1/Apr.01
6
PC133 SDRAM Unbuffered DIMM
HYM7V73A801B F-Series
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
0 ~ 70
°C
Ambient Temperature
TA
Storage Temperature
TSTG
-55 ~ 125
°C
Voltage on any Pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD relative to VSS
VDD, VDDQ
-1.0 ~ 4.6
V
Short Circuit Output Current
IOS
50
MA
Power Dissipation
PD
9
W
Soldering Temperature · Time
TSOLDER
260 · 10
°C · Sec
Note : Operation at above absolute maximum can adversely affect device reliability.
DC OPERATING CONDITION
(TA = 0 to 70°C)
PARAMETER
SYMBOL
MIN
TYP.
MAX
UNIT
NOTE
Power Supply Voltage
VCC
3.0
3.3
3.6
V
1
Input High Voltage
VIH
2.0
3.0
VCC + 2.0
V
1, 2
Input Low Voltage
VIL
VSS – 2.0
0
0.8
V
1, 3
Note : 1. All voltage are referenced to VSS = 0V.
2. VIH (max) is acceptable 5.6V AC pulse width with ≤ 3ns of duration.
3. VIL (min) is acceptable –2.0V AC pulse width with ≤ 3ns of duration.
AC OPERATING CONDITION
(TA = 0 to 70°C, VDD = 3.3 ± 0.3V, VSS = 0V)
PARAMETER
SYMBOL
VALUE
UNIT
2.4 / o.4
V
1.4
V
AC Input High / Low Level Voltage
VIH / VIL
Input Timing Measurement Reference Level Voltage
Vtrip
Input Rise / Fall Time
tR / tF
1
ns
Output Timing Measurement Reference Level Voltage
Voutref
1.4
V
Output Load Capacitance for Access Time Measurement
CL
*Note
pF
Note : *. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF).
For details, refer to AC/DC output circuit.
Rev. 1.1/Apr.01
7
PC133 SDRAM Unbuffered DIMM
HYM7V73A801B F-Series
CAPACITANCE
(TA = 25°C, f = 1MHz)
PARAMETER
Input Capacitance
Data Input/Output Capacitance
PIN
SYMBOL
MIN
MAX
TYP.
UNIT
CK0, CK2
CIN1
-
50
-
pF
CKE0
CIN2
-
65
-
pF
/S0, /S2
CIN3
-
45
-
pF
A0~A11, BA0, BA1
CIN4
-
65
-
pF
/RAS, /CAS, /WE
CIN5
-
65
-
pF
DQM0~DQM7
CIN6
-
20
-
pF
DQ0~DQ63, CB0~CB7
CI/O
-
15
-
pF
OUTPUT LOAD CIRCUIT
Rev. 1.1/Apr.01
8
PC133 SDRAM Unbuffered DIMM
HYM7V73A801B F-Series
DC CHARACTERISTICS I
(TA = 0 to 70°C, VDD = 3.3 ± 0.3V)
PARAMETER
SYMBOL
MIN
MAX
UNIT
NOTE
Input Leakage Current
ILI
-9
9
uA
1
Output Leakage Current
ILO
-1
1
uA
2
Output High Voltage
VOH
2.4
-
V
IOH = -4mA
Output Low Voltage
VOL
-
0.4
V
IOL = +4mA
Note : 1. VIN = 0 to 3.6V. All other pins are not tested under VIN = 0V.
2. DOUT is disabled. VOUT = 0 to 3.6V.
DC CHARACTERISTICS II
(TA = 0 to 70°C, VDD = 3.3 ± 0.3V, VSS = 0V)
SPEED
P ARAMETER
SYMBOL
TEST CONDITION
UNIT
NOTE
810
mA
1
-75
Operating Current
Precharge Standby Current
in Power Down Mode
IDD1
Burst Length = 1, One bank active
tRC ≥ tRC(min), IOL = 0mA
IDD2P
CKE ≤ VIL(max), tCK = min
18
mA
IDD2PS
CKE ≤ VIL(max), tCK = ∞
18
mA
IDD2N
CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = min
Input signals are changed one time during
2clks. All other pins ≥ VDD – 0.2V or ≤ 0.2V
135
mA
IDD2NS
CKE ≥ VIH(max), tCK = ∞
Input signals are stable.
135
mA
IDD3P
CKE ≤ VIL(max), tCK = min
45
mA
IDD3PS
CKE ≤ VIL(max), tCK = ∞
45
mA
IDD3N
CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = min
Input signals are changed one time during
2clks. All other pins ≥ VDD – 0.2V or ≤ 0.2V
270
mA
IDD3NS
CKE ≥ VIH(max), tCK = ∞
Input signals are stable.
270
mA
Precharge Standby Current
in Non Power Down Mode
Active Standby Current
in Power Down Mode
Active Standby Current
in Non Power Down Mode
Burst
Mode
Current
Operating
IDD4
tCK ≥ tCK(min), IOL = 0mA
CL = 3
1080
All banks active
CL = 2
810
Auto Refresh Current
IDD5
tRRC ≥ tRRC(min), All banks active
Self Refresh Current
IDD6
CKE ≤ 0.2V
mA
1
1800
mA
2
18
mA
Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.
2. Min. of tRRC (Refresh /RAS cycle time) is shown at AC CHARACTERISTICS II.
Rev. 1.1/Apr.01
9
PC133 SDRAM Unbuffered DIMM
HYM7V73A801B F-Series
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
-75
P ARAMETER
SYMBOL
UNIT
MIN
/CAS Latency = 3
tCK3
7.5
/CAS Latency = 2
tCK2
10
Clock High Pulse Width
tCHW
Clock Low Pulse Width
System Clock
Cycle Time
Access Time
from Clock
NOTE
MAX
1000
ns
2.5
-
ns
I
tCLW
2.5
-
ns
I
/CAS Latency = 3
tAC3
-
5.4
ns
2
/CAS Latency = 2
tAC2
-
6
Data-Out Hold Time
tOH
2.7
-
ns
Data-Input Setup Time
tDS
1.5
-
ns
1
Data-Input Hold Time
tDH
0.8
-
ns
1
Address Setup Time
tDS
1.5
-
ns
1
Address Hold Time
tDH
0.8
-
ns
1
CKE Setup Time
tDS
1.5
-
ns
1
CKE Hold Time
tDH
0.8
-
ns
1
Command Setup Time
tDS
1.5
-
ns
1
Command Hold Time
tDH
0.8
-
ns
1
CLK to Data Output in Low-Z time
tOLZ
1
-
ns
CLK to Data
Output
in
High-Z time
/CAS Latency = 3
tOHZ3
2.7
5.4
/CAS Latency = 2
tOHZ2
3
6
ns
Note : 1. Assume tR / tF (input rise and fall time) is 1ns.
2. Access times to be measured with input signals of 1v/ns edge rate.
Rev. 1.1/Apr.01
10
PC133 SDRAM Unbuffered DIMM
HYM7V73A801B F-Series
AC CHARACTERISTICS II
-75
P ARAMETER
SYMBOL
UNIT
MIN
Operation
tRC
65
Auto Refresh
tRRC
65
/RAS to /CAS Delay
tRCD
/RAS Active Time
/RAS
Time
Cycle
NOTE
MAX
-
ns
20
-
ns
tRAS
45
100K
ns
/RAS Precharge Time
tRP
20
-
/RAS to /RAS Bank Active Delay
tRRD
15
-
ns
/CAS to /CAS Delay
tCCD
1
-
CLK
Write Command to Data-in Delay
tWTL
0
-
CLK
Data-in to Precharge Command
tDPL
1
-
CLK
Data-in to Active Command
tDAL
4
-
CLK
DQM to Data-out Hi-Z
tDQZ
2
-
CLK
DQM to Data-in Mask
tDQM
0
-
CLK
MRS to New Command
tMRD
2
-
CLK
Precharge to
Data
Output
Hi-Z
/CAS Latency = 3
tPROZ3
3
-
/CAS Latency = 2
tPROZ2
2
-
Power Down Exit Time
tPDE
1
-
CLK
Self Refresh Exit Time
tSRE
1
-
CLK
Refresh Time
tREF
-
64
ms
CLK
1
Note : 1. A new command can be given tRRC after self refresh exit.
Rev. 1.1/Apr.01
11
PC133 SDRAM Unbuffered DIMM
HYM7V73A801B F-Series
OPERATING OPTION TABLE
/CAS
LATENCY
tRCD
tRAS
tRC
tRP
tAC
tOH
133MHz (7.5ns)
3CLKS
3CLKS
6CLKS
9CLKS
3CLKS
5.4ns
2.7ns
125MHz (8.0ns)
3CLKS
3CLKS
6CLKS
9CLKS
3CLKS
6ns
3ns
100MHz (10.0ns)
2CLKS
2CLKS
5CLKS
7CLKS
2CLKS
6ns
3ns
COMMAND TRUTH TABLE
ADDR
A10/
AP
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
DQM
Mode Register Set
H
X
L
L
L
L
X
OP code
H
X
X
X
No Operation
H
X
L
H
H
H
X
X
Bank Active
H
X
L
L
H
H
X
H
X
L
H
L
H
X
RA
BA
NOTE
V
Read
L
CA
V
Read with Autoprecharge
H
Write
L
Write with Autoprecharge
H
X
L
H
L
L
X
CA
H
X
L
L
H
L
X
X
H
Precharge All Banks
Precharge Selected Bank
Burst Stop
H
DQM
H
Auto Refresh
H
H
L
L
L
H
L
L
L
H
X
Entry
X
L
H
H
L
X
X
V
X
H
X
X
L
H
X
X
X
X
Self Refresh
Exit
L
H
Entry
H
L
Exit
L
H
Entry
H
L
Precharge
Power Down
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
V
H
X
L
V
X
X
1
X
X
X
X
Clock Suspend
X
Exit
L
H
X
X
Note : 1. Existing Self Refresh occurs by asynchronously bringing CKE from low to high.
2. X = Don’t care, H = Logic High, L = logic Low, BA = Bank Address, CA = Column Address, OP code = Operand code,
NOP = No operation
Rev. 1.1/Apr.01
12
PC133 SDRAM Unbuffered DIMM
HYM7V73A801B F-Series
PACKAGE DIMENSIONS
Rev. 1.1/Apr.01
13