HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules 3.3 V Low Profile 168-pin PC133 Registered SDRAM Modules for 1U Server Applications PC133 128 MByte Module PC133 256 MByte module PC133 512 MByte Module PC133 1024 MByte Module • 168-pin Registered 8 Byte Dual-In-Line SDRAM Module for Workstation and Server main memory applications with 1,2” inch (30,40 mm) height • Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) • All inputs and outputs are LVTTL compatible • One bank 16M × 72, 32M x 72 and 64M × 72 and two bank 128Mx72 organization • Utilizes SDRAMs in TSOPII-54 packages with on-board registers and PLL. • Optimized for ECC applications with very low input capacitances • Card Sizes : RawCard “F” and “G” 133.35 mm x 30,40 with gold contact pads • JEDEC standard Synchronous DRAMs (SDRAM) with 128Mb, 256Mb and 512Mb memory density. Stacked components for two bank modules • These modules all fully compatible with the current industry standard PC133 specifications and fully backward compatible to PC100 applications • Single + 3.3 V (± 0.3 V) power supply • Auto Refresh (CBR) and Self Refresh • Serial Presence Detect with E 2PROM • Performance: -7.5 Unit fCK3 Clock Frequency (max.) @ CL = 3 133 MHz tAC3 Clock Access Time (min.)@ CL = 3 5.4 ns fCK2 Clock Frequency (max.) @ CL = 2 100 MHz tAC2 Clock Access Time (min.)@ CL = 2 6 ns The HYS 72Vxx5/6x0GR-7.5 are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) organized as 16M × 72, 32M x 72, 64M × 72 and 128M x 72 high speed memory arrays designed with x4 or x8 organised Synchronous DRAMs (SDRAMs) for ECC applications. All control and address signals are registered on-DIMM and the design incorporates a PLL circuit for the Clock inputs. Use of an on-board register reduces capacitive loading on the input signals but are delayed by one cycle in arriving at the SDRAM devices. Decoupling capacitors are mounted on the PC board. The DIMMs use a serial presence detects scheme implemented via a serial E2PROM using the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint. This module family is designed with 30,40 mm (1.2 inch) maximum height for 1U Server Applications b ased on JEDEC standard RawCards “F” and “G”. INFINEON Technologies 1 1.02 HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules Ordering Information Type Compliance Code Description SDRAM Technology HYS 72V16600GR-7.5 PC133R-333-542-F one bank 128 MB Reg. DIMM 128 MBit (x8) HYS 72V32501GR-7.5 PC133R-333-542-G one bank 256 MB Reg. DIMM 128 MBit (x4) HYS 72V32600GR-7.5 PC133R-333-542-F one bank 256 MB Reg. DIMM 256 Mbit (x8) HYS 72V64500GR-7.5 PC133R-333-542-G one bank 512 MB Reg. DIMM 256 Mbit (x4) HYS 72V64601GR-7.5 PC133R-333-542-F 1.2” height: HYS 72V128520GR-7.5 PC133R-333-542-G Note: one bank 512 MB Reg. DIMM 512 MBit (x8) two banks 1024 MB Reg. DIMM 256 Mbit (x4) stacked All part numbers end with a place code (not shown), designating the die revision. Consult factory for current revision. Example: HYS 64V16600GR-7.5-C2, indicating Rev.C2 dies are used for SDRAM components. INFINEON Technologies 2 1.02 HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules Pin Definitions and Functions A0 - A11, A12 Address Inputs DQMB0 - DQMB7 Data Mask (A12 is used for 256Mbit and 512Mbit based modules only) BA0, BA1 Bank Selects CS0 - CS3 DQ0 - DQ63 Data Input/Output REGE *) Chip Select Register Enable “H” or N.C = registered mode “L” = buffered mode CB0 - CB7 Check Bits VDD Power (+ 3.3 V) RAS Row Address Strobe VSS Ground CAS Column Address Strobe SCL Clock for Presence Detect WE Read/Write Input SDA Serial Data Out CKE0 Clock Enable N.C. No Connection – – CLK0 - CLK3 Clock Input *) note : To confirm to this specification, motherboards must pull this pin to high state or no connect. Address Format Density Organization Memory SDRAMs Banks # of # of row/bank/ Refresh Period Interval SDRAMs columns bits 128 MB 16M × 72 1 16M x 8 9 12/2/10 4k 64 ms 15.6 µs 256 MB 32M x 72 1 32M x 4 18 12/2/11 4k 64 ms 15.6 µs 64 ms 7.8 µs 256 MB 32M x 72 1 32M x 8 9 13/2/10 8k 512 MB 64M × 72 1 64M × 4 18 13/2/11 8k 64 ms 7.8 µs 512 MB 64M × 72 1 64M × 8 9 13/2/12 8k 64 ms 7.8 µs 1 GB 2 64M × 4 36 13/2/11 8k 64 ms 7.8 µs 128M x 72 INFINEON Technologies 3 1.02 HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules Pin Configuration PIN# Symbol PIN# Symbol PIN# Symbol 1 PIN# Symbol VSS 43 VSS 85 VSS 127 VSS 2 3 DQ0 DQ1 44 45 DU CS2 86 87 DQ32 DQ33 128 129 CKE0 CS3 4 DQ2 46 DQMB2 88 DQ34 130 DQMB6 5 DQ3 47 DQMB3 89 DQ35 131 DQMB7 6 7 VDD DQ4 48 49 DU VDD 90 91 VDD DQ36 132 133 N.C. VDD 8 DQ5 50 N.C. 92 DQ37 134 N.C. 9 DQ6 51 N.C. 93 DQ38 135 N.C. 10 11 DQ7 DQ8 52 53 CB2 CB3 94 95 DQ39 DQ40 136 137 CB6 CB7 12 VSS 54 VSS 96 VSS 138 VSS 13 DQ9 55 DQ16 97 DQ41 139 DQ48 14 15 DQ10 DQ11 56 57 DQ17 DQ18 98 99 DQ42 DQ43 140 141 DQ49 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 VDD 101 DQ45 143 VDD 18 19 VDD DQ14 60 61 DQ20 N.C. 102 103 VDD DQ46 144 145 DQ52 N.C. 20 DQ15 62 DU 104 DQ47 146 DU 21 CB0 63 N.C. 105 CB4 147 REGE 22 23 CB1 VSS 64 65 VSS DQ21 106 107 CB5 VSS 148 149 VSS DQ53 24 N.C. 66 DQ22 108 N.C. 150 DQ54 25 N.C. 67 DQ23 109 N.C. 151 DQ55 26 27 VDD WE 68 69 VSS DQ24 110 111 VDD CAS 152 153 VSS DQ56 28 DQMB0 70 DQ25 112 DQMB4 154 DQ57 29 DQMB1 71 DQ26 113 DQMB5 155 DQ58 30 31 CS0 DU 72 73 DQ27 VDD 114 115 CS1 RAS 156 157 DQ59 VDD 32 VSS 74 DQ28 116 VSS 158 DQ60 33 A0 75 DQ29 117 A1 159 DQ61 34 35 A2 A4 76 77 DQ30 DQ31 118 119 A3 A5 160 161 DQ62 DQ63 36 A6 78 VSS 120 A7 162 VSS 37 A8 79 CLK2 121 A9 163 CLK3 38 39 A10 (AP) BA1 80 81 N.C. WP 122 123 BA0 A11 164 165 N.C. SA0 40 VDD 82 SDA 124 VDD 166 SA1 41 VDD 83 SCL 125 CLK1 167 SA2 42 CLK0 84 VDD 126 A12 168 VDD INFINEON Technologies 4 1.02 HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules RCS0 RDQMB0 DQ0-DQ7 CS DQM DQ0-DQ7 D0 RDQMB4 DQ32-DQ39 CS DQM DQ0-DQ7 D4 RDQMB1 DQ8-DQ15 CS DQM DQ0-DQ7 D1 RDQMB5 DQ40-DQ47 CS DQM DQ0-DQ7 D5 CS WE DQM DQ0-DQ7 D8 RCB0-RCB7 RCS2 RDQMB2 DQ16-DQ23 CS DQM DQ0-DQ7 D2 RDQMB4 DQ48-DQ55 CS DQM DQ0-DQ7 D6 RDQMB3 DQ24-DQ31 CS DQM DQ0-DQ7 D3 RDQMB7 DQ56-DQ63 CS DQM DQ0-DQ7 D7 VC C E 2 PROM (256 word x 8 Bit) SA0 SA0 SA1 SA1 SDA SA2 SA2 WP SCL SCL D0-D8, Reg., DLL C VS S D0-D8, Reg., DLL CLK0 PLL 47 k Ω SDRAMs D0-D8 12 pF Notes: DQ wirding may differ from that decribed in this drawing; however DQ/DQB relationship must be maintained as shown 2) All resistors are 10 Ω unless otherwise noted * ) A12 is only for 32 M x 72 & 64Mx72 organisation Register 1) CS0/CS2 DQMB0-7 BA0, BA1 A0-A11,12* ) RAS CAS CKE0 WE RCS0/RCS2 RDQMB0-7 RBA0, RBA1 RA0-11,12 RRAS RCAS RCKE0 RWE SDRAMs SDRAMs SDRAMs SDRAMs SDRAMs SDRAMs D0-D8 D0-D8 D0-D8 D0-D8 D0-D8 D0-D8 CLK1, CLK2, CLK3 REGE 10 kΩ VC C 12 pF reg_1U_1 Block Diagram: One Bank 16M x72, 32M x 72 and 64M × 72 Modules HYS72V16600, HYS72V32600 & HYS72V64601GR using x8 organized SDRAMs (RawCard F) INFINEON Technologies 5 1.02 HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules RCS0 RDQMB0 RDQMB4 DQ0-DQ3 DQM CS DQ0-DQ3 D0 DQ32-DQ35 DQM CS DQ0-DQ3 D8 DQ4-DQ7 DQM CS DQ0-DQ3 D1 DQ36-DQ39 DQM CS DQ0-DQ3 D9 RDQMB1 RDQMB5 DQM DQ0-DQ3 DQ40-DQ43 DQM CS DQ0-DQ3 D10 DQ12-DQ15 CS DQM DQ0-DQ3 D3 DQ44-DQ47 CS DQM DQ0-DQ3 D11 CB0-CB3 DQM CS DQ0-DQ3 D16 CB4-CB7 DQM CS DQ0-DQ3 D17 DQ8-DQ11 D2 RCS2 RDQMB2 RDQMB6 DQ16-DQ19 DQM CS DQ0-DQ3 D4 DQ48-DQ51 DQM CS DQ0-DQ3 D12 DQ20-DQ23 CS DQM DQ0-DQ3 D5 DQ52-DQ55 CS DQM DQ0-DQ3 D13 RDQMB3 RDQMB7 DQ24-DQ27 CS DQM DQ0-DQ3 D6 DQ56-DQ59 CS DQM DQ0-DQ3 D14 DQ28-DQ31 CS DQM DQ0-DQ3 D7 DQ60-DQ63 CS DQM DQ0-DQ3 D15 CLK0 PLL CS0/CS2 DQMB0-7 BA0, BA1 A0-A11, A12 RAS CAS CKE0 WE Register 12 pF SDRAMs D0-D17 CLK1, CLK2, CLK3 RCS0/RCS2 RDQMB0-7 RBA0, RBA1 RA0-RA11, RA12 RRAS RCAS RCKE0 RWE 12 pF SDRAMs D0-D17 SDRAMs D0-D17 SDRAMs D0-D17 SDRAMs D0-D17 SDRAMs D0-D17 SDRAMs D0-D17 REGE 10 k Ω SA0 SA1 SA2 SCL E 2PROM (256 word x 8 Bit) SA0 SA1 SDA WP SA2 SCL V CC 47 k Ω D0-D17, Reg., DLL C V SS D0-D17, Reg., DLL 1) DQ wirding may differ from that decribed in this drawing; however DQ/DQB relationship must be maintained as shown 2) All resistors are 10 Ω unless otherwise noted V CC SPB04135 Block Diagram: One Bank 32M x 72 and 64M x 72 Modules HYS72V32501GR and HYS72V64500GR with x4 components (RawCard G) INFINEON Technologies 6 1.02 HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules RCS0 RCS1 RDQMB0 RDQMB4 DQ0-DQ3 CS DQM DQ0-DQ3 D0 CS DQM DQ0-DQ3 D0 DQ32-DQ35 DQM CS DQ0-DQ3 D8 CS DQM DQ0-DQ3 D8 DQ4-DQ7 DQM CS DQ0-DQ3 D1 DQM CS DQ0-DQ3 D1 DQ36-DQ39 DQM CS DQ0-DQ3 D9 DQM CS DQ0-DQ3 D9 DQ8-DQ11 DQM CS DQ0-DQ3 D2 DQM CS DQ0-DQ3 D2 DQ40-DQ43 DQM CS DQ0-DQ3 D10 DQM CS DQ0-DQ3 D10 DQ12-DQ15 CS DQM DQ0-DQ3 D3 CS DQM DQ0-DQ3 D3 DQ44-DQ47 DQM CS DQ0-DQ3 D11 CS DQM DQ0-DQ3 D11 CB0-CB3 CS DQM DQ0-DQ3 D16 CS DQM DQ0-DQ3 D16 CB4-CB7 DQM CS DQ0-DQ3 D17 DQM CS DQ0-DQ3 D17 DQ16-DQ19 DQM CS DQ0-DQ3 D4 DQM CS DQ0-DQ3 D4 DQ48-DQ51 DQM CS DQ0-DQ3 D12 DQM CS DQ0-DQ3 D12 DQ20-DQ23 DQM CS DQ0-DQ3 D5 DQM CS DQ0-DQ3 D5 DQ52-DQ55 DQM CS DQ0-DQ3 D13 CS DQM DQ0-DQ3 D13 DQ24-DQ27 DQM CS DQ0-DQ3 D6 DQM CS DQ0-DQ3 D6 DQ56-DQ59 DQM CS DQ0-DQ3 D14 CS DQM DQ0-DQ3 D14 DQ28-DQ31 DQM CS DQ0-DQ3 D7 DQM CS DQ0-DQ3 D7 DQ61-DQ63 DQM CS DQ0-DQ3 D15 DQM CS DQ0-DQ3 D15 RDQMB1 RDQMB5 RCS2 RCS3 RDQMB2 RDQMB6 RDQMB3 CLK0 RDQMB7 PLL Stacked SDRAMs D0-D17 CLK1, CLK2, CLK3 CS0-CS3 DQMB0-7 BA0, BA1 A0-A11, A12* ) RAS CAS CKE0 WE REGE 10 k Ω V CC Register 12 pF RCS0-RCS3 RDQMB0-7 RBA0, RBA1 RA0-RA11 RRAS RCAS RCKE0 RWE *) 12 pF Stacked SDRAMs D0-D17 Stacked SDRAMs D0-D17 Stacked SDRAMs D0-D17 Stacked SDRAMs D0-D17 Stacked SDRAMs D0-D17 Stacked SDRAMs D0-D17 E 2PROM (256 word x 8 Bit) SA0 SA0 SA1 SA1 SDA SA2 SA2 WP SCL SCL V CC 47 k Ω D0-D17, Reg. DLL C V SS D0-D17, Reg. DLL 1.) DQ wirding may differ from that decribed in this drawing; however DQ/DQB relationship must be maintained as shown 2.) All resistors are 10 Ω unless otherwise noted A12 is only used for 128 M x 72 organisation SPB04136 Block Diagram: Two Bank 128M x 72 Modules HYS72V128520GR with x4 components (RawCard G) INFINEON Technologies 7 1.02 HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules Absolute Maximum Ratings Parameter Symbol Limit Values Unit min. max. Input / Output voltage relative to VSS VIN, VOUT – 1.0 4.6 V Power supply voltage on V DD VDD – 1.0 4.6 V Storage temperature range TSTG -55 +150 o Power dissipation (per SDRAM component) PD – 1 W Data out current (short circuit) IOS – 50 mA C Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to recommended operation conditions. Exposure to higher than recommended voltage for extended periods of time affect device reliability DC Characteristics TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V Parameter Symbol Limit Values min. Unit max. Input High Voltage VIH 2.0 VDD + 0.3 V Input Low Voltage VIL – 0.5 0.8 V Output High Voltage (I OUT = – 4.0 mA) VOH 2.4 – V Output Low Voltage (IOUT = 4.0 mA) VOL – 0.4 V Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) II(L) – 10 10 µA Output Leakage Current IO(L) – 10 10 µA (DQ is disabled, 0 V < VOUT < VDD) Capacitance TA = 0 to 70 °C 1); VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values Unit One Bank Two Bank Modules Modules Input Capacitance (all inputs except CLK and CKE) CIN 10 20 pF Input Capacitance (CLK) CCLK 30 30 pF Input Capacitance (CKE) CCKE 17 30 pF Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7) CIO 10 17 pF Input Capacitance (SCL, SA0 - 2) CSC 8 8 pF Input/Output Capacitance (SDA) CSD 8 8 pF INFINEON Technologies 8 1.02 HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules Operating Currents per SDRAM Component TA = 0 to 70 °C 1), VDD = 3.3 V ± 0.3 V (Recommended Operating Conditions unless otherwise noted) Parameter Test Condition Symbol 128Mb 256Mb 512 Mb Unit Note max. Operating current 2) – tRC = tRC(MIN.), tCK = tCK(MIN.) ICC1 160 230 270 mA tCK = min. ICC2P 1.5 2 4 mA 2) tCK = min. ICC2N 40 40 36 mA 2) CKE ≥ V IH(MIN.) ICC3N 50 50 35 mA 2) CKE ≤ V IL(MAX.) ICC3P 10 10 11 mA 2) – ICC4 100 150 255 mA Outputs open, Burst Length = 4, CL = 3. All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access Precharge stand-by current in Power Down Mode CS = V IH(MIN.), CKE ≤ VIL(MAX.) Precharge Stand-by Current in Non-Power Down Mode CS = V IH (MIN.), CKE ≥ V IH(MIN.) No operating current tCK = min., CS = VIH(MIN.), active state (max. 4 banks) Burst operating current tCK = min., Read command cycling 2), 3) – Auto refresh current tCK = min., Auto Refresh command cycling ICC5 230 240 440 mA 2) Self refresh current – Self Refresh Mode,CKE = 0.2 V ICC6 1.5 3 4 mA 2) INFINEON Technologies 9 1.02 HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules AC Characteristics (SDRAM Device Specification) 4), 5) TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol Limit Values Unit Note -7.5 min. max. Clock and Access Time tCK Clock Cycle Time CAS Latency = 3 CAS Latency = 2 – 7.5 10 – – ns ns – – 133 100 MHz MHz – – 5.4 6 ns ns – ns – fCK Clock Frequency CAS Latency = 3 CAS Latency = 2 – tAC Access Time from Clock CAS Latency = 3 CAS Latency = 2 – Clock High Pulse Width tCH 2.5 Clock Low Pulse Width tCL 2.5 – ns – Transition Time tT 0.5 10 ns – Input Setup Time tIS 1.5 – ns – Input Hold Time tIH 0.8 – ns – Power Down Mode Entry Time tSB – 1 CLK – Power Down Mode Exit Setup Time tPDE 1 – CLK – Mode Register Setup Time tRCS 2 – CLK – Row to Column Delay Time tRCD 20 – ns – Row Precharge Time tRP 20 – ns – Row Active Time tRAS 45 100k ns – Row Cycle Time tRC 67.5 – ns – Setup and Hold Parameters Common Parameters Activate (a) to Activate (b) Command Period tRRD 2 – CLK – CAS(a) to CAS(b) Command Period tCCD 1 – CLK – INFINEON Technologies 10 1.02 HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules AC Characteristics (SDRAM Device Specification) (cont’d) 4), 5) TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol Limit Values Unit Note -7.5 min. max. Refresh Cycle tREF Refresh Period 128MBit SDRAM Based Modules 256 & 512MBit SDRAM Based Modules – µs µs – – 15.6 7.8 tSREX 1 – CLK 6) Data Out Hold Time tOH 3 – ns – Data Out to Low Impedance Time tLZ 0 – ns 7) Data Out to High Impedance Time tHZ 3 7 ns 7) DQM Data Out Disable Latency tDQZ – 2 CLK – Data Input to Precharge (write recovery) tWR 2 – CLK – DQM Write Mask Latency tDQW 0 – CLK – INFINEON Technologies 11 Self Refresh Exit Time Read Cycle Write Cycle 1.02 HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules Notes 1. The registered DIMM modules are designed to operate under system operating conditions between 0-55 deg C ambient, maximum sustained bandwidth and 0 LFM airflow. Operating at higher ambient temperatures needs sufficient air flow to limit the case temperature of the SDRAM components do not exceed 85oC. 2. These parameters depend on the cycle rate. All values are measured at 133 MHz operation frequency. Input signals are changed once during tck excepts for Icc6 and for standby currents when tck = infinity. 3. These parameters are measured with continous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and the data-out current is excluded. 4. An initial pause of 100 µ s is required after power-up. Then a Precharge All Banks command must be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. Also the on-DIMM PLL must be given enough clock cycles to stabilize (tSTAB ) before any operation can be guaranteed. 5. AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between V IH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate between 0.8 V and 2.0 V. 6. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied after the Self Refresh Exit command is registered. 7. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. t CH 2.4 V 0.4 V CLOCK t CL t SETUP tT t HOLD 1.4 V INPUT t AC t LZ t AC I/O t OH 50 pF OUTPUT 1.4 V Measurement conditions for tAC and tOH t HZ SPT03404 Serial Presence Detect A serial presence detect storage device - E 2PROM 34C02 - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire bus). INFINEON Technologies 12 1.02 HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules SPD-Table for -7.5 Registered DIMM Modules 2 Memory Type SDRAM 3 4 5 Number of Row Addresses ) Number of Column Addresses Number of DIMM Banks 12/13 10/11/12 1,2 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Module Data Width Module Data Width (cont’d) Module Interface Levels Cycle Time at CL = 3 Access Time from Clock at CL = 3 DIMM Config (Error Det/Corr.) Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Width Minimum tCCD Burst Length Supported Number of SDRAM Banks SDRAM Supported CAS Latencies SDRAM CS Latencies SDRAM WE Latencies SDRAM DIMM Module Attributes 22 SDRAM Device Attributes 23 24 Min. Clock Cycle Time at CL = 2 Max. Access Time from Clock for CL = 2 Min. Clock Cycle Time at CL = 1 72 0 LVTTL 7.5 ns 5.4 ns ECC 15.6/7.8 µs x4, x8 x4, x8 1 CLK 1, 2, 4, 8 4 2&3 0 0 Registered with PLL VDD tol +/– 10% 10 ns 6.0 25 26 27 28 29 30 31 Max. Access Time from Clock at CL = 1 SDRAM Minimum tRP SDRAM Minimum tRRD SDRAM Minimum tRCD SDRAM Minimum tRAS Module Bank Density (per bank) 32 33 34 SDRAM Input Setup Time SDRAM Input Hold Time SDRAM Data Input Setup Time INFINEON Technologies 0D 0A 02 0D 0C 0D 0B 01 02 82 08 08 82 08 08 82 04 04 512 MB 2 Banks 512 MB 1 Bank*) 256 MB 1 Bank2) 128 256 1 GB 2 Banks Number of SPD Bytes Total Bytes in Serial PD 512 MB 1 Bank**) 0 1 Hex 256 MB 1 Bank1) SPD Entry Value 128 MB 1 Bank Byte# Description 80 08 0C 0A 01 80 08 08 0C 0B 01 80 04 04 0D 0A 01 82 08 08 13 48 00 01 75 54 02 82 04 04 01 0F 04 06 01 01 1F 0E A0 60 not supported not supp. 20 ns 15 ns 20 ns 45 ns 128 M/ 256M/ 512 MB 1.5 ns 0.8 ns 1.5 ns 04 0D 0B 01 00 00 20 40 40 14 0F 14 2D 80 40 80 80 15 08 15 1.02 HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules SPD-Table for -7.5 Registered DIMM Modules (cont’d) 0.8 ns – JEDEC 2 – 512 MB 2 Banks 512 MB 1 Bank*) 256 MB 1 Bank2) 256 MB 1 Bank1) 1 GB 2 Banks 62 63 64 65-71 72 73-90 91-92 93-94 95-98 99-125 126 SDRAM Data Input Hold Time Superset Information(may be used in future) SPD Revision Checksum for Bytes 0 - 62 Manufacturers JEDEC ID Code Manufacturer Module Assembly Location Module Part Number Module Revision Code Module Manufacturing Date Module Serial Number Hex 512 MB 1 Bank**) 35 36-61 SPD Entry Value 128 MB 1 Bank Byte# Description BD BD 08 00 60 79 12 BC 84 C1 INFINEO(N) 83 Frequency Specification – 64 127 Details of Clocks – 8F 128255 Open for Customer Use – Note: 1) HYS72V32501GR-7.5 (128Mbit x4 based), 2) HYS72V32600GR-7.5 (256Mbit x8 based) *) HYS72V64500GR-7.5 (256Mbit based) **) HYS72V64601GR-7.5 (512Mbit based) INFINEON Technologies 14 1.02 HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules Package Outlines Raw Card F Module Package JEDEC MO-161 Registered DIMM Modules (Raw Card F) L-DIM168-51 128MB, 256MB & 512MB modules based on x8 SDRAM components 133.35 ± 0.15 30,4 max. 1,2" max. 127.35 Register PLL Register 3 1 10 11 6.35 3 1.27 40 41 6.35 84 42.18 66.68 3.125 2 94 95 124 125 168 4 ±0.1 17.78 85 non-stacked: stacked: 4 max. 6.8 max. 2.55 0.2 Detail of Contacts +0.5 1 1.27 ± 0.1 1.27± 0.1 1.27 note: all outline dimensions and tolerances are in accordance with the JEDEC standard INFINEON Technologies 15 1.02 HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules Package Outlines Raw Card G Module Package JEDEC MO-161 Registered DIMM Modules (Raw Card G) L-DIM168-52 133.35 ± 0.15 30,4 max. 1,2" max. 127.35 Register Register 3 1 10 11 6.35 3 1.27 40 41 6.35 84 42.18 2 85 94 95 124 17.78 3.125 66.68 125 168 Register 4 ± 0.1 PLL non-stacked: stacked: 4 max. 6.8 max. 2.55 0.2 Detail of Contacts +0.5 1 1.27 ± 0.1 1.27± 0.1 1.27 L-DIM-168-52 note: all outline dimensions and tolerances are in accordance with the JEDEC standard INFINEON Technologies 16 1.02 HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules Functional Description All these PC133 168-pin Registered DIMMs conform to a compatible set of timing and operation characteristics intended to comply with the 133 MHz standards. The Registered DIMMs achieve high speed data transfer rate up to 133 MHz, when in “registered mode”. The “registered mode” is achieved when the REGE input signal is in “high” state or the pin is not connected. Operation in “buffered mode” (REGE = “low”) needs careful system design to compensate all input signals for the extra delay time of the register components when in “buffered mode”. “Buffered mode” is limited to 66 Mhz operation and is beyond the scope of this datasheet. Registered Mode: All control and address signals are synchronized with the positive edge of externally supplied clocks and are registered on-DIMM and hence delayed by one clock cycle in arriving at the SDRAM devices. The use of the on-board register reduces the capacitive loading of the DIMM on input control and address signals. The SDRAM device data lines (DQ) are connected directly to the DIMM tabs through 10 Ohm series resistors. All the following timing diagrams and explanations show DIMM operation at the tabs, not SDRAM operation. The picture below depicts an overview of the effect of the Registered Mode on the data outputs (DQs) for a Read operation. Without the registers, the data is delayed according to the device CAS latency, in the case two clocks. With the register, the data is delayed according to the device CAS latency plus an additional clock cycle. This is known as the DIMM CAS latency, and in this example is four three. The data path can be thought of as a pipeline in which the register effectively lengthens the pipe by one clock cycle. Registered DIMM Burst Read Operation (BL = 4) T0 T1 T2 T3 T4 T5 T6 Read A NOP NOP NOP NOP NOP NOP CLK Command Device CAS latency = 2 t CK2 , DQ’s DIMM CAS latency = 3 t CK3 , DQ’s DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 Added for on-DIMM pipeline register One Clock Reg-DIMM Latency = 1 SPT03968 In case of a Burst Write Command the data-in is delayed one clock due the op-DIMM pipeline register also. Therefore, data for the first Burst Write cycle must be applied on the DQ pins on the next clock cycle after the Write command is issued. the remaining data inputs must be supplied on INFINEON Technologies 17 1.02 HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules each subsequent rising clock edge until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP Write A NOP NOP NOP NOP NOP NOP NOP DIN A0 DIN A1 DIN A2 DIN A3 don’t care CLK Command DQ’s The first data element and the Write are registered on the next clock edge Reg-DIMM Latency = 1 CLK Extra data is ignored after termination of a Burst. SPT03969 Registered DIMM Burst Write Operation (BL = 4) INFINEON Technologies 18 1.02 HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules INFINEON Technologies 19 1.02 HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules Change List 12.00 18.1.2001 23.1.2001 Rev. 0.1 Rev. 0.1 Rev. 0.1 12.02.2001 19.02.2001 27.02.2001 04.04.2001 11.04.2001 Rev.0.2 Rev. 0.3 Rev. 0.4 Rev. 0.5 Rev. 0.5b 29.05.2001 21.06.2001 28.06.2001 Rev. 0.6 Rev. 0.7 Rev. 0.8 06.09.2001 17.12.2001 Rev. 0.9 Final 1.0 INFINEON Technologies First revision Clarification of “buffered mode”operation (not tested) Height reduced from 1.2” (nominal) to 1.155” (max) according to the lastest IBM drawings for RawCard F PM decided to stay with 1.2” inch height New PCB L-DIM-168-56 with 1.125” height Both Gerber Files (1,125” and 1.2”) are now in the target datasheet x4 based modules on L-DIM-168-52 added Info from Mr. Pammer AIT Rgb: L-DIM-168-51 is based on Raw Card A and L-DIM-168-52 is based on Raw Card B Block Diagram for stacked x8 module changed for use of x8 stacks with one CKE and two CS HYS72V32501GR-7.5 (128Mbit x4 based 256MByte) added Outline Drawings changed to L-DIM-168-51,52 & 56 Product Marketing Decision : Remove all 1,125” inch modules Datasheet changed from “target” to “preliminary” RawCards and therefore the Compliance Code changed according to JEDEC naming conventions, RawCard F for x8 and RawCard G for x4 (nonstackd and stacked) SCR: Thickness of modules changed from 4 to 4 max and 6.4 to 6.8 max SCR-028-2001-11-12 PC133 / TPCR_08 / JC42.5 Item 1138.5 : JEDEC changed Byte 62h (SPD Revision) from 02h to 12h Checksum changed therefore also 20 1.02