ESMT M24D816512DA Revision History : Revision 1.0 (Jul. 5, 2007) - Original Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 1/13 ESMT PSRAM M24D816512DA 8-Mbit (512K x 16) Pseudo Static RAM Features placed in a high-impedance state when: deselected ( CE1 • Wide voltage range: 1.7V–1.95V • Access Time: 55 ns, 70 ns • Ultra-low active power — Typical active current: 3 mA @ f = 1 MHz — Typical active current: 20 mA @ f = fmax • Ultra low standby power • Automatic power-down when deselected • CMOS for optimum speed/power • Offered in a 48-ball BGA Package • Operating Temperature: –40°C to +85°C HIGH or CE2 LOW), outputs are disabled ( OE HIGH), both Byte High Enable and Byte Low Enable are disabled Functional Description[1] The M24D816512DA is a high-performance CMOS Pseudo Static RAM organized as 512K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for portable applications such as cellular telephones. The device can be put into standby mode when deselected ( CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are ( BHE , BLE HIGH), or during a write operation ( CE1 LOW and CE2 HIGH and WE LOW). Writing to the device is accomplished by taking Chip Enable( CE1 LOW and CE2 HIGH) and Write Enable ( WE ) input LOW. If Byte Low Enable ( BLE ) is LOW, then data from I/O pins (I/O0through I/O7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable ( BHE ) is LOW, then data from I/O pins (I/O8 through I/O15) is written in to the location specified on the address pins (A0 through A18).Reading from the device is accomplished by taking Chip Enables ( CE1 LOW and CE2 HIGH) and Output Enable ( OE )LOW while forcing the Write Enable ( WE ) HIGH. If Byte Low Enable ( BLE ) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable ( BHE ) is LOW, then data from memory will appear on I/O8 to I/O15. Refer to the truth table for a complete description of read and write modes.. Logic Block Diagram Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 2/13 ESMT M24D816512DA Pin Configuration[2, 3] 48-Ball VFBGA Top View Product Portfolio [4] Power Dissipation VCC Range (V) Product M24D816512DA Speed(ns) Min. Typ.[4] Max. 1.7 1.8 1.95 55 70 Operating ICC(Ma) f = 1MHz .Typ.[4] Max. 3 5 Standby ISB2(µA) f = fmax .Typ.[4] Max. 20 35 18 25 .Typ. [4] Max. 32 70 Note: 2.Ball G2, H6 and E3 can be used to upgrade to a 16-Mbit, 32-Mbit and a 64-Mbit density, respectively. 3.NC “no connect” - not connected internally to the die. 4.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ) and TA = 25°C. Tested initially and after design changes that may affect the parameters. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 3/13 ESMT M24D816512DA Power-up Characteristics The initialization sequence is shown in Figure1. Chip Select should be CE1 HIGH or CE2 LOW for at least 200 µs after VCC has reached a stable value. No access must be attempted during this period of 200 µs. Parameter Description Min. Tpu CE1 LOW and CE2 HIGH After Stable VCC 200 Elite Semiconductor Memory Technology Inc. Typ. Max. Unit µs Publication Date : Jul. 2007 Revision : 1.0 4/13 ESMT M24D816512DA Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ...................................–65°C to +150°C Ambient Temperature with Power Applied ..............................................–55°C to +125°C Supply Voltage to Ground Potential . ............................−0.2V to VCCMAX + 0.3V DC Voltage Applied to Outputs in High-Z State[5, 6, 7] ...................... −0.2V to VCCMAX + 0.3V DC Input Voltage[5, 6, 7].................... −0.2V to VCCMAX + 0.3V Output Current into Outputs (LOW) ...............................20 mA Static Discharge Voltage ........................................ >2001V (per MIL-STD-883, Method 3015) Latch-up Current ....................................................> 200 mA Operating Range Range Ambient Temperature (TA) VCC Industrial −40°C to +85°C 1.7V to 1.95V DC Electrical Characteristics (Over the Operating Range)[5,6,7] -55 Parameter Description Test Conditions Min. VCC VOH VOL VIH VIL IIX IOZ Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage 2.7 VCC0.2 IOH = −0.1 mA VCC = 1.7V to 1.95V IOL = 0.1 mA VCC = 1.7V to 1.95V 1.95 1.7 VCC0.2 Typ. [4] 1.8 1.95 V V 0.2 V +1 -1 +1 µA -1 +1 -1 +1 µA -0.2 Input Leakage Current Output Leakage Current GND ≤ VIN ≤ VCC GND ≤ VOUT ≤ VCC VCC = VCCMAX IOUT = 0mA CMOS levels Unit Max. -1 VCC = 1.7V to 1.95V ISB2 Min. 0.8* VCC Input LOW Voltage Automatic CE Power-Down Current —CMOS Inputs Max. VCC+ 0.3V 0.2* VCC 0.8* VCC ICC Typ .[4] 1.8 0.2 VCC = 1.7V to 1.95V VCC Operating Supply Current -70 VCC +0.3V 0.2* VCC -0.2 V V 20 35 18 25 mA f = 1 MHz 3 5 3 5 mA CE1 ≥ VCC−0.2V or CE2 ≤ 0.2V VIN ≥ VCC − 0.2V or VIN ≤ 0.2V, f = 0, VCC = VCCMAX 32 40 32 40 µA f = fMAX = 1/tRC Capacitance[8] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions Max. Unit 8 8 pF pF TA = 25°C, f = 1 MHz VCC = VCC(typ) Thermal Resistance[8] Parameter Description Test Conditions BGA Unit ΘJA Thermal Resistance(Junction to Ambient) 56 °C/W ΘJC Thermal Resistance (Junction to Case) Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/ JESD51. 11 °C/W Notes: 5.VIL(MIN) = –0.5V for pulse durations less than 20 ns. 6.VIH(Max) = VCC + 0.5V for pulse durations less than 20 ns. 7.Overshoot and undershoot specifications are characterized and are not 100% tested. 8.Tested initially and after any design or process changes that may affect these parameters. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 5/13 ESMT M24D816512DA AC Test Loads and Waveforms Parameters R1 R2 RTH VTH 1.8V (VCC) 14000 14000 7000 0.90 Unit Ω Ω Ω V Switching Characteristics Over the Operating Range [9, 10, 11, 12] Parameter Read Cycle tRC[14] tCD [15] tAA tOHA tACE Description Read Cycle Time Chip Deselect Time CE1 = HIGH orCE2 = LOW, BLE / BHE High Pulse Time Address to Data Valid Data Hold from Address Change -55 -70 Unit Min. Max. Min. Max. 55 80000 70 80000 ns ns 70 5 5 55 CE1 LOW and CE2 HIGH to Data Valid 55 70 ns ns ns tDOE OE LOW to Data Valid 25 35 ns tLZOE OE LOW to Low Z[10, 11, 13] tHZOE OE HIGH to High Z[10, 11, 13] tLZCE CE1 LOW and CE2 HIGH to Low Z[10, 11, 13] tHZCE CE1 HIGH or CE2 LOW to High Z[10, 11, 13] 20 25 ns tDBE BLE / BHE LOW to Data Valid 55 70 ns tLZBE BLE / BHE LOW to Low Z[10, 11, 13] tHZBE BLE / BHE HIGH to Low Z[10, 11, 13] 5 5 5 ns 5 20 10 25 ns 10 5 ns 5 20 ns 25 ns Notes: 9.Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ.)/2, input pulse levels of 0V to VCC, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 10.At any given temperature and voltage conditions tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. All low-Z parameters will be measured with a load capacitance of 30 pF (3V) 11.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 12.The internal Write time of the memory is defined by the overlap of WE , CE1 = VIL and CE2 = VIH, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 13.High-Z and Low-Z parameters are characterized and are not 100% tested. 14.If invalid address signals shorter than min. tRC are continuously repeated for 80 µs, the device needs a normal read timing (tRC) or needs to enter standby state at least once in every 80 µs. 15.Whenever CE1 = HIGH or CE2 = LOW, BHE / BLE are taken inactive, they must remain inactive for a minimum of 5 ns. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 6/13 ESMT M24D816512DA Switching Characteristics Over the Operating Range[9, 10, 11, 12] (continued) Parameter Write Cycle [12] tWC tSCE tAW -55 Description -70 Unit Min. Max. Min. Max. Write Cycle Time 50 80000 70 80000 CE1 LOW and CE2 HIGH to Write End Address Set-Up to Write End 50 60 ns 50 60 ns 5 5 ns 0 0 50 ns ns ns ns Chip Deselect Time CE1 = HIGH or tCD[15] tHA tSA tPWE CE2 = LOW, BLE / BHE Pulse Time Address Hold from Write End Address Set-Up to Write Start High WE Pulse Width 0 0 45 tBW BLE / BHE LOW to Write End 50 60 ns tSD Data Set-Up to Write End 25 25 ns tHD Data Hold from Write End 0 0 ns tHZWE WE LOW to High-Z[10, 11, 13] tLZWE WE HIGH to Low-Z[10, 11, 13] Elite Semiconductor Memory Technology Inc. 20 10 25 10 ns ns Publication Date : Jul. 2007 Revision : 1.0 7/13 ESMT M24D816512DA Switching Waveforms Read Cycle 1 (Address Transition Controlled)[16, 17] Read Cycle 2 ( OE Controlled)[15, 17] Notes: 15. Device is continuously selected. OE , CE1 = VIL and CE2 = VIH. 16. WE is HIGH for Read Cycle. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 8/13 ESMT M24D816512DA Switching Waveforms (continued) Write Cycle 1 ( WE Controlled)[12, 13, 15, 18, 19] Notes: 18.Data I/O is high impedance if OE ≥ VIH. 19.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 9/13 ESMT M24D816512DA Switching Waveforms (continued) Write Cycle 2 ( CE1 or CE2 Controlled) [12, 13, 15, 18, 19] Write Cycle 3 ( WE Controlled, OE LOW)[15, 19] Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 10/13 ESMT M24D816512DA Switching Waveforms (continued) Write Cycle 4 ( BHE / BLE Controlled, OE LOW) [12, 15, 18, 19] Truth Table[20] CE1 H X X CE2 X L X WE X X X OE X X X BHE X X H L H H L L L L H H L H L L H H L L H L H H H L L L H H H H L H H H L H L L H L H Inputs/Outputs High Z High Z High Z Mode Deselect/Power-Down Deselect/Power-Down Deselect/Power-Down Power Standby (ISB) Standby (ISB) Standby (ISB) Data Out (I/O0–I/O15) Read Active (ICC) Read Active (ICC) Read Active (ICC) High Z Output Disabled Active (ICC) L High Z Output Disabled Active (ICC) L H High Z Output Disabled Active (ICC) X L L Data In (I/O0–I/O15) Write (Upper Byte and Lower Byte) Active (ICC) L X H L Write (Lower Byte Only) Active (ICC) L X L H Write (Upper Byte Only) Active (ICC) BLE X X H Data Out (I/O0–I/O7); (I/O8–I/O15) in High Z Data Out (I/O8–I/O15); (I/O0–I/O7) in High Z Data In (I/O0–I/O7); (I/O8–I/O15) in High Z Data Out (I/O8–I/O15); (I/O0–I/O7) in High Z Note: 20.H = Logic HIGH, L = Logic LOW, X = Don’t Care. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 11/13 ESMT M24D816512DA Ordering Information Speed (ns) 55 70 Ordering Code M24D816128DA-55BIG M24D816128DA-70BIG Package Type 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) Operating Range Industrial Industrial Package Diagrams 48-Lead VFBGA (6 x 8 x 1 mm) Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 12/13 ESMT M24D816512DA Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 13/13