May 1997 Micro Linear ML4821* Power Factor Controller GENERAL DESCRIPTION FEATURES The ML4821 provides complete control for a “boost” type power factor correction system using the average current sensing method. Special care has been taken in the design of the ML4821 to increase system noise immunity. The circuit includes a precision reference, gain modulator, average current error amplifier, output error amplifier, over-voltage protection comparator, shutdown logic, as well as a high current output. In addition, start-up is simplified by an under-voltage lockout circuit. ■ ■ ■ ■ ■ ■ In a typical application, the ML4821 controls the AC input current by adjusting the pulse width of the output MOSFET. This modulates the line current so that its shape conforms to the shape of the input voltage. The reference for the current regulator is a product of the sinusoidal line voltage times the output of the error amplifier which is regulating the output DC voltage. Average line voltage compensation is provided in the gain modulator to ensure constant loop gain over a wide input voltage range. This compensation includes a special “brown-out” control which reduces output power below 90V RMS input. ■ ■ ■ Average current sensing for lowest possible harmonic distortion Average line compensation with brown-out control Precision buffered 5V reference 1A peak current totem-pole output drive Overvoltage comparator eliminates output “runaway” due to load removal Wide common mode range in current sense comparators for better noise immunity Large oscillator amplitude for better noise immunity Output driver internally limited to 17V “Sleep mode” shutdown input * Some Packages Are Obsolete BLOCK DIAGRAM 11 1 OVP + VREF ILIM – + SLEEP – 0.7V – UNDER VOLTAGE LOCKOUT + 2 3 IA OUT IA– IA+ – R + S VLIMIT 6 7 OUT VRMS GAIN MODULATOR PGND RT OSC SYNC CT EA OUT 15 14 13 12 10 17 VREF EA– – VREF 9 18 17V OUT ISINE 16 Q 4 8 GND VCC – + 5 VREF + SOFT START Micro Linear 1 ML4821 PIN CONNECTION ML4821 20-Pin SOIC (S20) ML4821 18-Pin DIP (P18) ILIM 1 18 GND IA OUT 2 17 CT IA– 3 16 VREF IA+ 4 15 VCC ISINE 5 14 OUT EA OUT 6 13 PGND EA– 7 12 RT VRMS 8 11 OVP SOFT START 9 10 SYNC ILIM 1 20 IA OUT 2 19 CT IA– 3 18 VREF IA+ 4 17 VCC ISINE 5 16 OUT EA OUT 6 15 PGND EA– 7 14 RT VRMS 8 13 OVP SOFT START 9 12 SYNC N/C 10 11 N/C TOP VIEW GND TOP VIEW PIN DESCRIPTION (Pin numbers in parentheses are for 20-pin packages) PIN NAME FUNCTION 1 (1) ILIM Peak cycle-by-cycle current limit input 2 (2) IA OUT Output and compensation node of the average current error amplifier 3 (3) IA– Inverting input of the average current error amplifier 4 (4) IA+ Non-Inverting input of the average current error amplifier and output of the gain modulator 5 (5) 6 (6) ISINE Gain modulator input EA OUT Output of output voltage error amplifier 7 (7) INV Inverting input to error amplifier 8 (8) VRMS Input for average line voltage compensation SOFT START Normally connected to soft start capacitor 9 (9) 2 PIN NAME FUNCTION 10 (12) SYNC Oscillator synchronization input 11 (13) OVP Inhibits output pulses when the voltage at this pin exceeds 5V. Also, when the voltage at this pin is less than 0.7V, the IC goes into low current shut-down mode. 12 (14) RT Timing resistor for the oscillator 13 (15) PWR GND Return for the high current totem pole output 14 (16) OUT High current totem pole output 15 (17) VCC Positive supply for the IC 16 (18) VREF Buffered output for the 5V voltage reference 17 (19) CT Timing capacitor for the oscillator. 18 (20) GND Analog signal ground Micro Linear ML4821 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Supply Current (ICC) ................................................ 35mA OUT Current, Source or Sink .................................... 1.0A Output Energy (capacitive load per cycle) .................... 5µJ ISINE Input Current .................................................. 1.2mA EA OUT Source Current .......................................... 50mA Oscillator Charge Current ......................................... 2mA Input Voltage ...................................... GND –0.3V to 5.5V Junction Temperature .............................................. 150°C Storage Temperature Range ...................... –65°C to 150°C Lead Temperature (Soldering 10 sec.) ...................... 260°C Thermal Resistance (θJA) Plastic DIP ........................................................ 75°C/W Plastic SOIC ..................................................... 95°C/W OPERATING CONDITIONS Temperature Range ML4821CX ................................................. 0°C to 70°C ML4821IX .............................................. –40°C to 85°C ELECTRICAL CHARACTERISTICS Unless otherwise specified, RT = 6.2kΩ, CT = 720pF, T A = Operating Temperature Range, VCC = 15V (Notes 1 & 2). PARAMETER CONDITIONS MIN TYP. MAX UNITS 90 100 110 kHz OSCILLATOR Initial accuracy TA = 25°C Voltage stability 12V < VCC < 18V Temperature stability Total Variation Line, Temperature 1 % 2 % 85 115 kHz Ramp Valley to Peak 4.7 5.2 5.6 V RT Voltage 4.8 5.0 5.2 V 7.8 8.4 9.3 mA 1.5 2.0 3.0 V 4.95 5.00 5.05 V Discharge Current CT= 2V, RT = Open SYNC Input Threshold REFERENCE Output Voltage TA = 25°C, IO = 1mA Line regulation 12V < VCC < 24V 2 10 mV Load regulation 1mA < IO < 20mA 2 15 mV Temperature stability .4 4.9 % Total Variation line, load, temp Output Noise Voltage 10Hz to 10kHz 50 Long Term Stability TA = 125°C, 1000 hrs 5 25 mV Short Circuit Current VREF = 0V –85 –180 mA –15 mV –800 nA –30 5.1 V µV VOLTAGE ERROR AMPLIFIER Input Offset Voltage 0 Input Bias Current –50 Open Loop Gain 2 < EA OUT < 6V 60 75 dB PSRR 12V < VCC < 24V 70 100 dB Output Sink Current EA OUT = 4V, INV = 5.5V 300 500 µA Output Source Current EA OUT = 4.0V, INV = 4.8V –10 –30 mA Micro Linear 3 ML4821 ELECTRICAL CHARACTERISTICS (Continued) PARAMETER CONDITIONS MIN TYP 7.0 7.5 MAX UNITS VOLTAGE ERROR AMPLIFIER (Continued) Output High Voltage IPIN6 = –5mA, VPIN7 = 4.8V Output Low Voltage IPIN6 = 0, EA– = 5.5V 0 Unity Gain Bandwidth Soft Start Charge Current V 0.5 1.0 VPIN9 = 4V V MHz –22 –38 –50 µA –5 0 5 mV –0.15 –1 µA 400 nA CURRENT ERROR AMPLIFIER Input Offset Voltage Input Bias Current Input Offset Current Open Loop Gain 2 < EA OUT < 7V 80 100 dB PSRR 12V < VCC < 24V 65 85 dB Output Voltage Low IOL = 300µA Output Voltage High IOH = –10mA Input Common Mode Range 0 7.0 0.5 7.5 –0.3 V V 2.5 V GAIN MODULATOR Gain VINV = 4.8V, VRMS = 0V VINV = 4.8V, VRMS = 1.75V VINV = 4.8V, VRMS = 2.6V VINV = 4.8V, VRMS = 5.2V Output Current VINV = 5.2V, VRMS = 5.2V Output Current Limit VINV = 4.8V, ISINE = 500µA, VRMS = 1.75V 0.75 3.1 1.25 0.22 1.2 3.88 1.75 0.38 1.3 4.5 2.15 0.50 –2 –4 µA 395 420 µA +15 mV –200 µA 5 mV 105 130 mV Input Bias Current –0.3 –3 µA Propagation Delay 150 360 ILIM COMPARATOR Input Offset Voltage Input Bias Current –100 OVP COMPARATOR Input Offset Voltage Output Off –25 Hysteresis Output On 85 Shutdown Threshold 0.4 0.7 ns 1.0 V 8 V PWM COMPARATOR Input Common Mode Range 0 Propagation Delay 4 150 Micro Linear ns ML4821 ELECTRICAL CHARACTERISTICS (Continued) PARAMETER CONDITIONS MIN TYP. MAX UNITS 0.1 1.6 0.4 2.4 V V OUTPUT Output Voltage Low IOUT = 20mA IOUT = 200mA Output Voltage High IOUT = –20mA IOUT = –200mA Output Voltage Low in UVLO IOUT = –5mA, VCC = 8V 0.1 Output Rise/Fall Time CL = 1000pF 50 13 12 13.5 13.4 V V 0.8 V ns UNDERVOLTAGE LOCKOUT Start-up Threshold 14.5 16.5 V Shut-Down Threshold 8.5 11.0 V VREF Good Threshold 4.4 V SUPPLY Supply Current Start-up, VCC = 14V, TA = 25°C Operating, TA = 25°C Internal Shunt Zener Voltage ICC = 35mA 25 Note 1: Note 2: Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions. VCC is raised above the start-up threshold first to activate the IC, then returned to 15V Note 3: I Gain Modulator gain is defined as: OUTIA + 0.6 26 1.2 32 mA mA 27 35 V IINEA OUT Micro Linear 5 ML4821 FUNCTIONAL DESCRIPTION OSCILLATOR VOLTAGE AND CURRENT ERROR AMPLIFIERS The ML4821 oscillator charges the external capacitor connected to CT with a current equal to 2.5/RT. When the capacitor voltage reaches the upper threshold, the comparator changes state and the capacitor discharges to the lower threshold through Q1. The ML4821 voltage error amplifier is a high open loop gain, wide bandwidth amplifier with a class A output. The soft start circuit controls the input to this amplifier for closed loop soft start operation. The oscillator period can be described by the following relationship: TOSC = TRAMP + TDISCHARGE The current error amplifier (IA) is similar to the voltage error amplifier but is designed for very low offsets to allow the selection of a low value resistor for RSENSE. OUTPUT DRIVER STAGE where: The ML4821 Output Driver is a 1A peak output high speed totem pole circuit designed to quickly drive capacitive loads, such as power MOSFET gates. The driver circuit’s output voltage is internally limited to 17V. TRAMP = C(Ramp Valley to Peak) ÷ (IRT/2) and: TDISCHARGE = C(Ramp Valley to Pk) ÷ (8.4mA – IRT/2) CLOCK tD RAMP PEAK CT RAMP VALLEY The ML4821 oscillator includes a SYNC input for synchronizing to an external frequency source. A positive pulse on this pin of 2V (typ) resets the oscillators comparator and initiates a discharge cycle for CT. The RT and CT component values which set the ML4821 oscillator frequency should be selected to produce a lower frequency than the external frequency source. RT GAIN MODULATOR The ML4821 gain modulator responds linearly to current injected into the ISINE pin, and in an inverse-square fashion to voltage on the VRMS pin. At very low voltages on the VRMS pin, the gain modulator enforces a power limit, or ”brown-out protection”, upon the overall PFC circuit (Figures 6 and 7). The rectified line input sine wave is converted to a current for the ISINE input via a dropping resistor. In this way, most ground noise produces an insignificant effect on the reference to the PWM comparator. This gives the ML4821 a high degree of immunity to the disturbances common in high-power switching circuits. VREF 1000 IRT IRT 2 CT CT + – 8.4mA FREQUENCY (kHz) RT 150pF 100 330pF Q1 470pF 1nF 680pF SYNC Q2 2kΩ 1kΩ 10 0 10 20 30 40 50 RT (kΩ) Figure 1. Oscillator Block Diagram. 6 Figure 2. Oscillator Timing Resistance vs. Frequency. Micro Linear 7 +8V – EA OUT + +8V 6 VREF S.S 6.2kΩ 9 100 80 GAIN 60 60 40 90 PHASE 20 120 0 150 –20 10 Figure 3. Error and Current Amplifier Configuration 0 VCC = 15V VO = 1.0V TO 5.0V –30 RL = 100kΩ TA= 25°C 100 1.0k 10k 100k f, FREQUENCY (Hz) PHASE (DEGREES) INV AVOL, OPEN-LOOP VOLTAGE GAIN (dB) ML4821 180 10M 1.0M Figure 4. Error Amplifier Open-loop Gain and Phase vs. Frequency. 0.5 VSAT, OUTPUT SATURATION VOLTAGE (V) 0 SOURCE SATURATION (LOAD TO GROUND) VCC –1.0 TA = 25°C –2.0 OPERATING BOUNDRY VCC = 15V 80µs PULSED LOAD 120 Hz RATE DESIGN FOR NORMAL OPERATIONS 0.4 DESIGN FOR BROWNOUT TA = –55°C 0.3 THIS IS THE MINIMUM OPERATING VOLTAGE POINT K 0.23 0.2 3.0 THIS GAIN CURVE TAKES OUT THE 1/(VIN)2 DEPENDENCY OF THE VOLTAGE CONTROL LOOP TA = –55°C 2.0 TA = 25°C 1.0 GND 0 0.1 SINK SATURATION (LOAD TO VCC) 0 200 400 0 600 800 0 1 2 85VAC IO, OUTPUT LOAD CURRENT (mA) 3 4 5 6 7 220VAC 120VAC VRMS Figure 5. Output Saturation Voltage vs. Output Current. The output of the gain modulator is a current which appears on IA+ to form the reference for the current error amplifier and is given as: IGM = K × ISINE × (VEA − 0.8) where: ISINE is the current in the dropping resistor, VEA is the output of the error amplifier and K is a constant determined by the VRMS input. The output current of the gain modulator is limited to: IGM(MAX) = 2.5 RT This sets the system current limit.The multiplier output current is converted into the reference voltage for the current (IA) amplifier through a resistor to ground on IA+. Figure 6. K-factor. Gain Modulator gain with respect to the voltage at VRMS. Figure 6 shows the gain adjustor (K) with respect to the voltage at VRMS. The curve has been separated in two parts. The right hand part is for operation under normal conditions in the voltage range from minimum line voltage to maximum line voltage (90VAC to 260VAC). 85VAC on the curve has been chosen to account for tolerances. Under normal operating conditions as input voltage decreases the gain increases compensating for the drop in the loop gain. Under brownout conditions (below 85VAC) the gain decreases to limit the amount of current that is drawn from the line thus preventing an overload condition. This is a very useful feature since in many cases the load for a PFC is a constant power load. The input current has to go high to compensate for a drop in the input voltage. Micro Linear 7 ML4821 UNDER VOLTAGE LOCKOUT, OVP AND CURRENT LIMIT OVP, SHUTDOWN, AND IC BIAS On power-up the ML4821 remains in the UVLO condition; output low and quiescent current low. The IC becomes operational when VCC reaches 16V. When VCC drops below 9V, the UVLO condition is imposed. During the UVLO condition, the VREF pin is “off”, making it usable as a “flag” for starting up a down-stream PWM converter. 5.5 RT = 5kΩ VRMS = 3V 400 4.5 300 3.5 200 2.5 100 – E/A OUTPUT VOLTAGE MULTIPLIER OUTPUT CURRENT (µA) 500 When the input to the OVP comparator exceeds VREF, the output of the ML4821 is inhibited. The OVP input also functions as a “sleep” input, putting the IC into the low quiescent UVLO state when the OVP pin is pulled below 0.7V. + VREF 100 200 300 400 16 9V 500 VCC INTERNAL BIAS – 1.0 0 LOGIC POWER ENABLE VREF 1.5 0 4.4V 15 + SINE INPUT CURRENT (µA) Figure 7. Gain Modulator Linearity. ∆VREF, REFERENCE VOLTAGE CHANGE (mV) Figure 8. Under-Voltage Lockout Block Diagram. ICC SUPPLY CURRENT (mA) 40 30 20 TA = 25°C 10 0 0 10 20 30 0 VCC = 15V –4.0 –8.0 –12 TA = –55°C TA = 125°C –16 –20 –24 TA = 25°C 0 20 Figure 9. Total Supply Current vs. Supply Voltage. 8 40 60 80 100 IREF, REFERENCE SOURCE CURRENT (mA) VCC SUPPLY VOLTAGE (V) Figure 10. Reference Load Regulation. Micro Linear 120 ML4821 OFF-LINE START-UP AND BIAS SUPPLY GENERATION The circuit in Figure 11 supplies VCC power to the ML4821. Start-up current is delivered via R10. The IC starts when VCC reaches 15.5V. After that time running power is delivered through the tap on L1. The configuration shown delivers a voltage proportional to the PFC output bus voltage. R10 39kΩ 2W L1 TO B+ TO IC PIN 15 1µF 1000µF NP NS NP NS ≈ 1µF VOUT 14V Figure 11. Bias and Start-up Circuit. Micro Linear 9 ML4821 F1 5A, 250V D1 1N5406 D1 AC IN 90-264 VAC D2 L1 + C1 1µF D10 MUR850 D4 D3 C12 1µF D7 1N4934 C13 1µF R10 39kΩ C14 470µF C14 470µF C19 270µF 450V D8 1N4934 R7 560kΩ R8 910kΩ R5 2kΩ ML4821 1 2 3 R6 2.7kΩ C2 120pF 4 R13 20kΩ 5 R9 91kΩ 6 7 8 C5 1.5nF D5 1N5406 D6 1N5406 9 C3 0.1µF R12 2.7kΩ R1 0.25Ω R11 8.2kΩ R22 7.3Ω GND ILIM CT IA OUT IA– VREF IA+ VCC ISINE OUT PGND EA OUT RT EA– OVP VRMS SOFT START SYNC 18 17 16 15 14 13 12 11 10 C6 43nF R14 91kΩ C4 1.5nF R20 825kΩ C8 R21 6.2kΩ R15 27kΩ C7 0.47µF Figure 12. 200W Output PFC Circuit 10 Micro Linear C10 0.1µF R19 10.2kΩ R18 825kΩ C11 750pF R17 10.5kΩ DC OUT 382V – ML4821 PHYSICAL DIMENSIONS inches (millimeters) Package: P18 18-Pin PDIP 0.890 - 0.910 (22.60 - 23.12) 18 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26) PIN 1 ID 1 0.045 MIN (1.14 MIN) (4 PLACES) 0.050 - 0.065 (1.27 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) SEATING PLANE 0.016 - 0.022 (0.40 - 0.56) 0.125 MIN (3.18 MIN) 0º - 15º 0.008 - 0.012 (0.20 - 0.31) Package: S20 20-Pin SOIC 0.498 - 0.512 (12.65 - 13.00) 20 0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID 1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0º - 8º 0.090 - 0.094 (2.28 - 2.39) 0.012 - 0.020 (0.30 - 0.51) SEATING PLANE 0.005 - 0.013 (0.13 - 0.33) Micro Linear 0.022 - 0.042 (0.56 - 1.07) 0.007 - 0.015 (0.18 - 0.38) 11 ML4821 ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE PACKAGE ML4821CP ML4821CS 0°C to 70°C 0°C to 70°C 18-Pin PDIP (P18) 20-Pin SOIC (S20) ML4821IP ML4821IS –40°C to 85°C –40°C to 85°C 18-Pin PDIP (P18) (Obsolete) 20-Pin SOIC (S20) (Obsolete) © Micro Linear 1997 Micro Linear is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 12 Micro Linear 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 DS4821-01