INTEGRATED CIRCUITS NE57811 Advanced DDR memory termination power with shutdown Product data Supersedes data of 2002 Jul 16 2003 Apr 02 Philips Semiconductors Product data Advanced DDR memory termination power with shutdown NE57811 DESCRIPTION The NE57811 is designed to provide power for termination of a Double Data Rate (DDR) SDRAM memory bus. It significantly reduces parts count, board space, and overall system cost compared to previous solutions. The NE57811 DDR termination regulator maintains an output voltage (DDR reference bus voltage) that is one-half that of the RAM supply voltage. It is capable of providing up to ±3.5 A for sustained periods. Overcurrent limiting protects the NE57811 from inrush currents at start-up, and overtemperature shutdown protects the device in extreme temperature situations. The SPAK-5 (SOT756) package is thermally robust for flexibility of thermal design. Because the NE57811 is a linear regulator, no external inductors or switching FETs are necessary. Fast response to load changes reduces the need for output capacitors. FEATURES APPLICATIONS • Fast transient response time • Overtemperature protection • Overcurrent protection • Commercial (0 °C to +70 °C) temperature range • Reduced need for external components • Desktop microcomputer systems • Workstations • Servers • Game machines • Set top boxes • Embedded systems • Digital video recorders (switching FETs, inductors, decoupling capacitors) • Internal divider maintains termination voltage at 1/2 memory supply voltage • Reference out for other memory and control components • Shutdown pin that may be used to put the device into low power mode • Compatible with DDR-I (VDD = 2.5 V) or DDR-II (VDD = 1.8 V) SDRAM systems SIMPLIFIED SYSTEM DIAGRAM DIMM0 DIMM1 RefOut SHTDWN (optional) 0.1 µF Control & Address VTT NE57811 MEMORY CONTROLLER Data 100 µF TERMINATION POWER RT 27 Ω (typical) RS 20 Ω (typical) SL01690 Figure 1. Simplified system diagram. 2003 Apr 02 2 Philips Semiconductors Product data Advanced DDR memory termination power with shutdown NE57811 ORDERING INFORMATION PACKAGE NAME DESCRIPTION VERSION TEMPERATURE RANGE SPAK-5 plastic single-ended surface mounted package; 5 leads SOT756 0 °C to +70 °C TYPE NUMBER NE57811S Part number marking The package is marked with the part number under the logo. The second line indicates wafer lot number. The first four characters of the third line contain a date code. The remaining characters are manufacturing codes. PIN CONFIGURATION PIN DESCRIPTION 1 2 3 4 5 VTT VDD VSS SHTDWN RefOut PIN SYMBOL DESCRIPTION 1 VTT Regulated terminator voltage 2 VDD Power supply 3 VSS Circuit ground (Note 1) 4 SHTDWN Shutdown 5 RefOut Reference voltage out NOTE: 1. The thermal backside pad connects electrically to VSS internally and provides enhancement to thermal conductivity, but it should not be used as the primary connection to ground. Device specifications apply to use of the VSS pin as the connection to ground. SL01691 Figure 2. Pin configuration. MAXIMUM RATINGS SYMBOL PARAMETER MIN. TYP. MAX. UNIT –0.3 – +3.6 V 0 – +70 °C VDD VDD to VSS voltage Tamb Operating ambient temperature Tstg Storage temperature –40 – +165 °C Tj Junction temperature – – 160 °C Rth(j-a) Thermal resistance, junction to ambient – 16.5 – °C/W PD Power dissipation (Note 1) – – 3.3 W NOTE: 1. Tested on a minimum footprint on a four-layer PCB per JEDEC specification JESD51-7. 2003 Apr 02 3 Philips Semiconductors Product data Advanced DDR memory termination power with shutdown NE57811 ELECTRICAL CHARACTERISTICS Tamb = 0 °C to +70 °C, VDD = 2.5 V; ITT = –3.5 A to +3.5 A, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT – VDD/2 – V –15 – +15 mV 1.6 – 3.6 V VTT Output voltage VACC Output voltage accuracy (Note 4) VDD Supply voltage IQ(op) Supply current ITT = 0 A – 14 30 mA IQ(SD) Standby quiescent current Standby asserted – 1.2 1.35 mA ITT Output current VDD = 2.5 V ≤ VDD ≤ 3.6 V –3.5 – +3.5 A VDD = 1.6 V –2.5 – +2.5 A ITT = ±1.0 A – ±6 – mV ITT = ±3.5 A –18 – +18 mV – 100 – µF –15 VDD/2 +15 mV 2.2 3 – mA 0.1 – – µF 3.6 4.5 5.6 A ∆VTT CLOAD Load regulation Load capacitance (Note 2) ITT = 0 A Stable operation Reference Out RefOut Voltage reference out (Note 3) IrefOut Reference Out current max CLOAD Load capacitance IrefOut = 0 A; source or sink Stable operation Power Stage Ilim Current limit Tlim Temperature shutdown – +150 – °C Temperature shutdown hysteresis – 20 – °C NOTES: 1. Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. 2. Ceramic capacitors only. Low ESR electrolytic capacitors are not necessary. 3. RefOut voltage referenced to 1/2 VDD. 4. VACC = VTT – VDD/2. 2003 Apr 02 4 Philips Semiconductors Product data Advanced DDR memory termination power with shutdown NE57811 TYPICAL PERFORMANCE CURVES SL01687 SL01688 Figure 3. VTT transient response (output filter 50 µF ceramic) Figure 4. VDD-to-VTT response (output filter 50 µF ceramic) 1.300 1.290 NORMAL OPERATING REGION 1.280 1.270 1.260 Volts 1.250 1.240 1.230 OUTPUT SINK OUTPUT SOURCE 1.220 1.210 1.200 –6 –5 –4 –3 –2 –1 0 1 2 3 4 Amps Figure 5. Typical VTT versus output current (VDD = 2.5 V @ 25 °C) 2003 Apr 02 5 5 6 SL01684 Philips Semiconductors Product data Advanced DDR memory termination power with shutdown NE57811 TECHNICAL DISCUSSION The NE57811 supplies power to the DDR memory bus termination resistors at nominally 1/2 the voltage supplied to the memory ICs or DIMMs. DDR memory output drivers source and sink current into and out of their outputs. A typical DDR memory system is seen in Figure 1 (page 2). Each input/output pin on the bus has a series 20 Ω resistor connected to it. The bus is terminated to the DDR terminator though a 27 to 50 Ω resistance. The memory system will then require current from the VTT terminator bus only when the instantaneous value of the aggregate bus state are not equal amounts of 1s and 0s. When memory bus speeds are in the 200–300 MHz region, the period of any single bus state is extremely small. This permits the DDR bus termination regulator to be a linear ‘power Op Amp’ that can source and sink current instantly to the DDR bus from the VDD supply voltage. This yields the worst case current loading equation: I O(max) + Where: NDDR is the total number of terminated control, address and data lines within the DDR memory system. (typically 192) RT is the value of the terminating resistors. RS is the value of the series resistors from the active output driver. Hence the worst-case current loading condition, where there are either all 1s or all 0s for an instant, and RT is 27 Ω and RS is 20 Ω, produces an instantaneous output current of either + or – 3.5 Amperes. Figure 6 models the VTT loading condition of each bus line equivalent circuit during operation and with terminating resistors. VDD VDD N DDR V DD 2(R T ) R S) VDD 2 VDD 100 kΩ VTT OVER CURRENT OVER TEMPERATURE 1 VTT RefOut 5 VSS VSS VSS 100 kΩ VSS 3 SL01692 4 Figure 6. VTT loading conditions. SHTDWN Figure 7. Block diagram. 2003 Apr 02 6 SL01693 VTT Philips Semiconductors Product data Advanced DDR memory termination power with shutdown NE57811 THERMAL DESIGN dimension as given on the X axis. If you use a double-sided PCB with some plated-through holes to help transfer heat to the bottom side, the thermal resistance only improves by about 3 – 4 °C/W. Designing the proper thermal system for the NE57811 is important to its reliable operation. The NE57811 will be operating at an average power level less than the maximum rating of the part. In a typical DDR terminator system the average power dissipation is between 0.8 and 1.5 watts. The termination power will vary as the average number of ‘1s’ and ‘0s’ changes during normal operation of the DDR memory. The load current will assume a new value for each bus cycle at a 266 MHz rate, and will increase and decrease as the statistical average of bus states change. After the power is estimated, the minimum PCB area can be determined by calculating the worst case thermal resistance and referring to Figure 8 to determine the PCB area. This is done by: R qJA(min) + The terminator heatsink must be designed to accommodate the average power as a steady state condition and be able to withstand momentary periods of increased dissipation, typically 2 – 5 seconds duration. For the typical NE57811 application, the power dissipated by the terminator can be calculated: P D + I DD(VTT)Watts Eqn. (2) PD Where: Tj is the maximum desired junction temperature Tamb is the highest expected local ambient temperature PD is the estimated average power Eqn. (1) The junction temperature should be kept well away from the over-temperature cutoff threshold temperature (+150 °C) in normal operation. The thermal resistance of a surface mount package is given as Rth(j-a), the thermal resistance from the junction to air. JESD51-7 specifies a 4-layer multiplayer PCB (2oz/1oz/1oz/2oz copper) that is 4 inches on each side. This is probably the best (or lowest) thermal resistance you will see in any application. Most applications cannot afford the PCB area to create this situation, but the thermal performance of a multilayer PCB will still provide a significant heatsinking effect. The actual thermal resistance will be higher than the 16.5 °C/W given for the 4-layer JEDEC PCB. Using the above power dissipation, the highest ambient temperature and a junction temperature of +125 °C, calculate the maximum thermal resistance (1.5 watts is used only as an example). o o R th(j–a)(min) + 125 C * 70 C + 36.6 o CńW 1.5W Eqn. (3) Looking at Figure 8, you see that this power dissipation requires a minimum PCB island area of 225 mm2 (15 mm on each side). This is the smallest area you could use at this power dissipation. Of course, increasing this area will allow the NE57811 to operate at cooler temperatures, thus enhancing its long-term reliability. Figure 8 shows the thermal resistance you can expect for heatsinking PCB areas less than the JEDEC specification. The graph is for a 2 oz. single-sided PCB with a square area of the side 10 40.0 35.0 0.25 s 30.0 0.5 s 25.0 I DD (A) THERMAL RESISTANCE ( ° C/W) T j * T amb 20.0 DC 1 15.0 10.0 5.0 0.0 0.1 0 20 40 60 80 100 1 LENGTH OF SIDE OF 2 oz. COPPER AREA (mm) 3 4 5 6 7 8 9 10 VDD (V) SL01670 SL01678 Figure 8. PCB heatsink area versus thermal resistance. 2003 Apr 02 2 Figure 9. Safe operating area for the NE57811. 7 Philips Semiconductors Product data Advanced DDR memory termination power with shutdown NE57811 APPLICATION INFORMATION VSS so that the output will better track any variations in the VDD voltage. The NE57811 can be used in a variety of DDR memory configurations. Its small footprint, fast transient response and lessened need for large bulk output capacitance, makes it highly adaptable. Some of these methods of use are given below. For different memory sizes, the values of the recommended output filter capacitances will change. For a 256 MByte memory space, for example, approximately 100 µF of ceramic surface mount chip capacitors should be evenly distributed across the physical memory layout. Depending upon the PCB noise environment, this could be 10 pieces of 10 µF, 20 pieces of 5 µF, and so on. Normal operating mode (VTT = VDDR/2) The most common implementation of a DDR terminator regulator using the NE57811 is shown in Figure 10. The NE57811 has an internal resistor divider between the VDD (pin 2) and VSS (pin 3) pins which maintains the output voltage, VTT, at VDD/2. Typically, the VDD voltage is the DDR RAM supply voltage, which can range from 1.8 V to 2.5 V. The center node of this resistor divider is the reference for the VTT output voltage and the buffered RefOut signal (pin 5). It might be possible to reduce the total capacitance, provided the performance remains stable. Examine the behavior of the VTT bus carefully when the system is operating and verify that deviations in the bus voltage do not exceed the DDR specification (±40 mV). There are two components to the memory signal load: a high frequency component caused by the 266 MHz plus speed of the address, data, and control buses, and a low frequency component caused by the time-average skew of all of the bus states away from an equal number of 1s and 0s. Electrolytic and tantalum capacitor appear inductive at the high frequencies. Therefore two types of capacitors are needed for the output filtering. Use of the SHTDWN signal and low power mode The NE57811 provides an optional SHTDWN pin that may be used to put the device into low power mode. When SHUTDOWN is asserted (LOW), the VTT power amplifier is turned off and the output is 3-Stated. This brings the quiescent current of the entire device to less than 800 µA. If the pin is not externally connected, and internal 10 kΩ resistor biases the control logic to VDD causing the output sections to be turned on and the NE57811 operates normally. A very good, low ESR electrolyic capacitor of no less than 470 µF should be placed next to the terminator, which should be placed as close as possible to the memory array. One half of the high frequency filter capacitors should be to VDD and the other half to SHTDWN VDD (HF) 2 1 VDD +VTT VTT NE57811 CIN 4 SHTDWN COUT (LF) VSS COUT (HF) RefOut 5 3 GND GND VREF SL01694 Figure 10. Normal operating method (VTT = VDD/2) 2003 Apr 02 8 Philips Semiconductors Product data Advanced DDR memory termination power with shutdown NE57811 TEST CIRCUITS 2 VDD NE57811 CIN R(LOAD) 1 VTT VIN 820 µF OSCON VSS (5 ea) 10 µF CERAMIC 3 820 µF OSCON GND LIGHT LOAD HEAVY LOAD SL01695 Figure 11. Load transient test (+3 A – –3 A). VIN 0.4 V 2 VDD NE57811 4 VIN 2.5 V SHTDWN VTT 1 VSS 3 SL01696 Figure 12. VDD to VTT transient test. 2003 Apr 02 9 Philips Semiconductors Product data Advanced DDR memory termination power with shutdown NE57811 PACKING METHOD The NE57811 is packed in reels, as shown in Figure 13. GUARD BAND TAPE REEL ASSEMBLY TAPE DETAIL COVER TAPE CARRIER TAPE BARCODE LABEL BOX SL01305 Figure 13. Tape and reel packing method. 2003 Apr 02 10 Philips Semiconductors Product data Advanced DDR memory termination power with shutdown Plastic single-ended surface mounted package; 5 leads 2003 Apr 02 11 NE57811 SOT756 Philips Semiconductors Product data Advanced DDR memory termination power with shutdown NE57811 REVISION HISTORY Rev Date Description _2 20030402 Product data (9397 750 11216). ECN 853-2360 29724 of 28 March 2003. Supersedes data of 2002 Jul 16. Modifications: • Page 4, Electrical characteristics table: – (description): from “Tamb = 25 °C” to “Tamb = 0 °C to +70 °C” – Output voltage accuracy: add symbol “VACC”; add Note 4; change Min. value from “–10” to “–15”; change Max. value from “+10” to “+15”. – Change symbol “IQ” to “IQ(op)”; change Typ. value from “20” to “14” – Add IQ(SD) row to table. – ITT: change Condition from “VDD = 2.25 – 3.6 V” to “2.5 V ≤ VDD ≤ 3.6 V”. – ∆VTT, under condition ITT = ±3.5 A: change Min. value from “–20” to “–18”; change Max. value from “+20” to “+18”. – RefOut: add condition “IrefOut = 0 A; source or sink”; change Min. value from “–10” to “–15”; change Max. value from “+10” to “+15”. – Change subheading row from “Protection” to “Power Stage”. _1 20020716 2003 Apr 02 Product data (9397 750 10151). ECN 853-2360 28625 of 16 July 2002. 12 Philips Semiconductors Product data Advanced DDR memory termination power with shutdown NE57811 Data sheet status Level Data sheet status [1] Product status [2] [3] Definitions I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 04-03 For sales offices addresses send e-mail to: [email protected]. Document order number: 2003 Apr 02 13 9397 750 11216