INTEGRATED CIRCUITS DATA SHEET OM4031T Digital post-detection filter for FSK data receivers Preliminary specification File under Integrated Circuits, IC03 Philips Semiconductors October 1994 Philips Semiconductors Preliminary specification Digital post-detection filter for FSK data receivers OM4031T FEATURES GENERAL DESCRIPTION • External clock frequency 30 to 80 kHz (typ. 38.4 kHz) The OM4031T is intended for performance enhancement of FSK data receivers that do not have a built-in post-detection filter. • Supported data rates 600, 1200, 2400 and 4800 bits/s (typ.) It contains a digital moving average filter to remove noise from the demodulated data. When operated from a 38.4 kHz external clock it can handle data rates of 600, 1200 and 2400 bits/s at an oversampling rate of 16. The filter bandwidth can be doubled to ease the search for bit synchronization on the output data. • Double bandwidth option (not for 4800 bits/s) • Schmitt-triggered inputs for optimum slope tolerance • Enable input for power-down mode • Open-drain output (3-state in power-down mode) • No external components required To allow for jitter in the input data, a 12-bit sample is taken for the majority decision. Doubling the filter bandwidth is realised by taking the majority out of 6 samples (2400 bits/s) or by doubling the sampling rate (600 and 1200 bits/s). • Single supply voltage from 1.8 to 6.0 V • Very low operating current (1.5 µA typ.) • Operating temperature from −10 to +70 °C. An input data rate of 4800 bits/s is supported at 8 times oversampling and normal bandwidth. APPLICATIONS All inputs are Schmitt-triggered to ensure reliable operation even at signals with long rise/fall times. • Telemetry data receivers • RF security systems • Low-bit-rate radio data links • Paging applications of UAA2080 and UAA2082 with software decoding. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT 1.8 − 6.0 V CE = VSS − 1.0 10.0 µA CE = VDD; note 1 − 1.5 20.0 µA − 5.3 − dB 1200 bits/s, 250 µs slope − 3.6 − dB 2400 bits/s, 125 µs slope − 2.0 − dB − +70 °C VDD supply voltage IDDPD power-down supply current IDD operating supply current Pi(ref) sensitivity improvement at 3% bit error rate note 2 600 bits/s, 250 µs slope −10 operating ambient temperature Tamb MIN. Notes 1. VDD = 2.0 V; DOUT open-circuit; input data at 20 kHz random pattern. 2. Bench evaluated for UAA2080H at 470 MHz, not factory tested. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME OM4031T October 1994 SO8 DESCRIPTION plastic small outline package; 8 leads; body width 3.9 mm 2 VERSION SOT96-1 Philips Semiconductors Preliminary specification Digital post-detection filter for FSK data receivers OM4031T BLOCK DIAGRAM handbook, full pagewidth VSS VDD 4 8 1 DIN 13-BIT SHIFT REGISTER OM4031T OUTPUT LATCH MAJORITY LOGIC CLK CE 3 CINT 2 DBW PDN DATA RATE AND BANDWIDTH CONTROL 5 7 6 DOUT A1 A0 MLC273 Fig.1 Block diagram. PINNING SYMBOL PIN DESCRIPTION DIN 1 data input CE 2 chip enable input CLK 3 external clock input VSS 4 negative supply voltage DOUT 5 data output (open-drain) A0 6 data rate and bandwidth control input 0 (see Table 1) A1 7 data rate and bandwidth control input 1 (see Table 1) VDD 8 positive supply voltage October 1994 handbook, halfpage DIN 1 CE 2 8 V DD 7 A1 OM4031T CLK 3 6 A0 V SS 4 5 DOUT MLC274 Fig.2 Pin configuration. 3 Philips Semiconductors Preliminary specification Digital post-detection filter for FSK data receivers OM4031T FUNCTIONAL DESCRIPTION Filter implementation The OM4031T digital post-detection filter oversamples the noisy binary data stream at input DIN (pin 1), and outputs a noise-reduced data stream via open-drain output DOUT (pin 5). The filter bandwidth can be doubled to ease the search for bit synchronization on the data output signal. The moving average filter is implemented using a 13-bit register and two state machines (COUNT and CLOCK) for the majority decision. The first stage of the shift register is used for input synchronization. The CLOCK state machine generates the internal clock signal CINT and the bandwidth selection signal DBW in accordance with the logic levels on control lines CE, A0 and A1. Input sampling takes place at 16 times the data rate. For a typical clock frequency of 38.4 kHz the nominal data rates are 600, 1200 and 2400 bits/s. A data rate of 4800 bits/s can be handled at an oversampling rate of 8 and at normal bandwidth only. The majority decision is taken by state machine COUNT based on the contents of the input shift register and the previous decision in the output latch. Using a different clock frequency will produce bit rates equal to the clock frequency divided by 64, 32 or 16. When the clock frequency is not an integer multiple of the data rate some edge jitter will be introduced in the output data. The doubled bandwidth is achieved by increasing the sampling rate by a factor of 2 for 600 and 1200 bits/s. For 2400 bits/s the number of samples for the majority decision is halved, controlled by the DBW signal. This signal is derived from the control signals as follows: The clock frequency is not very critical for the noise filtering performance: a clock frequency of 32.768 kHz could be used at 512, 1200 and 2400 bits/s without loss of performance. DBW = CE • A0 • A1 Since no on-chip oscillator is available an external clock signal is required at input CLK (pin 3). Two control inputs A0 and A1 (pins 6 and 7) are used for selection of the data rate and the filter bandwidth. A separate enable input CE (pin 2) allows the circuit to be powered down. In power-down mode (CE = LOW) the system clock is inhibited and the data output DOUT is made 3-state and remains static. Moving average noise filter Noise reduction is achieved by applying a moving average filter on N samples of the input data signal. In principle N can be odd or even, but in the OM4031T an even number is used (N = 12). When there is no absolute majority (equal number of ones and zeroes) the previous majority output is maintained. An odd value for N would always produce an absolute majority and not require decision feedback. However the noise performance is worse for odd values of N, because the output can toggle at every clock (e.g. when a 101010... pattern is clocked in). For even values of N the output polarity can only change once every 3 clocks and does not toggle at all for a 101010... or a 11001100... pattern. Using 12 out of 16 samples for the majority decision produces a filter which combines good noise reduction with a large tolerance for data jitter (maximum 1⁄8-bit duration). October 1994 4 Philips Semiconductors Preliminary specification Digital post-detection filter for FSK data receivers OM4031T At normal bandwidth the oversampling rate is 16, except for 4800 bits/s where it is 8. At double bandwidth the oversampling rate is 32, except for 2400 bits/s, where it is 16. Filter characteristic The frequency characteristic of the moving average filter in the OM4031T is given in Fig.3 for N = 12 and N = 6. The horizontal axis shows the normalized frequency fN which is the ratio of the frequency f and the sampling frequency fs. The value for fs is given in Table 1 for the various data rates and filter bandwidths. The 3 dB cut-off frequency is calculated as follows: N = 12: f co = 0.0371 × f s N = 6: f co = 0.0748 × f s The vertical axis shows the normalized amplitude AN. MLC275 1.0 handbook, full pagewidth AN 0.8 0.6 (1) (2) 0.4 0.2 0 0 0.1 0.2 0.3 0.4 0.5 fN (1) N = 12. (2) N = 6. Fig.3 Filter transfer function of the OM4031T. October 1994 5 Philips Semiconductors Preliminary specification Digital post-detection filter for FSK data receivers OM4031T The OM4031T was also tested in a POCSAG pager application using software decoding together with the UAA2080H receiver. Noise reduction The performance of the OM4031T was bench tested by measuring the sensitivity improvement (3% BER) of the UAA2080H pager receiver at various bit rates using a stand-alone pager receiver board (OM4647 at 470 MHz). The results are given in Chapter “AC Characteristics” . For 12-digit numeric messages at 1200 bits/s the typical sensitivity for 80% call success rate improved by 2.8 dB, as shown in Fig.4. MLC276 100 handbook, call full pagewidth success rate (%) 80 60 40 20 no filter with OM4031T 0 120 121 122 123 125 124 126 127 128 129 130 RF level (dBm) Fig.4 Paging call success rate improvement; 1200 bits/s, 12-digit numeric message. October 1994 6 Philips Semiconductors Preliminary specification Digital post-detection filter for FSK data receivers OM4031T The parameter fs is the input sampling frequency, assuming a 38.4 kHz external clock signal. OPERATING INSTRUCTIONS Control signals The logic levels on A0 and A1 can be changed while CE = HIGH, except to select or deselect 2400 bits/s with doubled bandwidth (A1 = LOW, A0 = HIGH). This mode must be entered or left while CE = LOW to avoid data errors on DOUT. The operation of the OM4031T is determined by 3 control signals (CE, A0 and A1) and the clock frequency at input CLK. Table 1 shows the various possibilities for a typical clock frequency of 38.4 kHz. The parameter N is the number of samples used in the calculation of the average bit value. Table 1 Data rate and filter bandwidth selection DATA RATE (bits/s) N (samples) CE A1 A0 0 X X X 1 0 0 12 1 1 0 12 fs (kHz) NORMAL BANDWIDTH DOUBLE BANDWIDTH X X X 9.6 600 − 19.2 1200 600 2400 1200 1 0 1 6 38.4 4800(1) 1 1 1 12 38.4 2400 Note 1. At 4800 bits/s the oversampling rate is 8. The status after reset is as follows: Power-down mode • The shift register contains a 101010... pattern To reduce power consumption the filter can be disabled by applying a LOW level to input CE. The result is as follows: • DOUT is made LOW. • The internal clock is inhibited After power-up input CE must be kept at a LOW level for at least one clock period on input CLK. This ensures a successful reset when CE is made HIGH. • Output DOUT is made 3-state and static. Reset The OM4031T is reset internally when power-down mode is left by applying a HIGH level to input CE. The actual reset takes place on the second falling edge on input CLK after CE = HIGH. October 1994 7 Philips Semiconductors Preliminary specification Digital post-detection filter for FSK data receivers OM4031T LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC134). SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage −0.5 7.0 V VI input voltage on any pin −0.5 VDD + 0.5 V II DC input current all pins − 20 mA IO DC output current all pins − 20 mA Ptot total power dissipation − 150 mW Tamb operating ambient temperature −10 +70 °C Tstg storage temperature −55 +125 °C DC CHARACTERISTICS VDD = 1.8 to 6.0 V; VSS = 0 V; Tamb = −10 to +70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDD supply voltage 1.8 − 6.0 V IDDPD power-down supply voltage CE = VSS; note 1 − 1.0 10.0 µA IDD operating supply current − 1.5 20.0 µA V CE = VDD; notes 1 and 2 Inputs A0, A1, CLK and CE VIL LOW level input voltage −0.5 − +0.3VDD VIH HIGH level input voltage 0.7VDD − VDD + 0.5 V ILI input leakage current VI = VDD or VI = VSS − − 1.0 µA CI input capacitance tested on sample basis − 2.0 − pF IOL LOW level output current VOL = 0.4 V 1.0 − − mA ILO output leakage current VOH = VDD − − 1.0 µA Output DOUT Notes 1. VDD = 2.0 V; VIL = VSS; VIH = VDD; DOUT is open-circuit; clock signal at input CLK; fclk = 38.4 kHz, amplitude: VSS to VDD; data signal at input DIN: random pattern at 20 kHz to simulate 2400 bits/s data with noise; tr = tf = 5 ns. 2. The operating current will be higher than specified when the input signal amplitude is less than 100% (equals VSS to VDD) or when longer rise/fall times are used. This is caused by the Schmitt-trigger circuits drawing extra current. October 1994 8 Philips Semiconductors Preliminary specification Digital post-detection filter for FSK data receivers OM4031T AC CHARACTERISTICS VDD = 1.8 to 6.0 V; VSS = 0 V; Tamb = −10 to +70 °C; fclk = 38.4 kHz; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 80 kHz External clock fclk external clock frequency 30 38.4 Filter bandwidth (note 1) fco cut-off frequency (−3 dB) normal bandwidth 600 bits/s − 356 − Hz 1200 bits/s − 712 − Hz 2400 bits/s − 1425 − Hz 4800 bits/s − 2872 − Hz − 712 − Hz double bandwidth 600 bits/s 1200 bits/s − 1425 − Hz 2400 bits/s − 2872 − Hz − 5.3 − dB 1200 bits/s, 250 µs slope − 3.6 − dB 2400 bits/s, 125 µs slope − 2.0 − dB Noise reduction (note 2) Pi(ref) sensitivity improvement at 3% bit error rate note 3 600 bits/s, 250 µs slope Notes 1. Filter bandwidth is guaranteed by design. Values supplied are simulation results. 2. Noise reduction is not factory tested, only bench evaluated. 3. Sensitivity improvement was bench tested on the UAA2080H demonstration board OM4747. Test signal: preamble (101010...), fiRF = 469.950 MHz, deviation = ±4.0 kHz, slope = 10 to 90% of amplitude, VP = 2.05 V, Tamb = 25 °C. See “UAA2080 data sheet, AC characteristics”. October 1994 9 Philips Semiconductors Preliminary specification Digital post-detection filter for FSK data receivers OM4031T APPLICATION INFORMATION VDD andbook, full pagewidth VCC VCC R pull DO RF DIN FSK RECEIVER DOUT OM4031T CE CE CLK A1 MICROCONTROLLER A0 38.4 kHz MLC277 Fig.5 Typical application example. The OM4031T will generally operate from the same power supply (VCC) as the FSK data receiver providing its input data. The open-drain data output allows level shifting of the data to suit a microcontroller operating at a higher power supply voltage (VDD). For the highest rate (2400 bits/s) the signal rise time should preferably be below 50 µs. For a single CMOS input with a 10 pF capacitance Rpull = 1 MΩ gives a rise time of approximately 30 µs (3 × tRC). At VDD = 2.0 V this corresponds with a current of 2 µA. The value of the pull-up resistor Rpull on output DOUT is determined by the type and number of input circuits to be driven. The required signal rise time must be balanced against the current drawn by the pull-up. October 1994 10 Philips Semiconductors Preliminary specification Digital post-detection filter for FSK data receivers OM4031T PACKAGE OUTLINE 4.0 3.8 5.0 4.8 handbook, full pagewidth S A 6.2 5.8 0.1 S 0.7 0.3 5 8 0.7 0.6 1.45 1.25 1 4 1.0 0.5 0.25 0.10 pin 1 index detail A 1.27 0.49 0.36 1.75 1.35 0.25 0.19 0 to 8 o MBC180 - 1 0.25 M (8x) Dimensions in mm. Fig.6 Plastic small outline package; 8 leads; body width 3.9 mm (SO8; SOT96-1). October 1994 11 Philips Semiconductors Preliminary specification Digital post-detection filter for FSK data receivers OM4031T applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. SOLDERING Plastic small-outline packages Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 °C. BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 °C. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 °C within 6 s. Typical dwell time is 4 s at 250 °C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING IRON OR PULSE-HEATED SOLDER TOOL) Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 °C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 °C. (Pulse-heated soldering is not recommended for SO packages.) A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be October 1994 12 Philips Semiconductors Preliminary specification Digital post-detection filter for FSK data receivers OM4031T DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. October 1994 13 Philips Semiconductors Preliminary specification Digital post-detection filter for FSK data receivers OM4031T NOTES October 1994 14 Philips Semiconductors Preliminary specification Digital post-detection filter for FSK data receivers OM4031T NOTES October 1994 15 Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SÃO PAULO-SP, Brazil. P.O. Box 7383 (01064-970). Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. (708) 296-8556 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. 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