INTEGRATED CIRCUITS DATA SHEET TDA1311A Stereo Continuous Calibration DAC (CC-DAC) Preliminary specification Supersedes data of July 1993 File under Integrated Circuits, IC01 1995 Dec 18 Philips Semiconductors Preliminary specification Stereo Continuous Calibration DAC (CC-DAC) TDA1311A FEATURES GENERAL DESCRIPTION • Voltage output The TDA1311A; AT is a voltage-driven digital-to-analog converter and is new generation of DAC devices which embodies the innovative technique of Continuous Calibration (CC). The largest bit-currents are repeatedly generated by one single current reference source. This duplication is based upon an internal charge storage principle which has an accuracy insensitive to ageing, temperature matching and process variations. • Space saving packages SO8 or DIP8 • Low power consumption • Wide dynamic range (16-bit resolution) • Continuous Calibration (CC) concept • Easy application: – single 4 to 5.5 V rail supply The TDA1311A; AT is fabricated in a 1.0 µm CMOS process and features an extremely low-power dissipation, small package size and easy application. Furthermore, the accuracy of the intrinsic high coarse-current combined with the implemented symmetrical offset decoding method preclude zero-crossing distortion and ensures high quality audio reproduction. Therefore, the CC-DAC is eminently suitable for use in (portable) digital audio equipment. – output current and bias current are proportional to the supply voltage – integrated current-to-voltage converter • Fast settling time permits 2, 4 and 8 × oversampling (serial input) or double-speed operation at 4 × oversampling • Internal bias current ensures maximum dynamic range • Wide operating temperature range (−40 °C to +85 °C) • Compatible with most current Japanese input formats: time multiplexed, two's complement, TTL • No zero-crossing distortion • Cost efficient. ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION TDA1311A DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1 TDA1311AT SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 1995 Dec 18 2 Philips Semiconductors Preliminary specification Stereo Continuous Calibration DAC (CC-DAC) TDA1311A QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDD supply voltage 4 5 5.5 V IDD supply current VDD = 5 V at code 0000H − 3.4 6.0 mA VFS full scale output voltage VDD = 5 V 1.8 2.0 2.2 V (THD+N)/S total harmonic distortion plus noise at 0 dB signal level − −68 −63 dB − 0.04 0.07 % − −30 −24 dB − 3 6 % at −60 dB signal level; A-weighted − −33 − dB − 2 − % A-weighted at code 0000H 86 92 − dB at −60 dB signal level S/N signal-to-noise ratio at bipolar zero tcs current settling time to ±1 LSB − 0.2 − µs BR input bit rate at data input − − 18.4 Mbits/s fBCK clock frequency at clock input − − 18.4 MHz TCFS full scale temperature coefficient at analog outputs (IOL; IOR) − ±400 − ppm Tamb operating ambient temperature −40 − +85 °C Ptot total power dissipation − 17 30 mW 1995 Dec 18 VDD = 5 V at code 0000H 3 Philips Semiconductors Preliminary specification Stereo Continuous Calibration DAC (CC-DAC) TDA1311A BLOCK DIAGRAM handbook, full pagewidth VOL 6 I/V LEFT INPUT REGISTER RIGHT INPUT REGISTER LEFT OUTPUT REGISTER RIGHT OUTPUT REGISTER LEFT BIT SWITCHES RIGHT BIT SWITCHES I/V IOL 11-BIT PASSIVE DIVIDER BCK WS DATA 32 (5-BIT) CALIBRATED CURRENT SOURCES 32 (5-BIT) CALIBRATED CURRENT SOURCES 1 CALIBRATED SPARE SOURCE 1 CALIBRATED SPARE SOURCE 8 VOR IOR 11-BIT PASSIVE DIVIDER REFERENCE SOURCE 1 2 CONTROL AND TIMING 3 TDA1311A TDA1311AT 5 4 C2 MBG858 100 nF GND Fig.1 Block diagram. PINNING SYMBOL PIN DESCRIPTION BCK 1 bit clock input WS 2 word select input DATA 3 data input GND 4 ground VDD 5 supply voltage VOL 6 left channel output n.c. 7 not connected VOR 8 right channel output handbook, halfpage BCK 1 8 VOR WS 2 7 n.c. TDA1311A DATA 3 TDA1311AT 6 GND 4 5 VOL VDD MBG859 Fig.2 Pin configuration. 1995 Dec 18 4 VDD Philips Semiconductors Preliminary specification Stereo Continuous Calibration DAC (CC-DAC) TDA1311A A symmetrical offset decoding principle is incorporated that arranges the bit switching in such a way that the zero-crossing is performed only by switching the LSB currents. FUNCTIONAL DESCRIPTION The basic operation of the continuous calibration DAC is illustrated in Fig.3. The figure shows the calibration and operation cycle. During calibration of the MOS current source (see Fig.3a) transistor M1 is connected as a diode by applying a reference current. The voltage Vgs on the intrinsic gate-source capacitance Cgs of M1 is then determined by the transistor characteristics. After calibration of the drain current to the reference value IREF, the switch S1 is opened and S2 is switched to the other position (see Fig.3b). The gate-to-source voltage Vgs of M1 is not changed because the charge on Cgs is preserved. Therefore, the drain current of M1 will still be equal to IREF and this exact duplicate of IREF is now available at the OUT terminal. The TDA1311A; AT (CC-DAC) accepts serial input data formats of 16-bit word length. Left and right data words are time multiplexed. The most significant bit (bit 1) must always be first. The input data format is shown in Figs 4 and 5. With a HIGH level on the word select input (WS), data is placed in the left input register and with a LOW level on the WS input, data is placed in the right input register (see Fig.1). The data in the input registers are simultaneously latched in the output registers which control the bit switches. The 32 current sources and the spare current source of the TDA1311A; AT are continuously calibrated (see Fig.1). The spare current source is included to allow continuous converter operation. The output of one calibrated source is connected to an 11-bit binary current divider consisting of 2048 transistors. handbook, full pagewidth An internal offset voltage VOS is added to the full scale output voltage VFS; VOS and VFS are proportional to VDD: VDD1/VDD2 = VFS1/VFS2 = VOS1/VOS2. out out Iref Iref S2 Iref S2 S1 S1 M1 Cgs M1 Vgs Cgs Vgs MBG860 (a) (b) (a) = calibration. (b) = operation. Fig.3 Calibration principle. 1995 Dec 18 5 Philips Semiconductors Preliminary specification Stereo Continuous Calibration DAC (CC-DAC) TDA1311A LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD supply voltage − 6.0 V Tstg storage temperature −55 +150 °C TXTAL maximum crystal temperature − +150 °C Tamb operating ambient temperature Ves electrostatic handling −40 +85 °C note 1 −2000 +2000 V note 2 −200 +200 V Note 1. Human body model: C = 100 pF, R = 1500 Ω, 3 pulses positive and 3 pulses negative. 2. Machine model: C = 200 pF, L = 0.5 µH, R = 10 Ω, 3 pulses positive and 3 pulses negative. THERMAL RESISTANCE SYMBOL Rth j-a PARAMETER VALUE UNIT DIL8 100 K/W SO8 210 K/W thermal resistance from junction to ambient in free air QUALITY SPECIFICATION In accordance with SNW-FQ-0611. CHARACTERISTICS VDD = 5 V; Tamb = 25 °C; measured in Fig.1; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDD supply voltage IDD supply current 4.0 5.0 5.5 V at code 0000H − 3.4 6.0 mA input leakage current LOW VI = 0.8 V − − 10 µA |IIH| input leakage current HIGH VI = 2.4 V − − 10 µA fBCK clock frequency − − 18.4 MHz BR bit rate data input − − 18.4 Mbits/s fWS word select input frequency − − 384 kHz Digital inputs; pins WS, BCK and DATA |IIL| 1995 Dec 18 6 Philips Semiconductors Preliminary specification Stereo Continuous Calibration DAC (CC-DAC) SYMBOL PARAMETER TDA1311A CONDITIONS MIN. TYP. MAX. UNIT Timing (see Fig.4) tr rise time − − 12 ns tf fall time − − 12 ns tCY bit clock cycle time 54 − − ns tBCKH bit clock pulse width HIGH 15 − − ns tBCKL bit clock pulse width LOW 15 − − ns tSU;DAT data set-up time 12 − − ns tHD:DAT data hold time to bit clock 2 − − ns tHD:WS word select hold time 2 − − ns tSU;WS word select set-up time 12 − − ns Analog outputs; pins VOL and VOR VFS full-scale voltage 1.8 2.0 2.2 V TCFS full-scale temperature coefficient − ±400 − ppm Vos offset voltage VDD = VOL/ORmax 0.45 0.50 0.55 V (THD+N)/S total harmonic distortion plus noise at 0 dB signal level; note 1 at −60 dB signal level; note 1 at −60 dB signal level; A-weighted; note 1 at 0 dB signal level; f = 20 Hz to 20 kHz − −68 −63 dB − 0.04 0.07 % − −30 −24 dB − 3 6 % − −33 − dB − 2 − % − −65 −61 dB − 0.05 0.09 % tcs current settling time to ±1 LSB − 0.2 − µs αcs channel separation 75 80 − dB − 0.2 0.3 dB − ±0.2 − µs 86 92 − dB |δIO| unbalance between outputs |td| time delay between outputs S/N signal-to-noise ratio at bipolar zero note 1 A-weighted at code 0000H Note 1. Measured with 1 kHz sinewave generated at sampling rate of 192 kHz. 1995 Dec 18 7 Philips Semiconductors Preliminary specification Stereo Continuous Calibration DAC (CC-DAC) TDA1311A LEFT handbook, full pagewidth WS RIGHT tr <12 tBCKH >15 tf <12 tBCKL >15 tHD; WS >2 >12 tSU; WS BCK tSU; DAT >12 tCY >54 DATA LSB MSB sample out Fig.4 Timing and input signals. 1995 Dec 18 tHD; DAT >2 8 MBG861 Preliminary specification TDA1311A handbook, full pagewidth Philips Semiconductors 9 Fig.5 Format of input signals. Stereo Continuous Calibration DAC (CC-DAC) 1995 Dec 18 LEFT WS LSB MSB LSB MSB DATA BCK RIGHT sample out MBG862 Philips Semiconductors Preliminary specification Stereo Continuous Calibration DAC (CC-DAC) TDA1311A APPLICATION INFORMATION Basic application example A typical example of a CD-application with the TDA1311A; AT is shown in Fig.6. It features typical decoupling components and a third-order analog post-filter stage providing a line output. handbook, full pagewidth VDD 10 Ω 47 µF 100 nF 420 pF 5 22 kΩ 22 kΩ 8 BCK WS DATA 1 100 pF 2.2 nF TDA1311A 7 2 TDA1311AT 420 pF 3 22 kΩ 22 kΩ 6 4 2.2 nF 100 pF MBG863 Fig.6 Example of a 3rd order filter application. 3. Topology: the capacitor decoupling high-frequency supply interference from VDD to GND should be placed as close as is physically possible to the IC body, ensuring a low-inductance path to ground. The digital input conductors may be shielded by ground leads running alongside. The placement of a passive ground plane underside the entire IC surface gives `free` additional decoupling from the IC body to ground as well as providing a shield between the digital input pins and the analog output pins. Attention to printed circuit board layout The TDA1311A and even more so the TDA1311AT offers great ease in designing-in to printed-circuit boards due to its small size and low pin count. The TDA1311A; AT being a mixed-signal IC in CMOS, some attention needs to be paid to layout and topology of the application PCB. Following some basic rules will yield the desired performance. The most important considerations are: 1. Supply: care should be taken to supply the TDA1311A; AT with a clean, noiseless VDD, for a good noise performance of the analog parts of the DAC. Supply purity can easily be achieved by using an RC-filtered supply. Figure 7 shows recommended layouts for printed-circuit boards for the SO8 and DIL8 versions respectively. Both layouts use a single-interconnect layer. 2. Grounding: preferably a ground plane should be used, in order to have a low-impedance return available at any point in the layout. It is advantageous to make a partitioning of the ground plane according to the nature of the expected return currents (digital input returns separate from supply returns and separate from the analog section). 1995 Dec 18 10 Philips Semiconductors Preliminary specification Stereo Continuous Calibration DAC (CC-DAC) TDA1311A handbook, full pagewidth C1 V DD C2 R V DD MSA739 Fig.7 Recommended printed-circuit board layouts. Interface examples The following figures (Figs 8 to 14) show examples of connections to commonly used decoder and digital filter ICs. The digital interface part is shown only, for clarity. The diagrams are for guidance purposes only - no guarantee for industrial exploitation is implied. MBG864 handbook, halfpage BCKO SM5807 LRCOn DOUT 15 14 1 1 12 2 3 BCK WS TDA1311A TDA1311AT DATA remark: SCSLn − signal SM5807 both "L" and "H" supported by TDA1311A and TDA1311AT Fig.8 NPC SM5807 digital filter (4FS). 1995 Dec 18 11 Philips Semiconductors Preliminary specification Stereo Continuous Calibration DAC (CC-DAC) TDA1311A MBG865 handbook, halfpage DOL SM5840 (1) DOR BCKO 14 1 13 2 12 3 BCK WS TDA1311A TDA1311AT DATA OMODn pin 19: "L" for 4FS operation (1) versions A/B/G Fig.9 NPC SM5840 digital filter (4FS). MBG866 handbook, halfpage C2IOn CXD1125 LRCK DATA 76 1 80 2 78 3 BCK WS TDA1311A TDA1311AT DATA MODE SELECT: MD1 pin 55: "L" MD2 pin 56: "L" to use DOTX function MD3 pin 57: "H" PSSL pin 59: "L" SLOB pin 58: "L" Fig.10 Sony CXD1125 decoder (1FS). MBG867 handbook, halfpage 9 7 8 BCK C2IOn LRCK CXD1125 LRD DATA DATA 3 1 1 2 4 3 BCK WS TDA1311A TDA1311AT DATA remark: CXD1162 input connectable to CXD1125 in the same way as for TDA1311A; AT to CXD1125 Fig.11 Sony CXD1162 digital filter (4FS). 1995 Dec 18 12 Philips Semiconductors Preliminary specification Stereo Continuous Calibration DAC (CC-DAC) TDA1311A MBG868 handbook, halfpage DA14 CXD1135 LRCK DA16 76 1 80 2 78 3 BCK WS TDA1311A TDA1311AT DATA MODE SELECT: MD1 pin 55: "L" MD2 pin 56: "L" to use DOTX function MD3 pin 57: "H" for 1FS; "L" for 2FS PSSL pin 59: "L" SLOB pin 58: "L" Fig.12 Sony CXD1135 decoder (1FS) and digital filter (2FS). MBG869 handbook, halfpage DSCK M50423 LRCK DO1 74 1 75 2 72 3 BCK WS TDA1311A TDA1311AT DATA MODE SELECT: DOBSEL pin 7: "L" DASEL1 pin 8: "H" DASEL2 pin 9: "L" DASEL3 pin 10: "H" DASEL4 pin 11: "L" Fig.13 Mitsubishi M50423 decoder (1FS) and digital filter (4FS). MBG870 handbook, halfpage DACLK LC7863 LRCLK DFOUT 35 1 30 2 34 3 BCK WS TDA1311A TDA1311AT DATA MODE SELECT: DFOFF pin 27: "L" MSBF pin 38: "H" Fig.14 Sanyo LC7863 decoder (1FS). 1995 Dec 18 13 Philips Semiconductors Preliminary specification Stereo Continuous Calibration DAC (CC-DAC) TDA1311A Evaluation of audio parameters The following measurement graphs are performed on singular engineering samples; therefore no guarantee of typical parameter values is implied. Measurement conditions are typical, as stated in the section Characteristics, unless otherwise indicated. The normal measurement set-up includes a 20 kHz band-limiting filter for bandwidth definition, and an A-weighting filter where indicated. MBG871 −100 handbook, halfpage THD (dB) −80 −60 −40 −20 0 −100 −80 −60 −40 −20 0 signal level (dB) Fig.15 Total harmonic distortion plus noise as a function of signal level (4FS). MBG873 −20 handbook, halfpage (1) THD (dB) −40 10 THD (%) 1 −60 0.1 (2) −80 −100 10 0.01 102 103 0.001 104 105 frequency (Hz) (1) Measured including all distortion plus noise at a signal level of −60 dB. (2) Measured including all distortion plus noise at a signal level of 0 dB. Fig.16 Total harmonic distortion plus noises as a function of frequency (4FS). 1995 Dec 18 14 Philips Semiconductors Preliminary specification Stereo Continuous Calibration DAC (CC-DAC) TDA1311A MBG872 −50 handbook, halfpage THD (dB) (2) 20 THD (%) (3) −60 0 (1) −20 −70 −40 −80 3 4 5 VDD (V) 6 (1) Measured including all distortion plus noise within the specified operating supply voltage range. (2) Measured including all distortion plus noise outside the specified operating supply voltage range. (3) VFS relative to nominal. Fig.17 Total harmonic distortion plus noise as a function of supply voltage (4FS). 1995 Dec 18 15 Philips Semiconductors Preliminary specification Stereo Continuous Calibration DAC (CC-DAC) TDA1311A PACKAGE OUTLINES DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1 ME seating plane D A2 A A1 L c Z w M b1 e (e 1) b MH b2 5 8 pin 1 index E 1 4 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.14 0.53 0.38 1.07 0.89 0.36 0.23 9.8 9.2 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 1.15 inches 0.17 0.020 0.13 0.068 0.045 0.021 0.015 0.042 0.035 0.014 0.009 0.39 0.36 0.26 0.24 0.10 0.30 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.045 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT97-1 050G01 MO-001AN 1995 Dec 18 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-02-04 16 Philips Semiconductors Preliminary specification Stereo Continuous Calibration DAC (CC-DAC) TDA1311A SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp L 4 1 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.244 0.039 0.028 0.050 0.041 0.228 0.016 0.024 inches 0.010 0.057 0.069 0.004 0.049 0.01 0.01 0.028 0.004 0.012 θ Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03S MS-012AA 1995 Dec 18 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-05-22 17 o 8 0o Philips Semiconductors Preliminary specification Stereo Continuous Calibration DAC (CC-DAC) TDA1311A Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. WAVE SOLDERING This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. DIP SOLDERING BY DIPPING OR BY WAVE • The longitudinal axis of the package footprint must be parallel to the solder flow. The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. • The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1995 Dec 18 18 Philips Semiconductors Preliminary specification Stereo Continuous Calibration DAC (CC-DAC) TDA1311A DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1995 Dec 18 19 Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 513061/50/02/pp20 Document order number: Date of release: 1995 Dec 18 9397 750 00532