Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) DESCRIPTION PLUS153B/D FEATURES The PLUS153 PLDs are high speed, combinatorial Programmable Logic Arrays. The Philips Semiconductors state-of-the-art Oxide Isolated Bipolar fabrication process is employed to produce propagation delays as short as 12ns. • I/O propagation delays (worst case) The 20-pin PLUS153 devices have a programmable AND array and a programmable OR array. Unlike PAL devices, 100% product term sharing is supported. Any of the 32 logic product terms can be connected to any or all of the 10 output OR gates. Most PAL ICs are limited to 7 AND terms per OR function; the PLUS153 devices can support up to 32 input wide OR functions. • Two programmable arrays The polarity of each output is user-programmable as either active-High or active-Low, thus allowing AND-OR or AND-NOR logic implementation. This feature adds an element of design flexibility, particularly when implementing complex decoding functions. The PLUS153 devices are user-programmable using one of several commercially available, industry standard PLD programmers. PIN CONFIGURATIONS N Package – PLUS153B – 15ns max. – PLUS153D – 12ns max. • Functional superset of 16L8 and most other 20-pin combinatorial PAL devices – Supports 32 input wide OR functions • 8 inputs • 10 bi-directional I/O • 42 AND gates – 32 logic product terms – 10 direction control terms I0 1 20 VCC I1 2 19 B9 I2 3 18 B8 I3 4 17 B7 I4 5 16 B6 I5 6 15 B5 I6 7 14 B4 I7 8 13 B3 B0 9 12 B2 GND 10 • Programmable output polarity 11 B1 N = Plastic Dual In-Line Package (300mil-wide) – Active-High or Active-Low • Security fuse • 3-State outputs • Power dissipation: 750mW (typ.) • TTL Compatible A Package APPLICATIONS • Random logic • Code converters • Fault detectors • Function generators • Address mapping • Multiplexing I2 I1 3 2 I0 VCC B9 1 20 19 I3 4 18 B8 I4 5 17 B7 I5 6 16 B6 I6 7 15 B5 I7 8 14 B4 9 10 11 12 13 B0 GND B1 B2 B3 A = Plastic Leaded Chip Carrier ORDERING INFORMATION DESCRIPTION tPD (MAX) ORDER CODE DRAWING NUMBER 20-Pin Plastic Dual-In-Line 300mil-wide 15ns PLUS153BN 0408D 20-Pin Plastic Dual-In-Line 300mil-wide 12ns PLUS153DN 0408D 20-Pin Plastic Leaded Chip Carrier 15ns PLUS153BA 0400E 20-Pin Plastic Leaded Chip Carrier 12ns PLUS153DA 0400E PAL is a registered trademark of Monolithic Memories, Inc., a wholly owned subsidiary of Advanced Micro Devices Corporation. October 22, 1993 9 853–1285 11164 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) PLUS153B/D LOGIC DIAGRAM (LOGIC TERMS–P) I0 1 I1 2 I2 3 I3 4 I4 5 I5 6 I6 7 I7 8 (CONTROL TERMS) B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 S9 X9 X8 X7 X6 X5 X4 X3 X2 X1 31 24 23 16 15 8 7 0 NOTES: 1. All programmed ‘AND’ gate locations are pulled to logic “1”. 2. All programmed ‘OR’ gate locations are pulled to logic “0”. 3. Programmable connection. October 22, 1993 10 X0 S8 S7 S6 S5 S4 S3 S2 S1 S0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 19 B9 18 B8 17 B7 16 B6 15 B5 14 B4 13 B3 12 B2 11 B1 9 B0 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) PLUS153B/D FUNCTIONAL DIAGRAM P31 P0 D0 D9 I0 I7 B0 B9 S9 B9 X9 S0 B0 X0 ABSOLUTE MAXIMUM RATINGS1 THERMAL RATINGS TEMPERATURE RATING SYMBOL PARAMETER MIN MAX UNIT Maximum junction 150°C 75°C VCC Supply voltage +7 VDC Maximum ambient VIN Input voltage +5.5 VDC VOUT Output voltage +5.5 VDC Allowable thermal rise ambient to junction IIN Input currents +30 mA IOUT Output currents +100 mA Tamb Operating free-air temperature range 0 +75 °C Tstg Storage temperature range –65 +150 °C –30 NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. October 22, 1993 11 75°C Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) PLUS153B/D DC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V LIMITS SYMBOL Input PARAMETER TEST CONDITIONS MIN TYP1 MAX UNIT 0.8 V voltage2 VIL Low VCC = MIN VIH High VCC = MAX VIC Clamp Output 2.0 VCC = MIN, IIN = –12mA V –0.8 –1.2 V 0.5 V voltage2 VCC = MIN VOL Low4 IOL = 15mA VOH High5 IOH = –2mA 2.4 V Input current9 VCC = MAX IIL Low VIN = 0.45V –100 µA IIH High VIN = VCC 40 µA VOUT = 2.7V 80 µA VOUT = 0.45V –140 Output current VCC = MAX IO(OFF) IOS ICC Hi-Z state8 Short circuit3, 5, 6 VCC supply current7 VOUT = 0V VCC = MAX –15 150 –70 mA 200 mA Capacitance VCC = 5V CIN Input VIN = 2.0V 8 pF CB I/O VB = 2.0V 15 pF NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Measured with inputs I0 – I2 = 0V, inputs I3 – I5 = 4.5V, inputs I7 = 4.5V and I6 = 10V. For outputs B0 – B4 and for outputs B5 – B9 apply the same conditions except I7 = 0V. 5. Same conditions as Note 4 except I7 = +10V. 6. Duration of short circuit should not exceed 1 second. 7. ICC is measured with inputs I0 – I7 and B0 – B9 = 0V. 8. Leakage values are a combination of input and output leakage. 9. IIL and IIH limits are for dedicated inputs only (I0 – I7). October 22, 1993 12 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) PLUS153B/D AC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V, R1 = 300Ω, R2 = 390Ω LIMITS SYMBOL PARAMETER FROM TO TEST PLUS153B CONDITION MIN PLUS153D MIN UNIT TYP MAX TYP MAX tPD Propagation Delay2 Input +/– Output +/– CL = 30pF 11 15 10 12 ns tOE Output Enable1 Input +/– Output – CL = 30pF 11 15 10 12 ns tOD Output Disable1 Input +/– Output + CL = 5pF 11 15 10 12 ns NOTES: 1. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 2. All propagation delays are measured and specified under worst case conditions. VOLTAGE WAVEFORMS TEST LOAD CIRCUIT +3.0V 90% +5V VCC S1 10% 0V C1 tR 5ns tF C2 R1 5ns BY I0 +3.0V 90% INPUTS I7 BW 10% CL R2 DUT 0V 5ns 5ns MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. Input Pulses TIMING DEFINITIONS SYMBOL BX GND BZ OUTPUTS NOTE: C1 and C2 are to bypass VCC to GND. TIMING DIAGRAM PARAMETER +3V tPD Propagation delay between input and output. tOD Delay between input change and when output is off (Hi-Z or High). tOE I, B 1.5V 1.5V 0V VOH B 1.5V Delay between input change and when output reflects specified output level. October 22, 1993 1.5V 1.5V VT VOL tPD 13 tOD tOE Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) LOGIC PROGRAMMING PLUS153B/D PROGRAMMING AND SOFTWARE SUPPORT The PLUS153B/D is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABEL and CUPL design software packages also support the PLUS153B/D architecture. Refer to Section 9 (Development Software) and Section 10 (Third-Party Programmer/Software Support) of this data handbook for additional information. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. OUTPUT POLARITY – (B) PLUS153B/D logic designs can also be generated using the program table entry format, which is detailed on the following page. This program table entry format is supported by SNAP only. S S B B X X To implement the desired logic functions, the state of each logic variable from logic equations (I, B, O, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below. ACTIVE LEVEL CODE HIGH1 (NON–INVERTING) ACTIVE LEVEL CODE LOW H (INVERTING) L AND ARRAY – (I, B) I, B I, B I, B I, B I, B I, B I, B P, D I, B I, B I, B I, B P, D I, B P, D P, D STATE CODE STATE CODE STATE CODE STATE CODE INACTIVE1, 2 O I, B H I, B L DON’T CARE – OR ARRAY – (B) VIRGIN STATE P A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at “H” polarity. P S S 2. All Pn terms are disabled. 3. All Pn terms are active on all outputs. Pn STATUS CODE Pn STATUS ACTIVE1 A INACTIVE CODE • NOTES: 1. This is the initial unprogrammed state of all links. 2. Any gate Pn will be unconditionally inhibited if both the true and complement of an input (either I or B) are left intact. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. October 22, 1993 14 October 22, 1993 H L — I, B I, B DON’T CARE VARIABLE NAME 0 INACTIVE AND I, B(I) LOW HIGH L H B(0) (POL) A CONTROL INACTIVE ACTIVE OR Unused I and B bits in the AND array should be programmed as Don’t Care (–). Unused product terms in the OR array should be programmed as INACTIVE (o). Output polarity is non–inverting. All AND gates are pulled to a logic “0” (Low). NOTES In the unprogrammed state: CF(XXXX) PROGRAM TABLE # REV TOTAL NUMBER OF PARTS DATE CUSTOMER SYMBOLIZED PART # PHILIPS DEVICE # PURCHASE ORDER # CUSTOMER NAME Philips Semiconductors Programmable Logic Devices T E R M PIN Product specification Programmable logic arrays (18 × 42 × 10) PLUS153B/D PROGRAM TABLE POLARITY I AND B(I) 0 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 D9 31 D8 D7 D6 D5 D4 D3 D2 D1 D0 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 9 8 15 7 6 5 B(0) OR 4 3 2 1 19 18 17 16 15 14 13 12 11 0 9 9 1 0 19 18 17 16 15 14 13 12 11 9 8 7 6 5 4 3 2 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) PLUS153B/D SNAP RESOURCE SUMMARY DESIGNATIONS P31 P0 D0 D9 DIN153 I0 NIN153 I7 DIN153 B0 NIN153 B9 AND CAND TOUT153 S9 B9 X9 OR S0 B0 X0 EXOR153 October 22, 1993 16