Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (22 × 42 × 10) DESCRIPTION PLUS173B/D FEATURES The PLUS173 PLDs are high speed, combinatorial Programmable Logic Arrays. The Philips Semiconductors state-of-the-art Oxide Isolated Bipolar fabrication process is employed to produce propagation delays as short as 12ns. • I/O propagation delays (worst case) The 24-pin PLUS173 devices have a programmable AND array and a programmable OR array. Unlike PAL devices, 100% product term sharing is supported. Any of the 32 logic product terms can be connected to any or all of the 10 output OR gates. Most PAL ICs are limited to 7 AND terms per OR function; the PLUS173 devices can support up to 32 input wide OR functions. • Two programmable arrays The polarity of each output is userprogrammable as either Active-High or Active-Low, thus allowing AND-OR or AND-NOR logic implementation. This feature adds an element of design flexibility, particularly when implementing complex decoding functions. The PLUS173 devices are userprogrammable using one of several commercially available, industry standard PLD programmers. PIN CONFIGURATIONS N Package – PLUS173B – 15ns max. I0 1 24 VCC I1 2 23 B9 I2 3 22 B8 I3 4 21 B7 I4 5 20 B6 I5 6 19 B5 I6 7 18 B4 I7 8 17 B3 I8 9 16 B2 I9 10 15 B1 I10 11 14 B0 GND 12 13 I11 – PLUS173D – 12ns max. • Functional superset of 20L10 and most other 24-pin combinatorial PAL devices – Supports 32 input wide OR functions • 12 inputs • 10 bi-directional I/O • 42 AND gates – 32 logic product terms – 10 direction control terms • Programmable output polarity – Active-High or Active-Low • Security fuse • 3-State outputs • Power dissipation: 750mW (typ.) • TTL Compatible N = Plastic Dual In-Line (300mil-wide) A Package I2 I1 4 3 2 I0 VCC B9 B8 1 28 27 26 NC 5 25 NC I4 6 24 B7 I5 7 23 B6 I6 8 22 B5 I7 9 21 B4 I8 10 20 B3 NC 11 19 NC APPLICATIONS • Random logic • Code converters • Fault detectors • Function generators • Address mapping • Multiplexing I3 12 13 I9 I10 GND I11 B0 B1 B2 14 15 16 17 18 A = Plastic Leaded Chip Carrier ORDERING INFORMATION DESCRIPTION tPD (MAX) ORDER CODE DRAWING NUMBER 24-Pin Plastic Dual In-Line 300mil-wide 15ns PLUS173BN 0410D 24-Pin Plastic Dual In-Line 300mil-wide 12ns PLUS173DN 0410D 28-Pin Plastic Leaded Chip Carrier 15ns PLUS173BA 0401F 28-Pin Plastic Leaded Chip Carrier 12ns PLUS173DA 0401F PAL is a registered trademark of Advanced Micro Devices Corporation. October 22, 1993 33 853–1298 11164 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (22 × 42 × 10) PLUS173B/D LOGIC DIAGRAM (LOGIC TERMS–P) I0 1 I1 2 I2 3 I3 4 I4 5 I5 6 I6 7 I7 8 I8 9 (CONTROL TERMS) I9 10 I10 11 I11 13 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 S9 X9 X8 X7 X6 X5 X4 X3 X2 X1 31 24 23 16 15 8 7 0 NOTES: 1. All programmed ‘AND’ gate locations are pulled to logic “1”. 2. All programmed ‘OR’ gate locations are pulled to logic “0”. 3. Programmable connection. October 22, 1993 34 X0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 23 B9 S8 22 B8 S7 21 B7 S6 20 B6 S5 19 B5 S4 18 B4 S3 17 B3 S2 16 B2 S1 15 B1 S0 14 B0 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (22 × 42 × 10) PLUS173B/D FUNCTIONAL DIAGRAM P31 P0 D0 D9 I0 I11 B0 B9 S9 B9 X9 S0 B0 X0 ABSOLUTE MAXIMUM RATINGS1 THERMAL RATINGS TEMPERATURE RATING SYMBOL PARAMETER MIN MAX UNIT Maximum junction 150°C 75°C VCC Supply voltage +7 VDC Maximum ambient VIN Input voltage +5.5 VDC VOUT Output voltage +5.5 VDC Allowable thermal rise ambient to junction IIN Input currents +30 mA IOUT Output currents +100 mA Tamb Operating free-air temperature range 0 +75 °C Tstg Storage temperature range –65 +150 °C –30 NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. October 22, 1993 35 75°C Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (22 × 42 × 10) PLUS173B/D DC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V LIMITS SYMBOL Input PARAMETER TEST CONDITIONS MIN TYP1 MAX UNIT 0.8 V voltage2 VIL Low VCC = MIN VIH High VCC = MAX VIC Clamp Output 2.0 VCC = MIN, IIN = –12mA V –0.8 –1.2 V 0.5 V voltage2 VCC = MIN VOL Low4 IOL = 15mA VOH High5 IOH = –2mA 2.4 V Input current9 VCC = MAX IIL Low VIN = 0.45V –100 µA IIH High VIN = VCC 40 µA VOUT = 2.7V 80 µA VOUT = 0.45V –140 Output current VCC = MAX IO(OFF) IOS ICC Hi-Z state8 Short circuit3, 5, 6 VCC supply current7 VOUT = 0V VCC = MAX –15 150 –70 mA 200 mA Capacitance VCC = 5V IIN Input VIN = 2.0V 8 pF CB I/O VB = 2.0V 15 pF NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Measured with inputs I0 – I4 = 0V, inputs I5 – I9 = 4.5V, I11 = 4.5V and I19 = 10V. For outputs B0 – B4 and for outputs B5 – B9 apply the same conditions except I11 = 0V. 5. Same conditions as Note 4 except input I11 = +10V. 6. Duration of short circuit should not exceed 1 second. 7. ICC is measured with inputs I0 – I11 and B0 – B9 = 0V. Part in Virgin State. 8. Leakage values are a combination of input and output leakage. 9. IIL and IIH limits are for dedicated inputs only (I0 – I11). October 22, 1993 36 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (22 × 42 × 10) PLUS173B/D AC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V, R1 = 300Ω, R2 = 390Ω LIMITS SYMBOL PARAMETER FROM TO TEST PLUS173B TYP MAX TYP MAX tPD Propagation Delay2 Input +/– Output +/– CL = 30pF 11 15 10 12 ns tOE Output Enable1 Input +/– Output – CL = 30pF 11 15 10 12 ns tOD Output Disable1 Input +/– Output + CL = 5pF 11 15 10 12 ns CONDITION MIN PLUS173D MIN UNIT NOTES: 1. For 3-State outputs; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 2. All propagation delays are measured and specified under worst case conditions. VOLTAGE WAVEFORM TEST LOAD CIRCUIT +3.0V VCC 90% 10% 0V tR 5ns tF C1 +5V S1 C2 R1 BZ In 5ns +3.0V INPUTS 90% In BM CL R2 DUT 10% 0V BM 5ns 5ns MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. SYMBOL BZ OUTPUTS NOTE: C1 and C2 are to bypass VCC to GND. Input Pulses TIMING DEFINITIONS GND Test Load Circuit TIMING DIAGRAM PARAMETER +3V tPD Propagation delay between input and output. tOD Delay between input change and when output is off (Hi-Z or High). tOE I, B 1.5V 1.5V 0V VOH B 1.5V Delay between input change and when output reflects specified output level. October 22, 1993 1.5V 1.5V VT VOL tPD 37 tOD tOE Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (22 × 42 × 10) LOGIC PROGRAMMING The PLUS173 series is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABEL and CUPL design software packages also support the PLUS173 architecture. PLUS173B/D PROGRAMMING AND SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 10 (Third-Party Programmer/ Software Support) of this data handbook for additional information. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. OUTPUT POLARITY – (B) PLUS173 logic designs can also be generated using the program table entry format, which is detailed on the following page. This program table entry format is supported by SNAP only. S S B B X X To implement the desired logic functions, the state of each logic variable from logic equations (I, B, O, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below. ACTIVE LEVEL ACTIVE LEVEL CODE HIGH1 (NON-INVERTING) CODE LOW H (INVERTING) L AND ARRAY – (I, B) I, B I, B I, B I, B I, B I, B I, B P, D I, B I, B I, B I, B P, D I, B P, D P, D STATE CODE STATE CODE STATE CODE STATE CODE INACTIVE1, 2 O I, B H I, B L DON’T CARE – OR ARRAY – (B) VIRGIN STATE P A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at “H” polarity. P S S 2. All Pn terms are disabled. 3. All Pn terms are active on all outputs. Pn STATUS CODE Pn STATUS ACTIVE1 A INACTIVE CODE • NOTES: 1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates Pn, Dn. 2. Any gate Pn, Dn will be unconditionally inhibited if both the true and complement of any input (I, B) are left intact. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. October 22, 1993 38 October 22, 1993 H L — I, B I, B DON’T CARE VARIABLE NAME 0 INACTIVE AND I, B(I) LOW HIGH L H B(0) (POL) A CONTROL INACTIVE ACTIVE OR 2. Unused I and B bits in the AND array must be programmed Don’t Care (—). 3. Unused product terms can be left blank. NOTES 1. The PLA is shipped with all links intact. Thus a background of entries corresponding to states of virgin links exists in the table. (Shown BLANK for clarity.) PROGRAM TABLE # PHILIPS DEVICE # CUSTOMER NAME REV DATE Philips Semiconductors Programmable Logic Devices T E R M PIN 11 10 Product specification Programmable logic arrays (22 × 42 × 10) PLUS173B/D PROGRAM TABLE POLARITY I AND B(I) 0 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 D9 31 D8 D7 D6 D5 D4 D3 D2 D1 D0 9 8 7 6 5 4 3 2 1 0 13 11 10 9 8 7 6 5 4 3 2 1 39 9 8 7 6 5 B(0) OR 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (22 × 42 × 10) PLUS173B/D SNAP RESOURCE SUMMARY DESIGNATIONS P31 P0 D0 D9 DIN173 I0 NIN173 I11 DIN173 B0 NIN173 B9 AND CAND TOUT173 S9 B9 X9 OR S0 B0 X0 EXOR173 October 22, 1993 40