Philips Semiconductors Product specification N-channel logic level TrenchMOS transistor FEATURES SYMBOL PSMN010-55D QUICK REFERENCE DATA • ’Trench’ technology • Very low on-state resistance • Fast switching • Logic level compatible VDSS = 55 V d ID = 75 A RDS(ON) ≤ 10.5 mΩ (VGS = 10 V) g RDS(ON) ≤ 12 mΩ (VGS = 5 V) s GENERAL DESCRIPTION SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in each package at each voltage rating. Applications:• d.c. to d.c. converters • switched mode power supplies PINNING PIN SOT428 (DPAK) DESCRIPTION 1 gate 2 drain1 3 source tab 2 tab drain 1 3 The PSMN010-55D is supplied in the SOT428 (Dpak) surface mounting package. LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS VDSS VDGR VGS VGSM ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Continuous gate-source voltage Peak pulsed gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature MIN. MAX. UNIT Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ - 55 55 ± 15 V V V Tj ≤ 150 ˚C - ± 20 V - 55 752 57 240 125 175 A A A W ˚C Tmb = 25 ˚C; VGS = 5 V Tmb = 100 ˚C; VGS = 5 V Tmb = 25 ˚C Tmb = 25 ˚C 1 It is not possible to make connection to pin 2 of the SOT428 package. 2 Continuous current rating limited by package. October 1999 1 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOS transistor PSMN010-55D AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS EAS Non-repetitive avalanche energy Unclamped inductive load, IAS = 74 A; tp = 100 µs; Tj prior to avalanche = 25˚C; VDD ≤ 25 V; RGS = 50 Ω; VGS = 5 V IAS Non-repetitive avalanche current MIN. MAX. UNIT - 264 mJ - 75 A THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT428 package, pcb mounted, minimum footprint TYP. MAX. UNIT - - 1.2 K/W - 50 - K/W ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS VGS = 0 V; ID = 0.25 mA; VGS(TO) Drain-source breakdown voltage Gate threshold voltage MIN. Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C RDS(ON) IGSS IDSS Drain-source on-state resistance VGS = 10 V; ID = 25 A VGS = 5 V; ID = 25 A VGS = 4.5 V; ID = 25 A VGS = 5 V; ID = 25 A; Tj = 175˚C Gate source leakage current VGS = ±10 V; VDS = 0 V Zero gate voltage drain VDS = 25 V; VGS = 0 V; current Tj = 175˚C TYP. MAX. UNIT 55 42 1 0.5 - 1.5 7.4 8.6 9.1 0.02 0.05 - 2 2.3 10.5 12 13 25 100 10 500 V V V V V mΩ mΩ mΩ mΩ nA µA µA Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 75 A; VDD = 44 V; VGS = 5 V - 55 13 28 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 30 V; RD = 1.2 Ω; VGS = 10 V; RG = 10 Ω Resistive load - 19 114 250 216 - ns ns ns ns Ld Ls Internal drain inductance Internal source inductance Measured tab to centre of die Measured from source lead to source bond pad - 3.5 7.5 - nH nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 20 V; f = 1 MHz - 3300 560 370 - pF pF pF October 1999 2 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOS transistor PSMN010-55D REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER IS VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge ISM October 1999 CONDITIONS MIN. TYP. MAX. UNIT - - 75 A - - 240 A IF = 25 A; VGS = 0 V - 0.95 1.2 V IF = 25 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 25 V - 70 0.16 - ns µC 3 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOS transistor PSMN010-55D Normalised Power Derating, PD (%) 10 Transient thermal impedance, Zth j-mb (K/W) 100 90 80 D = 0.5 1 0.2 70 60 0.1 0.05 0.1 50 0.02 40 30 P D D = tp/T tp 0.01 single pulse 20 T 10 0.001 1E-06 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 Pulse width, tp (s) Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Drain Current, ID (A) 50 Normalised Current Derating, ID (%) 100 VGS = 10V 90 3V 5V 45 2.8 V 40 80 Tj = 25 C 35 70 2.6 V 60 30 50 25 40 20 30 15 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 2.4 V 10 2.2 V 5 2V 0 175 0 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 2 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS) Peak Pulsed Drain Current, IDM (A) 1000 0.2 0.05 RDS(on) = VDS/ ID Drain-Source On Resistance, RDS(on) (Ohms) 2.2 V 0.045 2.4 V 2.6 V Tj = 25 C 2.8 V 0.04 tp = 10 us 100 0.035 0.03 100 us 0.025 1 ms 10 0.02 D.C. 3V 0.015 10 ms 5V 0.01 100 ms VGS = 10V 0.005 1 0 1 10 100 Drain-Source Voltage, VDS (V) 1000 0 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp October 1999 5 10 15 20 25 30 Drain Current, ID (A) 35 40 45 50 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID) 4 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOS transistor Drain current, ID (A) 2.25 50 VDS > ID X RDS(ON) 45 PSMN010-55D Threshold Voltage, VGS(TO) (V) 2 maximum 1.75 40 35 1.5 30 1.25 25 typical minimum 1 20 0.75 15 175 C 0.5 10 Tj = 25 C 5 0.25 0 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 -60 -40 -20 Gate-source voltage, VGS (V) 20 40 60 80 100 120 140 160 180 Junction Temperature, Tj (C) Fig.7. Typical transfer characteristics. ID = f(VGS) 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 0 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Transconductance, gfs (S) 1.0E-01 VDS > ID X RDS(ON) Tj = 25 C Drain current, ID (A) 1.0E-02 175 C 1.0E-03 minimum typical 1.0E-04 maximum 1.0E-05 1.0E-06 0 5 10 15 20 25 30 35 Drain current, ID (A) 40 45 0 50 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID) 0.5 1 1.5 2 Gate-source voltage, VGS (V) 2.5 3 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Normalised On-state Resistance 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 10000 Capacitances, Ciss, Coss, Crss (pF) Ciss 1000 Coss Crss 100 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction temperature, Tj (C) 0.1 Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 ˚C = f(Tj) October 1999 1 10 Drain-Source Voltage, VDS (V) 100 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 5 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOS transistor 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSMN010-55D Gate-source voltage, VGS (V) Maximum Avalanche Current, IAS (A) 100 ID = 75 A Tj = 25 C 25 C VDD = 11 V 10 VDD = 44 V 0 10 20 30 40 50 60 70 Gate charge, QG (nC) 80 90 1 0.001 100 Tj prior to avalanche = 150 C 0.01 0.1 1 10 Avalanche time, tAV (ms) Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG) Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tAV); unclamped inductive load Source-Drain Diode Current, IF (A) 50 VGS = 0 V 45 40 35 30 25 20 175 C 15 Tj = 25 C 10 5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 Source-Drain Voltage, VSDS (V) Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj October 1999 6 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOS transistor PSMN010-55D MECHANICAL DATA Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads (one lead cropped) SOT428 seating plane y A E A2 A A1 b2 D1 mounting base E1 D HE L2 2 L1 L 1 3 b1 w M A b c e e1 0 10 20 mm scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 2.38 2.22 A1(1) A2 b b1 max. b2 c 0.65 0.45 0.89 0.71 0.89 0.71 1.1 0.9 5.36 5.26 0.4 0.2 D1 E D max. max. max. 6.22 5.98 4.81 4.45 6.73 6.47 E1 min. 4.0 e e1 2.285 4.57 HE max. L 10.4 9.6 2.95 2.55 L1 min. L2 w y max. 0.5 0.7 0.5 0.2 0.2 Note 1. Measured from heatsink back to lead. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ SOT428 EUROPEAN PROJECTION ISSUE DATE 98-04-07 Fig.16. SOT428 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". October 1999 7 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOS transistor PSMN010-55D MOUNTING INSTRUCTIONS Dimensions in mm 7.0 7.0 2.15 1.5 2.5 4.57 Fig.17. SOT428 : soldering pattern for surface mounting. October 1999 8 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOS transistor PSMN010-55D DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. October 1999 9 Rev 1.200