INTEGRATED CIRCUITS 74ABT16543 74ABTH16543 16-bit latched transceivers with dual enable (3-State) Product specification Supersedes data of 1995 Aug 17 IC23 Data Handbook 1998 Feb 27 Philips Semiconductors Product specification 16-bit latched transceivers with dual enable (3-State) FEATURES 74ABT16543 74ABTH16543 DESCRIPTION • Two 8-bit octal transceivers with D-type latch • Live insertion/extraction permitted • Power-up 3-State • Power-up reset • Multiple VCC and GND pins minimize switching noise • Back-to-back registers for storage • Separate controls for data flow in each direction • 74ABTH16543 incorporates bus-hold data inputs which eliminate The 74ABT16543 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT16543 16-bit registered transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable (nLEAB, nLEBA) and Output Enable (nOEAB, nOEBA) inputs are provided for each register to permit independent control of data transfer in either direction. The outputs are guaranteed to sink 64mA. Two options are available, 74ABT16543 which does not have the bus-hold feature and 74ABTH16543 which incorporates the bus-hold feature. the need for external pull-up resistors to hold unused inputs • Output capability: +64mA/–32mA • Latch-up protection exceeds 500mA per JEDEC Std 17 • ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model • See 74ABT161543 for same function with Master Reset control pins QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER TYPICAL UNIT 2.5 2.2 ns pF tPLH tPHL Propagation delay nAx to nBx CL = 50pF; VCC = 5V CIN Input capacitance VI = 0V or VCC 3 CI/O I/O capacitance VO = 0V or VCC; 3-State 7 pF 550 µA 9 mA ICCZ Quiescent su supply ly current ICCL Outputs disabled; VCC = 5.5V Outputs low; VCC = 5.5V ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 56-Pin Plastic SSOP Type III –40°C to +85°C 74ABT16543 DL BT16543 DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16543 DGG BT16543 DGG SOT364-1 56-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16543 DL BH16543 DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16543 DGG BH16543 DGG SOT364-1 PIN DESCRIPTION PIN NUMBER SYMBOL 5, 6, 8, 9, 10, 12, 13, 14 15, 16, 17, 19, 20, 21, 23, 24 1A0 – 1A7, 2A0 – 2A7 Data inputs/outputs 52, 51, 49, 48, 47, 45, 44, 43 42, 41, 40,38, 37, 36, 34, 33 1B0 – 1B7, 2B0 – 2B7 Data inputs/outputs 1, 56 28, 29 1OEAB, 1OEBA, 2OEAB, 2OEBA 3, 54 26, 31 1EAB, 1EBA, 2EAB, 2EBA 2, 55 27, 30 1LEAB, 1LEBA, 2LEAB, 2LEBA 4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V) 7, 22, 35, 50 VCC Positive supply voltage 1998 Feb 27 NAME AND FUNCTION A to B / B to A Output Enable inputs (active-Low) A to B / B to A Enable inputs (active-Low) A to B / B to A Latch Enable inputs (active-Low) 2 853-1739 19026 Philips Semiconductors Product specification 16-bit latched transceivers with dual enable (3-State) LOGIC SYMBOL (IEEE/IEC) 74ABT16543 74ABTH16543 PIN CONFIGURATION 1OEAB 1 56 1OEBA 1LEAB 2 55 1LEBA 1EAB 3 54 1EBA GND 4 53 GND 2EN4 1A0 5 52 1B0 3 G2 1A1 6 51 1B1 1LEAB 2 2C6 VCC 7 50 VCC 2OEBA 29 7EN9 1A2 8 49 1B2 2EBA 31 G7 1A3 9 48 1B3 2LEBA 30 7C11 1A4 10 47 1B4 2OEAB 28 GND 11 46 GND 2EAB 26 1A5 12 45 1B5 1A6 13 44 1B6 1A7 14 43 1B7 2A0 15 42 2B0 1OEBA 56 1EBA 54 1LEBA 55 1C5 1OEAB 1 1EAB 2LEAB 27 1EN3 G1 8EN10 G8 8C12 1A0 5 2A1 16 41 2B1 1A1 6 51 1B1 2A2 17 40 2B2 1A2 8 49 1B2 GND 18 39 GND 1A3 9 48 1B3 2A3 19 38 2B3 1A4 10 47 1B4 2A4 20 37 2B4 1A5 12 45 1B5 2A5 21 36 2B5 1A6 13 44 1B6 22 35 VCC 1A7 14 VCC 2A0 15 ∇3 5D 6D 4∇ ∇9 11D 12D 10 ∇ 52 1B0 43 1B7 2A6 23 34 2B6 42 2B0 2A7 24 33 2B7 GND 25 32 GND 2EAB 26 31 2EBA 2LEAB 27 30 2LEBA 2OEAB 28 29 2OEBA 2A1 16 41 2B1 2A2 17 40 2B2 2A3 19 2A4 20 37 2B4 2A5 21 36 2B5 2A6 23 34 2B6 2A7 24 33 2B7 38 2B3 SH00037 SH00036 1998 Feb 27 3 Philips Semiconductors Product specification 16-bit latched transceivers with dual enable (3-State) LOGIC SYMBOL 74ABT16543 74ABTH16543 FUNCTIONAL DESCRIPTION The 74ABT16543 contains two sets of eight D-type latches, with separate control pins for each set. Using data flow from A to B as an example, when the A-to-B Enable (nEAB) input and the A-to-B Latch Enable (nLEAB) input are Low the A-to-B path is transparent. 5 6 8 9 10 12 13 A subsequent Low-to-High transition of the nLEAB signal puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With EAB and nOEAB both Low, the 3-State B output buffers are active and display the data present at the outputs of the A latches. 14 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 3 1EAB 54 1EBA 1OEAB 1 2 1LEAB 1OEBA 56 55 1LEBA Control of data flow from B to A is similar, but using the nEBA, nLEBA, and nOEBA inputs. 1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 52 51 49 48 47 45 44 43 15 16 17 19 20 21 23 24 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 26 2EAB 31 2EBA 2OEAB 28 27 2LEAB 2OEBA 29 30 2LEBA 2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7 42 41 40 38 37 36 34 33 SH00038 FUNCTION TABLE INPUTS H = h = L = l = X = ↑ = NC= Z = OUTPUTS STATUS nOEXX nEXX nLEXX nAx or nBx nBx or nAx H X X X Z Disabled X H X X Z Disabled L L ↑ ↑ L L h l Z Z Disabled + Latch L L L L ↑ ↑ h l H L Latch + Display L L L L L L H L H L Transparent L L H X NC Hold High voltage level High voltage level one set-up time prior to the Low-to-High transition of nLEXX or nEXX (XX = AB or BA) Low voltage level Low voltage level one set-up time prior to the Low-to-High transition of nLEXX or nEXX (XX = AB or BA) Don’t care Low-to-High transition of nLEXX or nEXX (XX = AB or BA) No change High impedance or “off” state 1998 Feb 27 4 Philips Semiconductors Product specification 16-bit latched transceivers with dual enable (3-State) 74ABT16543 74ABTH16543 LOGIC DIAGRAM DETAIL A D nB0 Q LE nA0 Q D LE nA1 nB1 nA2 nB2 nA3 nA4 nB3 DETAIL A X 7 nB4 nA5 nB5 nA6 nB6 nA7 nB7 nOEBA nOEAB nEBA nEAB nLEBA nLEAB SH00039 ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC PARAMETER CONDITIONS RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V VO < 0 –50 mA output in Off or High state –0.5 to +5.5 V output in Low state 128 mA output in High state –64 mA –65 to 150 °C DC supply voltage IIK DC input diode current VI DC input voltage3 IOK DC output diode current voltage3 VOUT DC output IOUT O DC output current Tstg Storage temperature range VI < 0 NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Feb 27 5 Philips Semiconductors Product specification 16-bit latched transceivers with dual enable (3-State) 74ABT16543 74ABTH16543 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC LIMITS PARAMETER DC supply voltage UNIT Min Max 4.5 5.5 V 0 VCC V VI Input voltage VIH High-level input voltage VIL Low-level Input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 2.0 ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range V 64 mA 0 10 ns/V –40 +85 °C DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VIK VOH VOL VRST II IHOLD Input clamp voltage High-level output voltage Low-level output voltage Power-up output voltage3 Input leakage g current Bus Hold current A or B Ports5 74ABTH16543 Tamb = –40°C to +85°C Tamb = +25°C TYP VCC = 4.5V; IIK = –18mA MAX MIN –1.2 UNIT MAX –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 2.9 2.5 V VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.4 2.0 V VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.36 0.55 0.55 V VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V 0 01 0.01 ±1 0 ±1.0 ±1 0 ±1.0 µA 5V; VI = GND or 5 5V VCC = 5 5.5V 5.5V Control pins VCC = 4.5V; VI = 0.8V 35 35 VCC = 4.5V; VI = 2.0V –75 –75 VCC = 5.5V; VI = 0 to 5.5V ±800 µA Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V 2.0 ±100 ±100 µA Power-up/down 3-State output current4 VCC = 2.1V; VO = 0.0V or VCC; VI = GND or VCC; VOE = Don’t care 1.0 ±50 ±50 µA IIH + IOZH 3-State output High current VCC = 5.5V; VO = 5.5V; VI = VIL or VIH 1.0 10 10 µA IIL + IOZL 3-State output Low current VCC = 5.5V; VO = 0.0V; VI = VIL or VIH –1.0 –10 –10 µA Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC 1.0 50 50 µA Output current1 VCC = 5.5V; VO = 2.5V –100 –200 –200 mA IOFF IPU/PD ICEX IO –50 –50 ICCH VCC = 5.5V; Outputs High, VI = GND or VCC 0.55 2 2 mA ICCL VCC = 5.5V; Outputs Low, VI = GND or VCC 9 19 19 mA VCC = 5.5V; Outputs 3–State; VI = GND or VCC 0.55 2 2 mA Quiescent su supply ly current ICCZ ∆ICC Additional supply current per input pin2 74ABT16543 VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 5.0 50 50 µA ∆ICC Additional supply current per input pin2 74ABTH16543 VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 200 500 500 µA NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V, with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a transition time of up to 100µsec is permitted. 5. This is the bus hold overdrive current required to force the input to the opposite logic state. 1998 Feb 27 6 Philips Semiconductors Product specification 16-bit latched transceivers with dual enable (3-State) 74ABT16543 74ABTH16543 AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER +25oC Tamb = –40 to +85oC VCC = +5.0V ±0.5V Tamb = VCC = +5.0V WAVEFORM UNIT MIN TYP MAX MIN MAX 2 1.0 1.0 2.5 2.2 3.3 4.4 1.0 1.0 3.8 5.1 ns tPLH tPHL Propagation delay nAx to nBx, nBx to nAx tPLH tPHL Propagation delay LEBA to nAx, LEAB to nBx 1, 2 1.0 1.2 3.1 3.0 4.3 4.8 1.0 1.2 5.2 5.6 ns tPZH tPZL Output enable time OEBA to nAx, OEAB to nBx 4 5 1.0 1.1 3.3 3.3 4.3 5.9 1.0 1.1 5.2 7.0 ns tPHZ tPLZ Output disable time OEBA to nAx, OEAB to nBx 4 5 1.9 1.6 3.5 2.6 5.0 4.2 1.9 1.6 5.7 4.6 ns tPZH tPZL Output enable time EBA to nAx, EAB to nBx 4 5 1.0 1.2 3.4 3.4 4.9 6.5 1.0 1.2 6.2 7.8 ns tPHZ tPLZ Output disable time EBA to nAx, EAB to nBx 4 5 2.0 1.7 3.4 2.6 5.6 5.1 2.0 1.7 6.6 5.4 ns AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORM +25oC Tamb = –40 to +85oC VCC = +5.0V ±0.5V Tamb = VCC = +5.0V MIN TYP MIN UNIT ts(H) ts(L) Setup time nAx to LEAB, nBx to LEBA 3 1.5 3.5 0.4 –0.1 1.5 3.5 ns th(H) th(L) Hold time nAx to LEAB, nBx to LEBA 3 1.5 2.0 0.2 –0.3 1.5 2.0 ns ts(H) ts(L) Setup time nAx to EAB, nBx to EBA 3 1.5 3.5 0.2 –0.3 1.5 3.5 ns th(H) th(L) Hold time nAx to EAB, nBx to EBA 3 1.5 2.0 0.3 –0.2 1.5 2.0 ns tw(L) Latch enable pulse width, Low 3 4.0 3.1 4.0 ns AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V VIN VM tPHL VOUT VIN VM VOUT VM SH00040 tPHL VM VM SH00041 Waveform 1. Propagation Delay For Inverting Output 1998 Feb 27 VM tPLH tPLH VM VM Waveform 2. Propagation Delay For Non-Inverting Output 7 Philips Semiconductors Product specification 16-bit latched transceivers with dual enable (3-State) 74ABT16543 74ABTH16543 AC WAVEFORMS (Continued) VM = 1.5V, VIN = GND to 3.0V ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ nAx, nBx VM VM ts(H) VM ts(L) th(H) nLEAB, nLEBA, nEAB, nEBA VM nOEAB, nOEBA, nEAB, nEBA VM VM th(L) tw(L) VM tPZL VM nAx, nBx VM tPLZ VOL +0.3V VOL NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SH00042 SH00044 Waveform 3. Data Setup and Hold Times and Latch Enable Pulse Width nOEAB, nOEBA, nEAB, nEBA VM Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level VM tPZH tPHZ VOH VOH –0.3V VM nAx, nBx 0V SH00043 Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level TEST CIRCUIT AND WAVEFORMS VCC 7.0V PULSE GENERATOR VOUT VIN tW 90% VM NEGATIVE PULSE RL 10% 0V tTLH (tR) tTHL (tF) CL tTLH (tR) RL tTHL (tF) 90% POSITIVE PULSE Test Circuit for 3-State Outputs AMP (V) 90% VM VM 10% 10% tW SWITCH POSITION TEST SWITCH tPLZ closed tPZL closed All other open 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. AMP (V) VM 10% D.U.T. RT 90% FAMILY 74ABT/H16 Amplitude Rep. Rate tW tR tF 3.0V 1MHz 500ns 2.5ns 2.5ns SA00018 1998 Feb 27 8 Philips Semiconductors Product specification 16-bit latched transceivers with dual enable (3-State) SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm 1998 Feb 27 9 74ABT16543 74ABTH16543 SOT371-1 Philips Semiconductors Product specification 16-bit latched transceivers with dual enable (3-State) TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm 1998 Feb 27 10 74ABT16543 74ABTH16543 SOT364-1 Philips Semiconductors Product specification 16-bit latched transceivers with dual enable (3-State) NOTES 1998 Feb 27 11 74ABT16543 74ABTH16543 Philips Semiconductors Product specification 16-bit latched transceivers with dual enable (3-State) 74ABT16543 74ABTH16543 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 12 Date of release: 05-96 9397-750-03496