Philips Semiconductors Product specification 8-bit serial/parallel register with sign extend (3-State) FEATURES 74F322 PIN CONFIGURATION • Multiplexed parallel I/O ports • Separate serial input and output • Sign extend function • 3-State outputs for bus applications • Direct Overriding Clear RE 1 20 VCC S/P 2 19 S D0 3 18 SE I/O0 4 17 D1 I/O2 5 16 I/O1 DESCRIPTION I/O4 6 15 I/O3 The 74F322 is an 8-bit shift register with provision for either serial or parallel loading and with 3-State parallel outputs plus a bi-state serial output. Parallel data inputs and outputs are multiplexed to minimize pin count. State changes are initiated by the rising edge of the clock. Four synchronous modes of operation are possible: hold (store), shift right with serial entry, shift right with sign extend, and parallel load. An asynchronous Master Reset (MR) input overrides clocked operation and clears the registers. I/O6 7 14 I/O5 OE 8 13 I/O7 MR 9 12 Q7 11 CP GND 10 SF00874 The 74F322 contains eight D-type edge triggered flip-flops and the interstage gating required to perform right shift and the intrastage gating necessary for hold and synchronous parallel load operations. A Low signal on RE enables shifting or parallel loading, while a High signal enables the hold mode. A High signal on S/P enables shift right, while a Low signal disables the 3-State output buffers and enables parallel loading. In the shift right mode a High signal on SE enables serial entry from either D0 or D1, as determined by the S input. A Low signal on SE enables shift right, but Q7 reloads its contents, thus performing the sign extend function. A High signal on OE disables the 3-State output buffers, regardless of the other control inputs. In this condition the shifting and loading operations can still be performed. TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74F322 125MHz 60mA ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 20-pin plastic DIP N74F322N 20-pin plastic SOL N74F322D INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW D0, D1 Serial data inputs 1.0/1.0 20µA/0.6mA S Serial data select input 1.0/2.0 20µA/1.2mA SE Sign Extend input 1.0/3.0 20µA/1.8mA CP Clock Pulse input (Active rising edge) 1.0/1.0 20µA/0.6mA S/P Serial (High) or Parallel (Low) mode control input 1.0/1.0 20µA/0.6mA RE Register Enable input (Active Low) 1.0/1.0 20µA/0.6mA MR Asynchronous Master Reset input (Active Low) 1.0/1.0 20µA/0.6mA OE Output Enable input (Active Low) 1.0/1.0 20µA/0.6mA Q7 Bi-state serial output 50/33 1.0mA/20mA Multiplexed parallel data inputs or 3.5/1.0 70µA/0.6mA 150/40 3.0mA/24mA I/On 3-State parallel outputs NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High State and 0.6mA in the Low state. 1988 Apr 22 1 853-0366 93020 Philips Semiconductors Product specification 8-bit serial/parallel register with sign extend (3-State) LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 3 17 SRG8 9 R 8 S 19 D0 2EN15 G3 1 D1 1 RE 2 2 S/P 11 18 SE 3M1[SHIFT] 3M2[PAR LOAD] C6/1 → 18 11 CP 8 OE 19 9 MR 3 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Q7 G4 8, 4, 1, 6D G5 8, 5, 1, 6D 17 8, 4, 1, 6D 4 VCC = Pin 20 GND = Pin 10 4 74F322 16 5 15 6 14 7 13 2, 6D 7, 15 12 16 SF00875 Z7 2, 96D 8, 15 5 Z8 15 6 14 7 13 2, 6D Z14 12, 13 12 SF00876 FUNCTION TABLE INPUTS INPUTS OPERATING MODE MR RE S/P SE S OE* CP I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Q7 L L H X X H X X X X L L X X L L L L L L L L L L L L L L L L L L Clear H L L X X X ↑ I0 I1 I2 I3 I4 I5 I6 I7 I7 Parallel load H H L L H H H H L H L L ↑ ↑ D0 D1 O0 O0 O1 O1 O2 O2 O3 O3 O4 O4 O5 O5 O6 O6 O6 O6 Shift right H L H L X L ↑ O0 O0 O1 O2 O3 O4 O5 O6 O6 Sign extend H H X X X L X NC NC NC NC NC NC NC NC NC Hold X X L L X X X X Z Z Z Z Z Z Z Z NC 3-State X X X X H ↑ Z Z Z Z Z Z Z Z NC When the input is High, all I/O terminals are at the high impedance state, sequential operation or clearing of the register is not affected. High voltage level Low voltage level No change Don’t care High impedance “off” state Low-to-High clock transition The level of the steady state input at the respective I/O terminal is loaded into the flip-flop while the flip-flop outputs (except Q7) are isolated from the I/O terminal. The level of the steady state inputs to the serial multiplexer input. The level of the respective Qn flip-flop prior to the last clock Low-to-High transition. Not a Low-to-High clock transition * = H L NC X Z ↑ I0–I7 = = = = = = = D0–D7 = O0–O7 = ↑ = 1988 Apr 22 2 Philips Semiconductors Product specification 8-bit serial/parallel register with sign extend (3-State) 74F322 LOGIC DIAGRAM OE RE 8 1 S/P 2 D1 17 S D0 19 3 CP D 18 Q Q 4 Q Q 16 Q Q 5 Q Q 15 Q Q 6 Q Q 14 Q Q 7 I/O0 R SE CP D I/O1 R CP D I/O2 R CP D I/O3 R CP D I/O4 R CP D I/O5 R CP D I/O6 R 12 Q7 Q Q CP D 13 I/O7 R MR VCC = Pin 20 GND = Pin 10 1988 Apr 22 CP 9 11 SF00877 3 Philips Semiconductors Product specification 8-bit serial/parallel register with sign extend (3-State) 74F322 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT V VCC Supply voltage –0.5 to +7.0 VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state IOUT Current applied to output in Low output state Tamb Operating free-air temperature range Tstg Storage temperature –0.5 to +5.5 V Q7 40 mA I/On 48 mA 0 to +70 °C –65 to +150 °C RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNIT MIN NOM MAX 5.0 5.5 VCC Supply voltage 4.5 VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current IOL Low-level output current Tamb Operating free-air temperature range 1988 Apr 22 V Q7 –1 mA I/On –3 mA Q7 20 mA I/On 24 mA 70 °C 0 4 V Philips Semiconductors Product specification 8-bit serial/parallel register with sign extend (3-State) 74F322 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL Q7 VOH High-level output voltage I/On VOL Low-level output voltage VIK Input clamp voltage II Input current at maximum input voltage IIH High-level input current IIL Low-level input current LIMITS TEST CONDITIONS1 PARAMETER VCC = MIN, VIL = MAX, VIH = MIN VCC = MIN, VIL = MAX, VIH = MIN IOH = –1mA IOH = –3mA IOL = MAX MIN ±10%VCC 2.5 ±5%VCC 2.7 ±10%VCC 2.4 ±5%VCC 2.7 ±10%VCC ±5%VCC VCC = MIN, II = IIK TYP2 MAX UNIT V 3.4 V V 3.3 V 0.38 0.55 V 0.35 0.50 V –0.73 –1.2 V 100 µA others VCC = MAX, VI = 7.0V I/On VCC = MAX, VI = 5.5V 1 mA VCC = MAX, VI = 2.7V 20 µA –1.8 mA –1.2 mA –0.6 mA SE S VCC = MAX, VI = 0.5V others IIH + IOZH Off-state output current High-level voltage applied VCC = MAX, VI = 2.7V 70 µA IIL + IOZL Off-state output current Low-level voltage applied VCC = MAX, VI = 0.5V –0.6 mA IOS Short-circuit output current3 –150 mA 50 75 mA ICC Supply current (total) 60 90 mA 65 95 mA VCC = MAX ICCH ICCL VCC = MAX ICCZ –60 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 1988 Apr 22 5 Philips Semiconductors Product specification 8-bit serial/parallel register with sign extend (3-State) 74F322 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω PARAMETER TEST CONDITIONS MIN TYP fMAX Maximum clock frequency Waveform 1 110 125 tPLH tPHL Propagation delay CP to I/On Waveform 1 4.0 4.5 6.0 7.0 9.0 9.5 4.0 4.5 10.0 10.0 ns ns tPLH tPHL Propagation delay CP to Q7 Waveform 1 4.5 5.0 6.5 6.5 9.0 9.0 4.5 5.0 10.0 9.0 ns ns tPHL Propagation delay MR to I/On Waveform 2 5.0 6.5 9.5 4.5 10.0 ns tPHL Propagation delay MR to Q7 Waveform 2 5.0 6.5 9.5 4.5 10.0 ns tPZH tPZL Output Enable time OE to I/On Waveform 4 Waveform 5 3.0 5.5 5.0 7.5 8.0 10.5 3.0 5.0 9.0 11.0 ns ns tPHZ tPLZ Output Disable time OE to I/On Waveform 4 Waveform 5 2.0 1.0 4.0 2.5 6.5 5.5 2.0 1.0 7.5 6.0 ns ns tPZH tPZL Output Disable time S/P to I/On Waveform 4 Waveform 5 4.0 6.0 6.0 8.0 9.0 11.0 3.5 5.5 10.0 11.5 ns ns tPHZ tPLZ Output Disable time S/P to I/On Waveform 4 Waveform 5 4.0 2.0 6.0 4.0 9.0 7.0 3.5 2.0 10.5 7.5 ns ns tPZH tPZL Output Disable time RE to I/On Waveform 4 Waveform 5 8.0 9.0 9.5 11.0 12.5 14.0 7.0 8.0 14.0 16.0 ns ns tPHZ tPLZ Output Disable time RE to I/On Waveform 4 Waveform 5 6.5 4.5 8.5 6.5 11.5 9.5 5.5 4.0 13.0 10.5 ns ns 1988 Apr 22 6 MAX MIN UNIT MAX 90 MHz Philips Semiconductors Product specification 8-bit serial/parallel register with sign extend (3-State) 74F322 AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω TEST CONDITIONS MIN ts(H) ts(L) Setup time, High or Low RE to CP th(H) th(L) TYP MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX Waveform 3 8.0 12.5 9.5 14.0 ns ns Hold time, High or Low RE to CP Waveform 3 0 0 0 0 ns ns ts(H) ts(L) Setup time, High or Low D0, D1 or I/On to CP Waveform 3 4.0 4.5 6.0 5.0 ns ns th(H) th(L) Hold time, High or Low D0, D1 or I/On to CP Waveform 3 0 0 0 0 ns ns ts(H) ts(L) Setup time, High or Low SE to CP Waveform 3 5.5 5.0 7.0 5.5 ns ns th(H) th(L) Hold time, High or Low SE to CP Waveform 3 0 0 0 0 ns ns ts(H) ts(L) Setup time, High or Low S/P to CP Waveform 3 10.5 9.5 11.0 10.5 ns ns ts(H) ts(L) Setup time, High or Low S to CP Waveform 3 4.0 8.5 4.5 9.5 ns ns th(H) th(L) Hold time, High or Low S or S/P to CP Waveform 3 0 0 0 0 ns ns tw(H) tw(L) CP Pulse width, High or Low Waveform 3 5.0 5.0 5.0 5.0 ns tw(L) MR Pulse width, Low Waveform 3 5.0 5.0 ns tREC Recovery time, MR to CP Waveform 2 4.0 4.5 ns 1988 Apr 22 7 Philips Semiconductors Product specification 8-bit serial/parallel register with sign extend (3-State) 74F322 AC WAVEFORMS For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fMAX MR CP VM VM tW(H) tW(L) tW(L) tPLH tPHL Q7, I/On VM VM VM tPHL Q7, I/On VM SF00879 Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency ts(H) CP Waveform 2. Master Reset Pulse Width, Master Reset to Output Delay, and Master Reset to Clock Recovery Time RE, S/P, OE VM VM VM th(H) ts(L) VM I/On VM VM I/On VOH -0.3V VM SF00881 tPLZ VM VOL +0.3V SF00882 Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level 1988 Apr 22 tPHZ Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level VM tPZL VM 0V SF00880 VM VM tPZH th(L) Waveform 3. Data Setup and Hold Times RE, S/P, OE tREC CP SF00878 RE, D0, D1, I/On, SE, S/P, S VM VM 8 Philips Semiconductors Product specification 8-bit serial/parallel register with sign extend (3-State) 74F322 TEST CIRCUIT AND WAVEFORM VCC 7.0V VIN RL VOUT PULSE GENERATOR tw 90% NEGATIVE PULSE VM CL AMP (V) VM 10% D.U.T. RT 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V RL AMP (V) 90% 90% Test Circuit for 3-State Outputs POSITIVE PULSE VM VM 10% TEST tPLZ tPZL All other SWITCH closed closed open DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 10% tw SWITCH POSITION 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00777 1988 Apr 22 9