INTEGRATED CIRCUITS 74LVT573 3.3V Octal D-type transparent latch (3-State) Product specification Supersedes data of 1995 Nov 14 IC23 Data Handbook 1998 Feb 19 Philips Semiconductors Product specification 3.3V Octal D-type transparent latch (3-State) 74LVT573 FEATURES DESCRIPTION • Inputs and outputs on opposite side of package allow easy The LVT573 is a high-performance BiCMOS product designed for VCC operation at 3.3V. This device is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. The 74LVT573 has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. interface to microprocessors • 3-State output buffers • Common output enable • TTL input and output switching levels • Input and output interface capability to systems at 5V supply • Bus-hold data inputs eliminate the need for external pull-up The data on the D inputs are transferred to the latch outputs when the Latch Enable (E) input is High. The latch remains transparent to the data inputs while E is High, and stores the data that is present one setup time before the High-to-Low enable transition. resistors to hold unused inputs • Live insertion/extraction permitted • No bus current loading when output is tied to 5V bus • Latch-up protection exceeds 500mA per JEDEC Std 17 • Power-up 3-State • Power-up reset • ESD protection exceeds 2000V per MIL STD 883 Method 3015 The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in the High-impedance “OFF” state, which means they will neither drive nor load the bus. and 200V per Machine Model QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER tPLH tPHL Propagation delay Dn to Qn CL = 50pF; VCC = 3.3V CIN TYPICAL UNIT 2.5 2.7 ns pF Input capacitance VI = 0V or 3.0V 4 COUT Output capacitance Outputs disabled; VO = 0V or 3.0V 8 pF ICCZ Total supply current Outputs disabled; VCC = 3.6V .13 mA ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 20-Pin Plastic SOL PACKAGES –40°C to +85°C 74LVT573 D 74LVT573 D SOT163-1 20-Pin Plastic SSOP Type II –40°C to +85°C 74LVT573 DB 74LVT573 DB SOT339-1 20-Pin Plastic TSSOP Type I –40°C to +85°C 74LVT573 PW 74LVT573PW DH SOT360-1 PIN CONFIGURATION PIN DESCRIPTION PIN NUMBER SYMBOL 1 OE FUNCTION Output enable input (active-Low) OE 1 20 VCC 2, 3, 4, 5, 6, 7, 8, 9 D0-D7 Data inputs D0 2 19 Q0 Q0-Q7 Data outputs D1 3 18 Q1 19, 18, 17, 16, 15, 14, 13, 12 D2 4 17 Q2 11 E Enable input (active-High) D3 5 16 Q3 10 GND Ground (0V) D4 6 15 Q4 20 VCC Positive supply voltage D5 7 14 Q5 D6 8 13 Q6 D7 9 12 Q7 GND 10 11 E SV00031 1998 Feb 19 2 853–1750 18988 Philips Semiconductors Product specification 3.3V Octal D-type transparent latch (3-State) 74LVT573 LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 1 EN 11 C1 2 3 D0 D1 4 5 6 7 8 9 D4 D5 D6 D7 2 11 1 D2 D3 E OE 19 1D 3 18 4 17 5 16 6 15 7 14 8 13 9 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 SV00032 SV00033 FUNCTION TABLE INPUTS OUTPUTS OE E Dn INTERNAL REGISTER L L H H L H L H L H Enable and read register L L ↓ ↓ I h L H L H Latch and read register L L X NC NC H = h = L = l = NC= X = Z = ↓ = OPERATING MODE Q0 – Q7 H X X NC High voltage level High voltage level one set-up time prior to the High-to-Low E transition Low voltage level Low voltage level one set-up time prior to the High-to-Low E transition No change Don’t care High impedance “off” state High-to-Low E transition Hold Z Disable outputs LOGIC DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 D E D Q E D Q E D Q D E Q E D Q E D Q E D Q E Q 11 E 1 OE 19 Q0 18 Q1 17 16 Q2 Q3 15 Q4 14 Q5 13 Q6 12 Q7 SV00034 1998 Feb 19 3 Philips Semiconductors Product specification 3.3V Octal D-type transparent latch (3-State) 74LVT573 ABSOLUTE MAXIMUM RATINGS1, 2 PARAMETER SYMBOL VCC CONDITIONS RATING UNIT –0.5 to +4.6 V –50 mA –0.5 to +7.0 V VO < 0 –50 mA Output in Off or High state –0.5 to +7.0 V Output in Low state 128 Output in High state –64 DC supply voltage IIK DC input diode current VI DC input voltage3 IOK DC output diode current VOUT DC output voltage3 IOUT O DC output current Tstg Storage temperature range VI < 0 mA –65 to 150 °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC PARAMETER UNIT DC supply voltage MIN MAX 2.7 3.6 V 0 5.5 V VI Input voltage VIH High-level input voltage VIL Input voltage 0.8 V IOH High-level output current –32 mA Low-level output current 32 Low-level output current; current duty cycle ≤ 50%, f ≥ 1kHz 64 ∆t/∆v Input transition rise or fall rate; outputs enabled 10 ns/V Tamb Operating free-air temperature range +85 °C IOL O 1998 Feb 19 2.0 mA –40 4 V Philips Semiconductors Product specification 3.3V Octal D-type transparent latch (3-State) 74LVT573 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIK Input clamp voltage VCC = 2.7V; IIK = –18mA VCC = 2.7 to 3.6V; IOH = –100µA VOH VOL VRST High-level output voltage Low-level output voltage Power-up output low voltage5 I Input t lleakage k currentt Output off current Bus Hold current A inputs7 –1.2 VCC = 2.7V; IOH = –8mA 2.4 2.5 VCC = 3.0V; IOH = –32mA 2.0 2.2 0.1 0.2 VCC = 2.7V; IOL = 24mA 0.3 0.5 VCC = 3.0V; IOL = 16mA 0.25 0.4 VCC = 3.0V; IOL = 32mA 0.3 0.5 VCC = 3.0V; IOL = 64mA 0.4 0.55 VCC = 3.6V; IO = 1mA; VI = GND or VCC 0.13 0.55 VCC = 3.6V; VI = VCC or GND VCC = 3.6V; VI = VCC Control pins Data pins4 VCC = 0V; VI or VO = 0 to 4.5V 1 10 ±0.1 ±1 0.1 1 –1 -5 1 ±100 75 150 VCC = 3V; VI = 2.0V –75 –150 VCC = 0V to 3.6V; VCC = 3.6V ±500 UNIT V V VCC = 2.7V; IOL = 100µA VCC = 3V; VI = 0.8V IHOLD –0.9 VCC-0.1 VCC = 3.6V; VI = 0 IOFF MAX VCC-0.2 VCC = 0 or 3.6V; VI = 5.5V II TYP1 V V µA A µA µA Current into an output in the High state when VO > VCC VO = 5.5V; VCC = 3.0V 60 125 µA Power up/down 3-State output current3 VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC; OE/OE = Don’t care 1 ±100 µA IOZH 3-State output High current VCC= 3.6V; VO = 3V; VI = VIL or VIH 1 5 IOZL 3-State output Low current VCC= 3.6V; VO = 0.5V; VI = VIL or VIH –1 –5 VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0 0.13 0.19 VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0 3 12 VCC = 3.6V; Outputs Disabled; VI = GND or VCC, IO = 05 0.13 0.19 VCC = 3V to 3.6V; One input at VCC-0.6V, Other inputs at VCC or GND 0.1 0.2 IEX IPU/PD ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 µA mA mA NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND 3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 3.3V ± 0.3V a transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only 4. Unused pins at VCC or GND. 5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 6. ICCZ is measured with outputs pulled to VCC or GND. 7. This is the bus hold overdrive current required to force the input to the opposite logic state. 1998 Feb 19 5 Philips Semiconductors Product specification 3.3V Octal D-type transparent latch (3-State) 74LVT573 AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER VCC = 3.3V ± 0.3V WAVEFORM VCC = 2.7V MIN TYP1 MAX MAX UNIT tPLH tPHL Propagation delay Dn to Qn 2 1.0 1.0 2.5 2.7 4.2 4.3 4.7 5.2 ns tPLH tPHL Propagation delay E to Qn 1 1.6 2.5 3.5 4.3 5.6 6.5 6.3 7.2 ns tPZH tPZL Output enable time to High and Low level 4 5 1.0 1.3 2.8 3.3 5.1 5.5 6.2 6.6 ns tPHZ tPLZ Output disable time from High and Low level 4 5 2.0 1.5 3.7 3.0 5.7 4.6 6.7 5.1 ns VCC = 2.7V UNIT NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER VCC = 3.3V ± 0.3V WAVEFORM MIN tS(H) tS(L) Setup time, High or Low, Dn to E TH(H) TH(L) TW(H) MAX MIN 3 0.7 0.7 0.6 0.6 ns Hold time, High or Low, Dn to E 3 1.6 1.6 1.8 1.8 ns E pulse width High 1 3.3 3.3 ns AC WAVEFORMS VM = 1.5V, VIN = GND to 2.7V 2.7V E 1.5V 1.5V Dn 0V tw(H) VOH Qn 1.5V 1.5V 1.5V ts(H) tPLH tPHL ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ 2.7V 1.5V E 1.5V 1.5V th(H) 1.5V 1.5V ts(L) 0V SV00035 NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SV00118 Waveform 3. Data Setup and Hold Times 2.7V 1.5V 1.5V 0V tPLH tPHL VOH Qn 1.5V 1.5V VOL SV00117 Waveform 2. Propagation Delay for Data to Outputs 1998 Feb 19 2.7V 1.5V VOL Waveform 1. Propagation Delay, Enable to Output, and Enable Pulse Width Dn 0V th(L) 6 Philips Semiconductors Product specification 3.3V Octal D-type transparent latch (3-State) 74LVT573 2.7V 2.7V 1.5V OE 1.5V OE 0V tPZH 1.5V 0V tPHZ tPZL VOH Qn 1.5V tPLZ 3V VOH –0.3V 1.5V 1.5V Qn 0V VOL +0.3V VOL SV00119 SV00120 Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level TEST CIRCUIT AND WAVEFORM 6.0V VCC Open VIN VOUT PULSE GENERATOR RL GND tW 90% NEGATIVE PULSE 90% VM VM 10% 10% D.U.T. RT 0V CL tTHL (tF) RL tTLH (tR) tTLH (tR) tTHL (tF) 90% Test Circuit for 3-State Outputs POSITIVE PULSE AMP (V) 90% VM VM 10% 10% tW SWITCH POSITION TEST SWITCH tPLH/tPHL Open tPLZ/tPZL 6V tPHZ/tPZH GND AMP (V) 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS FAMILY RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. 74LVT Amplitude Rep. Rate 2.7V 10MHz tW tR tF 500ns 2.5ns 2.5ns RT = Termination resistance should be equal to ZOUT of pulse generators. SV00092 1998 Feb 19 7 Philips Semiconductors Product specification 3.3V Octal D-type transparent latch (3-State) 74LVT573 SO24: plastic small outline package; 24 leads; body width 7.5 mm 1998 Feb 19 8 SOT137-1 Philips Semiconductors Product specification 3.3V Octal D-type transparent latch (3-State) 74LVT573 SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm 1998 Feb 19 9 SOT340-1 Philips Semiconductors Product specification 3.3V Octal D-type transparent latch (3-State) 74LVT573 TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm 1998 Feb 19 10 SOT355-1 Philips Semiconductors Product specification 3.3V Octal D-type transparent latch (3-State) 74LVT573 NOTES 1998 Feb 19 11 Philips Semiconductors Product specification 3.3V Octal D-type transparent latch (3-State) 74LVT573 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 12 Date of release: 05-96 9397-750-03538