12-BIT 500KSPS ADC ADC1275X GENERAL DESCRIPTION FEATURES The ADC1275X is a CMOS 3.3V 12-bit analog-todigital converter (ADC). It converts the analog input signal into 12-bit binary digital codes at a maximum conversion rate of 500KSPS with 2.5MHz clock. The device is a recycling type monolithic ADC with an on-chip sample-and-hold function. The ADC has power down mode. TYPICAL APPLICATIONS • Resolution : 12-bit • Maximum Conversion Rate : 500KSPS • Main Clock : 2.5MHz • Power Supply : 3.3V ±0.3V • Total Current : 20uA (Standby Mode) 2.7mA (Normal Operation) • Input Range : 0.0V ~ 3.3V (3.3VP-P) • Differential Linearity Error : ±1.0 LSB (Max) • Integral Linearity Error : ±3.0 LSB (Max.) • Signal to Noise & Distortion Ratio : 62dB • Digital Output : CMOS Level • Operating Temperature Range : -40 °C ~ 85 °C MICOM Interface Portable Equipment Low-Voltage Low-Power Application FUNCTIONAL BLOCK DIAGRAM AINT MDAC1 STBY MAIN BIAS VREF AGND REF GEN MDAC2 FLASH1 FLASH2 CML GEN CKIN STC CLOCK GEN DIGITAL LOGIC Ver 1.3 (Apr. 2002) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this data sheet is subject to change without any notice. SAMSUNG ELECTRONICS Co. LTD DO[11:0] EOC ADC1275X 12bit 500KSPS ADC CORE PIN DESCRIPTION NAME I/O TYPE I/O PAD VREF AI phia_abb Reference Top (3.3V) AGND AI phia_abb Reference Bottom (0.0V) AVDD33A1 AP vdd3t_abb Analog Power (3.3V) AVBB33A1 AG vbb3_abb Analog Sub Bias (0.0V) AVSS33A1 AG vss3t_abb Analog Ground (0.0V) AINT AI phiar50_abb Analog Input (Input Range : 0.0V ~ 3.3V) STBY DI phicc_abb VDD=power saving (standby), GND=normal CKIN DI phicc_abb Sampling Clock Input D[11:0] DO phot4_abb Digital Output EOC DO phot4_abb End of Conversion Signal STC DI phicc_bb AVSS33A2 DG vss3t_abb Digital GND (0.0V) AVDD33A2 DP vdd3t_abb Digital Power (3.3V) I/O TYPE ABBR. PIN DESCRIPTION • • • • AI : Analog Input DI : Digital Input AO : Analog Output DO : Analog Output • • • • AP AG DP DG : : : : Analog Power Analog Ground Digital Power Digital Ground • AB : Analog Bidirection • DB : Digital Bidirection Start of Conversion Signal avss33a1 avdd33a2 avdd33a1 avbb33a1 avss33a2 AINT adc1275x [MSB:LSB] DO[11:0] EOC VREF AGND STBY CKIN SEC ASIC 2/11 STC MIXED ADC1275X 12bit 500KSPS ADC ABSOLUTE MAXIMUM RATINGS Characteristics Value Symbol Unit Supply Voltage VDD 3.8 V Analog Input Voltage AINT VSS to VDD V Digital Input Voltage CKIN VSS to VDD V VREF / AGND VSS to VDD V Reference Voltage Storage Temperature Range Tstg -45 to 150 °C Operating Temperature Range Topr -40 to 85 °C NOTES 1. Absolute maximum rating specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5kΩ resistor (Human body model) RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Typ Max Unit 3.0 3.3 3.6 V VREF 2.0 3.3 3.6 AGND 0.0 0.0 0.0 Analog Input Voltage AINT 0.0 VREF - V Operating Temperature Toper -40 - 85 °C AVDD33A1 Supply Voltage AVDD33A2 Reference Input Voltage V NOTES It is strongly recommended that all the supply pins (AVDD33A1, AVDD33A2) be powered from the same source to avoid power latch-up. DC ELECTRICAL CHARACTERISTICS Characteristics Differential Nonlinearity Integral Symbol Min Typ Max Unit DNL - ±0.8 ±1 LSB INL - ±1.8 ±3 LSB OFF - 10 16 LSB Nonlinearity Offset Voltage Test Condition VREF=3.3V AGND=0.0V VREF=3.3V AGND=0.0V VREF=3.3V AGND=0.0V (Converter Specifications : AVDD33A1=AVDD33A2=3.3V, AVSS33A1=AVSS33A2=0V, Toper=25 °C, VREF=3.3V, AGND=0.0V unless otherwise specified) SEC ASIC 3/11 MIXED ADC1275X 12bit 500KSPS ADC AC ELECTRICAL CHARACTERISTICS Characteristics Maximum Conversion Rate Standby Supply Symbol Min Typ Max Unit Test Condition fc - - 500 KSPS fCKIN = 2.5MHz - 20 40 uA STBY = VDD Current Dynamic Supply Current IVDD - 2.3 3 mA Reference Current Total Harmonic IREF - 0.4 0.6 mA THD - -70 -66 dB SNDR 60 62 - dB Distortion Signal-to-Noise & Distortion Ratio fCKIN=2.5MHz (without system load) VREF = 3.3V fCKIN = 2.5MHz AINT=100kHz fCKIN = 2.5MHz AINT=100kHz (Converter Specifications : AVDD33A1=AVDD33A2=3.3V, AVSS33A1=AVSS33A2=0V, Toper=25 °C, VREF=3.3V, AGND=0.0V unless otherwise specified) I/O CHART Index AINT Input (V) Digital Output 0 ~ 0.00081 0000 0000 0000 1 0.00081 ~ 0.00161 0000 0000 0001 2 0.00161 ~ 0.00242 0000 0000 0010 ~ ~ ~ 2047 1.64919 ~ 1.65000 0111 1111 1111 2048 1.65000 ~ 1.65081 1000 0000 0000 2049 1.65081 ~ 1.65161 1000 0000 0001 ~ ~ ~ 4093 3.29758 ~ 3.29839 1111 1111 1101 4094 3.29839 ~ 3.29919 1111 1111 1110 4095 3.29919 ~ 1111 1111 1111 SEC ASIC 4/11 1LSB=0.806mV VREF=3.3V AGND=0.0V MIXED ADC1275X 12bit 500KSPS ADC TIMING DIAGRAM 1. Main Waveform A2 A1 AINT Input Sampling Period CKIN 1 2 3 4 5 STBY STC EOC DO[11:0] 2. STC & CKIN Condition CKIN 10ns TSAFE 3ns STC The A/D Converter operates data conversion when STC (Start Conversion) signal is just "HIGH". Otherwise, output data (DO[11:0]) keep the current states. The STC signal should be changed during "TSAFE" with the "HIGH" level of the clock to operation as shown in the main waveform. • ADC External Interface Signal AINT : Analog Input Signal (Input) Input Range : VREF ~ AGND STBY : Stand-by Signal, Power Save Mode (Input) CKIN : ADC Main Clock, fCKIN = 2.5MHz, 1 Clock Period = 400ns (Input) STC : Start of Conversion Signal (Input) EOC : End of Conversion Signal (Output) DO[11:0] : Digital Output Signal (Output) SEC ASIC 5/11 MIXED ADC1275X 12bit 500KSPS ADC CORE EVALUATION GUIDE 1. ADC function is evaluated by external check on the bidirectional pads connected to input nodes of HOST DSP back-end circuit. 2. The reference voltages may be biased internally through resistor divider. avss33a1 avdd33a2 avdd33a1 avbb33a1 avss33a2 AINT [MSB:LSB] DO[11:0] adc1275x EOC VREF AGND STBY CKIN STC D[11:0] D[11:0] Digital Mux HOST DSP CORE D[11:0] Bidirectional PAD (ADC Function Test & externally forced Digital Input) SEC ASIC 6/11 MIXED ADC1275X 12bit 500KSPS ADC PACKAGE CONFIGURATION NOTES 1. NC denotes "No Connection". Digital I 10u 10u 0.1u 10u 0.1u 10u 0.1u Analog Digital II 1 VREF AVDD33A2 48 2 VREF AVDD33A2 47 3 AGND AVSS33A2 46 4 AGND AVDD33A2 45 5 NC NC 44 6 AVDD33A1 NC 43 7 AVDD33A1 STC 42 8 AVBB33A1 EOC 41 9 AVSS33A1 NC 40 10 AVSS33A1 NC 39 11 AINT 12 NC 13 NC DO[9] 36 14 NC DO[8] 35 15 NC DO[7] 34 16 NC DO[6] 33 17 STBY DO[5] 32 18 VDDR DO[4] 31 19 VSSR DO[3] 30 20 CKIN DO[2] 29 21 NC DO[1] 28 22 NC DO[0] 27 23 NC NC 26 24 RP RN 25 0.1u 10u SEC ASIC 0.1u 0.1u 10u DO[11] 38 adc1275x 7/11 DO[10] 37 MIXED ADC1275X 12bit 500KSPS ADC PACKAGE PIN DESCRIPTION I/O No. NAME 1,2 VREF AI Reference Voltage (3.3V) 3,4 AGND AI 6, 7 AVDD33A1 8 TYPE PIN DESCRIPTION CONFIGURATION VREF 1 48 VDDD Analog Ground (0.0V) VREF 2 47 VDDD AP Analog Power (3.3V) AGND 3 46 VSSD AVBB33A1 AG Analog Sub Bias AGND 4 45 VSSD NC 5 44 NC 9, 10 AVSS33A1 AG Analog Ground VDDA 6 43 NC 11 AINT AI Analog Input VDDA 7 42 STC VBBA 8 41 EOC VSSA 9 40 NC VSSA 10 39 NC AINT 11 38 DO[11] NC 12 37 DO[10] NC 13 36 DO[9] NC 14 35 DO[8] 17 STBY DI VDD=Power saving (Standby), GND=Normal 18 VDDR PP PAD Power (3.3V) 19 VSSR PG PAD Ground 20 CKIN DI Clock Input (fCKIN = 2.5MHz) 24 RP AO Test Pin1 NC 15 34 DO[7] 25 RN AO Test Pin2 NC 16 33 DO[6] 27 DO[0] DO Digital Output (LSB) STBY 17 32 DO[5] VDDR 18 31 DO[4] 28~37 DO[1:10] DO Digital Output VSSR 19 30 DO[3] CKIN 20 29 DO[2] NC 21 28 DO[1] NC 22 27 DO[0] RP 23 26 NC RN 24 25 NC 38 DO[11] DO Digital Output (MSB) 41 EOC DO End of Conversion Signal 42 STC DI Start of Conversion Signal 45, 46 AVSS33A2 DG Digital GND 47, 48 AVSS33A2 DP Digital Power (3.3V) adc1275x NOTES 1. I/O TYPE PP and PG denote PAD Power and PAD Ground respectively. SEC ASIC 8/11 MIXED ADC1275X 12bit 500KSPS ADC USER GUIDE 1. Input Range - The analog input is single-ended type and the range is from VREF to AGND. This AINT voltage follows reference voltage range fundamentally. So, if you want to alter into the another input range, you should change the voltage value of VREF. - You can use the AINT voltage whose minimum range is 2.0V. In this case, the VREF is 2.0V. SEC ASIC 9/11 MIXED ADC1275X 12bit 500KSPS ADC PHANTOM CELL INFORMATION STC CKIN EOC AVDD33A2 AVBB33A1 AVSS33A2 DO[0] DO[1] DO[2] DO[3] DO[4] DO[5] DO[6] DO[7] DO[8] DO[9] DO[10] DO[11] STBY VREF AGND adc1275x AVSS33A1 AVBB33A1 AVDD33A1 AINT NAME I/O TYPE Pin Usage AINT AI Internal/External STBY DI Internal/External CKIN DI Internal/External D[11:0] DO Internal/External EOC DO Internal/External STC DI Internal/External VREF AI External AGND AI External AVDD33A1 AP External AVBB33A1 AG External AVSS33A1 AG External AVSS33A2 DG External AVDD33A2 DP External SEC ASIC PIN DESCRIPTION AINT signal should not be crossed by any signals and should not run next to digital signals to minimize capacitive coupling between the two signals. Digital Input Signal lines must have same length to reduce propagation delay. Voltage reference lines (VREF and AGND) must be wide metal to reduce voltage drop of metal lines. 1. It is recommended that you use thick analog power metal. When connected to PAD, the path should be kept as short as possible. 2. Digital power and analog power are separately used. 10/11 MIXED ADC1275X 12bit 500KSPS ADC FEEDBACK REQUEST ADC Specification Parameter Min Typ Max Unit Supply voltage V Reference Input voltage V Analog Input voltage Vpp Operating temperature °C Integral non-linearity error LSB Differential non-linearity error LSB Offset voltage error (Bottom) mV Offset voltage error (Top) mV Maximum conversion rate MSPS Dynamic supply current mA Power dissipation mW Signal-to-noise ratio dB Remarks Digital output format (Provide detailed description & timing diagram) • What do you want to choose as power supply voltages? For example, the analog VDD needs to be 5V. the digital VDD can be 3.3V/5V. • What resolution do you need for ADC? • How about conversion speed (data in → data out)? • How many cycles do exist during the latency of ADC (pipelined delay)? • What's the input range? And then what do you need between single input and differential input? • Can the bus interface be compatible with TTL? • Could you explain external/internal pin configurations as required? Specially requested function list : SEC ASIC 11/11 MIXED ADC1275X 12bit 500KSPS ADC HISTORY CARD Version Modified Items Date ver 1.0 Comments Original version published (preliminary) ver 1.1 ver 1.2 2001.02 Release the formal datasheet ver 1.3 02.04.27 Add the pin information to the phantom cell information Temperature range is modified SEC ASIC MIXED