12BIT 20MSPS ADC ADC1256X GENERAL DESCRIPTION FEATURES The ADC1256X is a CMOS 12bit analog-to-digital Resolution : 12bit Maximum Conversion Rate : 20MHz Package Type : 48TSSOP Power Supply : 2.5V Power Consumption : 115mW (typical) Reference Voltage : 1.75V, 0.75V (dual reference) Input Range : ±1V (differential) Differential Linearity Error : ±1.0 LSB (Max) Integral Linearity Error : ±3.0 LSB (Max) Signal to Noise & Distortion Ratio : 62dB (Typ.) Digital Output : CMOS Level Operating Temperature Range : 0ºC ~ 70ºC converter (ADC). into 12bit It converts the analog input signal binary digital codes at a maximum sampling rate of 20MHz. The device is a monolithic ADC with an on-chip, high-performance, sample-and-hold Amplifier (SHA) and current reference. The structure allows both differential and single-ended input. TYPICAL APPLICATIONS High Definition TV (HDTV) Video Applications CCD Imaging (Copiers, Scanners, Cameras) Medical Imaging Digital Communications FUNCTIONAL BLOCK DIAGRAM VDD25A1 AINT SHA AINC REFTOP1 REFTOP VSS25A1 VBBA1 VDD25A2 MDAC1 GAIN=8 MDAC2 GAIN=8 4 4 FLASH 1 FLASH 2 VBBA2 MDAC3 GAIN=8 4 FLASH 3 4 4 VSS25A2 DO[11:0] FLASH 4 4 [MSB:LSB] 4 REFBOT 12 DIGITAL CORRECTION LOGIC REFBOT1 Common Mode MAIN Clock Level Generator BIAS Generator CML SPEEDUP ITEST STBY CKIN Ver 1.1 (February. 2000) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice. SAMSUNG ELECTRONICS Co. LTD ADC1256X 12BIT 20MSPS ADC CORE PIN DESCRIPTION NAME I/O TYPE I/O PAD PIN DESCRIPTION REFTOP1 AI piar50_abb Reference Top Sense (1.75V) REFTOP AI pia_abb Reference Top Force (1.75V) REFBOT AI pia_abb Reference Bottom Force (0.75V) REFBOT1 AI piar50_abb Reference Bottom Sense (0.75V) CML AB pia_abb Common Mode Level (Test Pin) VDD25A1 AP vdd2t_abb VBBA1 AG vbb_abb Analog Sub Bias VSS25A1 AG vss2t_abb Analog Ground AINT AI piar50_abb Analog Input + (Input Range : 0.75V ~ 1.75V) AINC AI piar50_abb Analog Input (Input Range : 0.75V ~ 1.75V) SPEEDUP DI picc_abb VDD=Speed up, Normal ( ≤20MHz) GND=Speed down ( ≤15MHz) ITEST AB pia_abb open=use internal bias point STBY DI picc_abb VDD=power saving (standby), GND=normal CKIN DI picc_abb Sampling Clock Input D[11:0] DO poa_abb Digital Output VBBA2 DG vbb_abb Digital Sub Bias VSS25A2 DG vss2t_abb Digital GND VDD25A2 DP vdd2t_abb Digital Power (2.5V) I/O TYPE ABBR. AI : Analog Input DI : Digital Input AO : Analog Output DO : Analog Output Analog Power (2.5V) VDD25A1 VSS25A1 VBBA1 VDD25A2 AP AG DP DG : : : : Analog Power Analog Ground Digital Power Digital Ground AB : Analog Bidirection DB : Digital Bidirection VSS25A2 VBBA2 AINT AINC adc1256x DO[11:0] [MSB:LSB] REFTOP1 REFTOP REFBOT REFBOT1 CML SEC ASIC SPEEDUP 2/12 ITEST STBY CKIN ANALOG ADC1256X 12BIT 20MSPS ADC ABSOLUTE MAXIMUM RATINGS Characteristics Symbol Supply Voltage Value VDD Unit 3.3 V Analog Input Voltage AINT/AINC VSS to VDD V Digital Input Voltage CLK VSS to VDD V REFTOP/REFBOT/ REFTOP1/REFBOT1 VSS to VDD V Reference Voltage Storage Temperature Range Tstg -40 to 125 ºC Operating Temperature Range Topr 0 to 70 ºC NOTES 1. Absolute maximum rating specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5Kohm resistor (Human body model) RECOMENDED OPERATING CONDITIONS Characteristics Symbol Min Typ Max Unit 2.3 2.5 2.7 V VDD25A1 Supply Voltage VDD25A2 VDD25A3 Reference Input Voltage Analog Input Voltage Operating Temperature REFTOP 1.75 REFBOT 0.75 AINT ±1 AINC (differential) Toper 0 - V V 70 ºC NOTES It is strongly recommended that all the supply pins (VDD25A1, VDD25A2, VDD25A3) be powered from the same source to avoid power latch-up. SEC ASIC 3/12 ANALOG ADC1256X 12BIT 20MSPS ADC DC ELECTRICAL CHARACTERISTICS Characteristics Differential Nonlinearity Integral Nonlinearity Offset Voltage Symbol Min DNL - INL OFF Typ Max Unit ±0.8 ±1 LSB - ±1.2 ±3 LSB - 10 15 Test Condition REFTOP=1.75V REFBOT=0.75V REFTOP=1.75V REFBOT=0.75V REFTOP=1.75V mV REFBOT=0.75V (Converter Specifications : VDD25A1=VDD25A2=VDD25A3=2.5V, VSS25A1=VSS25A2=VSS25A3=0V, Toper=25ºC, REFTOP=1.75V, REFBOT=0.75V unless otherwise specified) AC ELECTRICAL CHARACTERISTICS Characteristics Maximum Conversion Rate Dynamic Supply Current Signal-to-Noise & Distortion Ratio Symbol Min Typ Max Unit Test Condition fc - - 20 MHz AIN=AINT-AINC IVDD - 46 60 mA SNDR 56 62 - dB fc=20MHz (without system load) AIN=1MHz (Conversion Specifications : VDD25A1=VDD25A2=VDD25A3=2.5V, VSS25A1=VSS25A2=VSS25A3=0V, Toper=25ºC, REFTOP=1.75V, REFBOT=0.75V unless otherwise specified) SEC ASIC 4/12 ANALOG ADC1256X 12BIT 20MSPS ADC I/O CHART Index AINT Input (V) AINC Input (v) Digital Output 0 0.2500 ~ 0.2505 1.25 0000 0000 0000 1 0.2505 ~ 0.2510 1.25 0000 0000 0001 2 0.2510 ~ 0.2515 1.25 0000 0000 0010 ~ ~ ~ ~ 2047 1.2495 ~ 1.2500 1.25 0111 1111 1111 2048 1.2500 ~ 1.2505 1.25 1000 0000 0000 2049 1.2505 ~ 1.2510 1.25 1000 0000 0001 ~ ~ ~ ~ 4093 2.2485 ~ 2.2490 1.25 1111 1111 1101 4094 2.2490 ~ 2.2495 1.25 1111 1111 1110 4095 2.2495 ~ 2.2500 1.25 1111 1111 1111 SEC ASIC 5/12 1LSB=0.488mV REFTOP=1.75V REFBOT=0.75V ANALOG ADC1256X 12BIT 20MSPS ADC TIMING DIAGRAM A1 AINT A2 A5 CKIN Input sampling period DO[11:0] D1 SEC ASIC D2 D3 6/12 D4 D5 ANALOG ADC1256X 12BIT 20MSPS ADC input block is designed to be the rail-to-rail architecture using complementary different pair. FUNCTIONAL DESCRIPTION 1. The ADC1256X is a CMOS four step pipelined Analog-to-Digital Converter. It contains four 4-bit flash A/D Converters and three multiplying D/A Conveters. The 4-bit flash ADC is composed of 24-1 latching comparators, and multiplying DAC is composed of 2×(24+1) capacitors and two fully-differential amplifiers. 2. The ADC1256X operates as follows. During the first "L" cycle of external clock the analog input data is sampled, and the input is held from the rising edge of the external clock, which is fed to the first 4-bit flash ADC, and the first multiplying DAC. Multiplying DAC reconstructs a voltage corresponding to the first 4-bit ADC's output, and finally amplifies a residue voltage by 23. The second and third 4-bit flash ADC, and MDAC are worked as same manner. Finally amplified residue voltage at the third multiplying DAC is fed to the last 4-bit flash ADC decides final 4-bit digital code. 2. FLASH The 4-bit flash converters compare analog signal (TAH output) with reference voltage, and that results transfer to MDAC and digital correction logic block. It is realized fully differential comparators of 15EA. Considering self-offset, dynamic feed through error, it should distinguish 40mV at least. First, the comparators charge the reference voltage at the sampling capacitors before transferred SHA output.That operation is performed on the phase of Q2, and discharging on the phase of Q1. That is, the comparators compare relative different values dual input voltage with dual reference voltage. Its output during Q1 operation is stored at the pre-latch block by Q1P. 3. MDAC 3. ADC1256X has the error correction scheme, which handles the output from mismatch in the first, second, third and fourth flash ADC. MAIN BLOCK DESCRIPTION 1. SHA MDAC is the most important block at this ADC and it decides the characteristics. MDAC is consist of two stage op amp, selection logic and capacitor array (c_array). c_array's compositions are the capacitors to charge the analog input and and the reference voltage, switches to control the path. Selection logic controls the c_array internal switches . If Q1 is high, selection's output are all low, the switches of tsw1 are off, the switches of tsw2 are all on. Therefore the capacitors of c_array can charge analog input values held at SHA. SHA (Sample-and-Hold Amplifier) is the circuit that samples the analog input signal and hold that value until next sample-time. It is good as small as its different value between analog input signal and output signal. SHA amp gain is higher than 70dB at 20MHz conversion rate, its settling-time must be shorten than 18ns with less than 1/2 LSB error voltage at 12bit resolution. This SHA is consist of fully differential op amp, switching tr. and sampling capacitor. The sampling clock is non-overlapping clock (Q1, Q2) and sampling capacitor value is about 3.0pF. SHA uses independent bias to protect interruption of any other circuit. SHA amp is designed that open-loop dc gain is higher than 70dB, phase margin is higher than 60 degrees. Its SEC ASIC 7/12 ANALOG ADC1256X 12BIT 20MSPS ADC CORE EVALUATION GUIDE 1. ADC function is evaluated by external check on the bidirectional pads connected to input nodes of HOST DSP back-end circuit. 2. The reference voltages may be biased internally through resistor divider. VDD25A1 VSS25A1 VBBA1 VDD25A2 VSS25A2 VBBA2 AINT AINC DO[11:0] [MSB:LSB] adc1256x REFTOP1 REFTOP REFBOT REFBOT1 CML SPEEDUP ITEST STBY CKIN vdd D[11:0] D[11:0] Digital Mux HOST DSP CORE D[11:0] Bidirectional PAD (ADC Function Test & externally forced Digital Input) SEC ASIC 8/12 ANALOG ADC1256X 12BIT 20MSPS ADC PACKAGE CONFIGURATION NOTES 1. NC denotes "No Connection". Digital I 10u 0.1u 10u 0.1u 10u 0.1u 10u 10u 0.1u 0.1u Analog Digital II 10u 0.1u 50ohm SEC ASIC 1 REFTOP1 VDD25A2 48 2 REFTOP VDD25A2 47 3 REFBOT VSS25A2 46 4 REFBOT1 VSS25A2 45 5 CML VBBA2 44 6 VDD25A1 NC 43 7 VDD25A1 NC 42 8 VBBA1 NC 41 9 VSS25A1 NC 40 10 VSS25A1 NC 39 11 AINT DO[11] 38 12 NC DO[10] 37 13 AINC DO[9] 36 14 NC DO[8] 35 15 SPEEDUP DO[7] 34 16 ITEST DO[6] 33 17 STBY DO[5] 32 18 VDD25A3 DO[4] 31 19 VSS25A3 DO[3] 30 20 CKIN DO[2] 29 21 TEST1 DO[1] 28 22 TEST2 DO[0] 27 26 25 ADC1256X 23 NC NC 24 NC TRIST 9/12 0.1u 10u ANALOG ADC1256X 12BIT 20MSPS ADC PACKAGE PIN DESCRIPTION I/O No. NAME 1 2 REFTOP1 REFTOP AI AI Reference Top Sence (1.75V) Reference Top Force (1.75V) 3 4 REFBOT REFBOT1 AI AI Reference bottom Force (0.75V) Reference bottom Sense (0.75V) 5 CML AB Common Mode Level (Test Pin) 6, 7 8 VDD25A1 VBBA1 AP AG Analog Power (2.5V) Analog Sub Bias 9, 10 11 VSS25A1 AINT AG AI Analog Ground Analog Input + 13 AINC AI Analog Input - TYPE PIN DESCRIPTION 15 SPEEDUP DI VDD=Normal (≤20MHz) GND=Speed Down (≤15MHz) 16 ITEST AB open=use internal bias circuit 17 STBY DI 18 VDD25A3 PP PAD Power (2.5V) 19 20 VSS25A3 CKIN PG DI PAD Ground Sampling Clock Input 21 22 TEST1 TEST2 AO AO VDD=Power saving (Standby), GND=Normal Monitoring (TEST) Cell Pin1, TRIST DI REFTOP1 1 48 VDD25A2 REFTOP 2 47 VDD25A2 REFBOT 3 46 VSS25A2 REFBOT1 4 45 VSS25A2 CML 5 44 VBBA2 VDD25A1 6 43 NC VDD25A1 7 42 NC VBBA1 8 41 NC VSS25A1 9 40 NC VSS25A1 10 39 NC AINT 11 38 DO[11] NC 12 37 DO[10] AINC 13 36 DO[9] NC 14 35 DO[8] SPEEDUP 15 34 DO[7] ITEST 16 33 DO[6] STBY 17 32 DO[5] VDD25A3 18 31 DO[4] VSS25A3 19 30 DO[3] CKIN 20 29 DO[2] ADC1256X GND=Normal Monitoring (TEST) Cell Pin2, GND=Normal Tristate Buffer Input 25 CONFIGURATION VDD=High Impedance, GND=Normal 27 DO[0] DO Digital Output (LSB) TEST1 21 28 DO[1] 28~37 38 DO[1:10] DO[11] DO DO Digital Output Digital Output (MSB) TEST2 22 27 DO[0] NC 23 26 NC 44 VBBA2 45, 46 VSS25A2 47, 48 VDD25A2 DG DG DP Digital Sub Bias Digital GND Digital Power (2.5V) NC 24 25 TRIST NOTES 1. I/O TYPE PP and PG denote PAD Power and PAD Ground respectively SEC ASIC 10/12 ANALOG ADC1256X 12BIT 20MSPS ADC USER GUIDE 1. Input Range - If you want to using the single-ended input, you should use he input range as below. AINT : 0.25V ~ 2.25V, AINC : 1.25V. - If you want to using the differential input, you should use the input range as below. AINT : 0.75V ~ 1.25V, AINC : 0.75V ~ 1.25V. AIN : AINT-AINC 2. Speed Up The initial target speed of ADC1256X is 20MHz. If you want speed down (about 15MHz), you should connect the SPEEDUP port to 'LOW'. And it can save the total power consumption about 10 ~ 15%. 3. Power Consumption Optimization Yon can optimize the power consumption, as control the ITEST voltage level precisely . SEC ASIC 11/12 ANALOG ADC1256X 12BIT 20MSPS ADC FEEDBACK REQUEST ADC Specification Parameter Min Typ Max Unit Supply voltage V Reference Input voltage V Analog Input voltage Vpp Operating temperature ºC Integral non-linearity error LSB Differential non-linearity error LSB Offset voltage error Remarks mV (Bottom) Offset voltage error mV (Top) Maximum conversion rate MSPS Dynamic supply current mA Power dissipation mW Signal-to-noise ratio dB Digital output format (Provide detailed description & timing diagram) - What do you want to choose as power supply voltages? - What resolution do you need for ADC? - How about conversion speed(data in→ data out)? - How many cycles do exist during the latency of ADC (pipelined delay)? - What's the input range? And then what do you need between single input and differential input? - Could you explain external/internal pin configurations as required? Specially requested function list : SEC ASIC 12/12 ANALOG