10-BIT 250KSPS SAR ADC ADC1255X FEATURES GENERAL DESCRIPTION The ADC1255X is a CMOS 10-bit low supply, low power, successive approximation A/D converter which is composed of auto-zeroing comparator, 10-bit DAC, clock generator, successive approximation register(SAR) and output register. The 10-bit DAC consists of capacitor arrays and resistor strings. The conversion result can be accessed over a parallel interface. The ADC1255X operates with a single +1.8V power supply and the conversion rate is up to 250KSPS. ·Resolution: 10-Bit ·Differential Linearity Error:±1.0 LSB(Max) ·Integral Linearity Error:±2.0 LSB(Typ) ·Maximum Conversion Rate: 250KSPS ·Low Power Consumption: 2.2mW(Typ) ·Power Supply Voltage: 1.8V(Typ) ·No Pipeline Delays ·No Missing Code Guaranteed ·Operation Temperature Range: 0ºC~70ºC FUNCTIONAL BLOCK DIAGRAM VDD18A1 VSS18A1 VBBA1 REFT VCOM REFB VDD18A2 VSS18A2 VBBA2 VDD18A3 VSS18A3 INP 10(12)-Bit DAC COMP INN CONV BUSY SAR CONTROLLER CLK SLEEP OUT_REG DO[11:0] Ver 1.1 (Jan., 2000) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this data sheet is subject to change without any notice. SEC ASIC 1/13 ANALOG 10-BIT 250KSPS SAR ADC ADC1255X CORE PIN DESCRIPTION NAME I/O TYPE I/O PAD REFT AI pia_abb Reference Top Voltage VCOM AI pia_abb Analog Common Voltage; Reference Middle Voltage REFB AI pia_abb Reference Bottom Voltage VDD18A1 AP vdd1t_abb VBBA1 AG vbb_abb Analog Bulk VSS18A1 AG vss1t_abb Analog Ground INP AI piar10_abb Analog Input(+) INN AI piar10_abb Analog Input(-) ITEST AB pia_abb Current Bias Test SLEEP DI picc_abb SLEEP; Power Saving Mode (Active High) CLK DI picc_abb Master Clock Input DO[11:2] DO poa_abb Digital Output Data DO[1:0] DO poa_abb Extra Digital Output Data BUSY DO poa_abb No Sleep Mode; BUSY = "HIGH" CONV DI picc_abb Conversion Control Pin (Active High) VSS18A2 DG vss1t_abb Digital Ground VBBA2 DG vbb_abb Digital Bulk VDD18A2 DP vdd1t_abb Digital Power VSS18A3 DG vss1t_abb Output Buffer Ground VDD18A3 DP vdd1t_abb Output Buffer Power CORE CONFIGURATION PIN DESCRIPTION Analog Power I/O TYPE ABBR. · · · · · · · · AI : Analog Input DI : Digital Input AO : Analog Output DO : Digital Output AP : Analog Power AG : Analog Ground DP : Digital Power DG : Digital Ground · AB : Analog Bidirection · DB : Digital Bidirection VDD18A1VSS18A1VBBA1 VDD18A2VSS18A2VBBA2 VDD18A3 VSS18A3 INP INN adc1255x DO[11:0] REFT VCOM REFB ITEST SLEEP CLK BUSY CONV SEC ASIC 2/13 MIXED 10-BIT 250KSPS SAR ADC ADC1255X ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Value Unit Supply Voltage VDD 3.3 V Analog Input Voltage AIN VSS to VDD V Digital Input Voltage DIN VSS to VDD V VOH, VOL VSS to VDD V REFT/REFB VSS to VDD V Digital Output Voltage Reference Voltage Storage Temperature Range Tstg -45 to 150 ºC Operating Temperature Range Topr 0 to 70 ºC NOTES 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5kΩ resistor (Human body model) RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Typ Max Unit 1.7 1.8 - V - V VDD18A1 Supply Voltage VDD18A2 VDD18A3 Reference Input Voltage Analog Input Voltage Operating Temperature REFT - REFB INP 0.0 INN 1.35 0.45 - 1.8 0.9 Toper 0 - 70 V ºC NOTES It is strongly recommended that all the supply pins (VDD18A1, VDD18A2, VDD18A3) be powered from the same source to avoid power latch-up. SEC ASIC 3/13 MIXED 10-BIT 250KSPS SAR ADC ADC1255X ANALOG SPECIFICATIONS Characteristics Symbol Min Typ Max Unit Resolution - - 10 - Bits Differential Llinearity Error DLE - - ±1.0 LSB Integral Linearity Error ILE - ±2 - LSB Offset Voltage Error(Top) EOT - ±2.0 - LSB Offset Voltage Error(Bottom) EOB - ±2.0 - LSB Conversion Rate fAD 250 - - KSPS Conversion Time tAD 4 - - us Dynamic Supply Current Is - 1.2 2 mA Conversion Mode Power Dissipation Pd - 2.2 3.6 mW Conversion Mode Conditions NOTES 1. Converter Specifications (unless otherwise specified) VDD18A1=1.8V VDD18A2=1.8V VDD18A3=1.8V VSS18A1=GND VSS18A2=GND VSS18A3=GND VBBA1=GND VBBA2=GND REFT=1.35V REFB=0.45V Ta=25ºC 2. TBD : To Be Determined TIMING SPECIFICATIONS Characteristics Symbol Min Typ Max Unit Clock High Time tpwh 130 - - ns Clock Low Time tpwl 130 - - ns BUSY Signal Output Delay tBD 10 ADC Output Delay tOD 10 SEC ASIC Conditions Output load capacitor = 5pF - 4/13 - ns Output load capacitor = 5pF MIXED 10-BIT 250KSPS SAR ADC ADC1255X TIMING DIAGRAM Conversion Timing To be continued 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CLK SLEEP "LOW" "HIGH" BUSY CONV tOD DO[11:0] DO(n)[11:0] To be continued 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 CLK SLEEP BUSY 14 cycles CONV tOD tOD DO(n)[11:0] DO[11:0] 45 46 47 48 49 50 DO(n+1)[11:0] 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 CLK SLEEP BUSY CONV tOD DO[11:0] SEC ASIC DO(n+3)[11:0] DO(n+2)[11:0] 5/13 MIXED 10-BIT 250KSPS SAR ADC ADC1255X FUNCTIONAL DESCRIPTION The ADC1255X is a 10-bit analog-to-digital converter including successive approximation register, and parallel output port. The ADC1255X employs a successive approximation technique to determine the value of the analog input voltage. An array of binary-weighted capacitors subdivides the input value to perform the analog to digital conversion. The conversion of the ADC1255X is controlled by two signals, CONV and CLK. When CONV is taken "HIGH" on the rising edge of CLK, the ADC1255X is internally reset after next two clock cycles, the BUSY pin is driven "HIGH". The CONV pin should be held "HIGH" for at least one CLK cycle. The number of conversion cycles to generate an output data is 14 except the first conversion after the CONV pin is asserted. DO[11:2] are actual 10-bit output data with 1.8V power supply. There are extra least significant bits, DO[1:0] for 12-bit resolution when the part is operating with 2.5V power supply. SEC ASIC 6/13 MIXED 10-BIT 250KSPS SAR ADC CORE EVALUATION ADC1255X GUIDE The reference voltages should be asserted externally through REFT and REFB pins VDD18A1VSS18A1VBBA1 VDD18A2VSS18A2 VBBA2VDD18A3 VSS18A3 INP INN DO[11:0] adc1255x REFT VCOM REFB ITEST SLEEP CLK BUSY CONV DO[11:0] HOST DSP/Microcontroller CORE (ADC Function Test & externally forced Digital Input) SEC ASIC 7/13 MIXED 10-BIT 250KSPS SAR ADC ADC1255X PACKAGE CONFIGURATION Digital I 10u 0.1u 10u 1u 0.1u 10u 0.1u 10u 0.1u 50Ω VCOM 10u 0.1u Analog Digital II 10u 0.1u 50Ω 1 NC VDD18A2 48 2 REFT VDD18A2 47 3 NC VSS18A2 46 4 REFB VSS18A2 45 5 VCOM 6 VDD18A1 CONV 43 7 VDD18A1 NC 42 8 VBBA1 BUSY 41 9 VSS18A1 NC 40 10 VSS18A1 NC 39 11 INP 12 NC 13 INN DO[9] 36 14 NC DO[8] 35 15 NC DO[7] 34 16 ITEST DO[6] 33 17 SLEEP DO[5] 32 18 VDD18A3 DO[4] 31 19 VSS18A3 DO[3] 30 20 CLK DO[2] 29 21 NC DO[1] 28 22 NC DO[0] 27 23 RP NC 26 24 RN NC 25 0.1u 10u VBBA2 44 DO[11] 38 adc1255x DO[10] 37 NOTES 1. ESD (Electro Static Discharge) sensitive device. Although the digital control inputs are diode protected, permanent damage may occur on devices subjected to high electrostatic discharges. It is recommended that unused devices be stored in conductive foam or shunts to avoid performance degradation or loss of functionality. The protective foam should be discharged to the destination socket before devices are inserted. 2. NC denotes "No Connection". SEC ASIC 8/13 MIXED 10-BIT 250KSPS SAR ADC ADC1255X PACKAGE PIN DESCRIPTION I/O No. NAME 2 REFT AI Reference Top Voltage 4 REFB AI Reference Bottom Voltage NC 1 48 VDD18A2 5 VCOM AB Reference Middle Voltage REFT 2 47 VDD18A2 6, 7 VDD18A1 AP Analog Power NC 3 46 VSS18A2 8 VBBA1 AG Analog Bulk REFB 4 45 VSS18A2 9, 10 VSS18A1 AG Analog Ground VCOM 5 44 VBBA2 11 INP AI Analog Input (+) VDD18A1 6 43 CONV 13 INN AI Analog Input (-) VDD18A1 7 42 NC VBBA1 8 41 BUSY 16 ITEST AB open; use internal bias circuit VSS18A1 9 40 NC VSS18A1 10 39 NC INP 11 38 DO[11] NC 12 37 DO[10] INN 13 36 DO[9] 17 SLEEP TYPE DI PIN DESCRIPTION Sleep; Power Saving Mode (Active High) CONFIGURATION 18 VDD18A3 PP Output Buffer Power 19 VSS18A3 PG Output Buffer Ground 20 CLK DI Master Clock Input NC 14 35 DO[8] 27,28 DO[0:1] DO Extra Digital Output NC 15 34 DO[7] 29 DO[2] DO Digital Output (LSB) ITEST 16 33 DO[6] 30~37 DO[3:10] DO Digital Output SLEEP 17 32 DO[5] 38 DO[11] DO Digital Output (MSB) VDD18A3 18 31 DO[4] 41 BUSY DO Conversion in Process VSS18A3 19 30 DO[3] CLK 20 29 DO[2] NC 21 28 DO[1] NC 22 27 DO[0] NC 23 26 NC NC 24 25 NC Conversion Control Pin 43 CONV DI 44 VBBA2 DG Digital Bulk 45, 46 VSS18A2 DG Digital Ground 47, 48 VDD18A2 DP Digital Power (Active High) adc1255x NOTES 1. I/O TYPE PP and PG denote PAD Power and PAD Ground respectively SEC ASIC 9/13 MIXED 10-BIT 250KSPS SAR ADC ADC1255X USER GUIDE 1. Power Saving Mode When the overall system is in sleep, as SLEEP pin goes "HIGH", power consumption of the ADC1255X can be reduced a lot. 2. Power Consumption Optimization Yon can optimize power consumption, as the ITEST voltage level is controlled precisely. 3. Analog Input Range The analog input range is concerned with the difference voltage, REFT - REFB. In case that the INN pin is connected with VCOM pin, the analog input range of INP pin is equal to 2*(REFT - REFB). 4. Conversion Control To operate the ADC1255X in conversion mode, the CONV pin should be set to "HIGH" for more than one clock cycle. 5. Digital Output Data DO[11:2] are actual 10-bit output data with 1.8V power supply. SEC ASIC 10/13 MIXED 10-BIT 250KSPS SAR ADC ADC1255X Phantom Cell Information - Pins of the core can be assigned externally(Package pins) or internally(internal ports) depending on design methods. The term "external" implies that the pins should be assigned externally like power pins. The term "internal/external" implies that these pins are user dependant R E F B V C O M V D D 1 8 A 2 R E F T V S S 1 8 A 2 Pin Pin Name Usage VDD18A1 External VSS18A1 External VBBA1 External VDD18A2 External VSS18A2 External DO[11] VBBA2 External DO[10] VDD18A3 External D0[9] VSS18A3 External DO[8] REFT External DO[7] VCOM External REFB External INP External INN External/Internal - Using this pin internally, INN should be connected to DO[2] ITEST External/Internal - It is O.K that ITEST is floating. DO[1] CLK External/Internal - Don't cross over other signals as possible as it can VBBA2 CONV SLEEP VSS18A1 VBBA1 INP INN - Dedicated power/ground pins - Power cuts are required to provide on-chip isolation VDD18A1 VCOM Pin Layout Guide adc1255x 10-bit 250KSPS ADC DO[6] DO[5] - Use good power and source on board - Use good power source - Locate as close as possible to pad - Metal line width should be larger than 10um - Locate as close as possible to pad - Locate as close as possible to pad DO[4] DO[3] "VCOM" pad directly DO[0] CONV External/Internal SLEEP External/Internal DO[11:0] External/Internal BUSY I T E S T S L E E P C L K V D D 1 8 A 2 V S S 1 8 A 2 Table 1. Pin Layout Guide Figure 1. Phantom cell feature SEC ASIC 11/13 MIXED 10-BIT 250KSPS SAR ADC ADC1255X FEEDBACK REQUEST It should be quite helpful to ADC core development if you specify your system requirements on ADC in the following characteristic checking table and fill out the additional questions. We appreciate your interest in our products. Characteristic Min Typ Max Unit Analog Power Supply Voltage V Digital Power Supply Voltage V Resolution Remarks Bits Reference Input Voltage V Analog Input Voltage Vpp Number of Analog Input Channel Operating Temperature ºC Integral Linearity Error LSB Differential Linearity Error LSB Bottom Offset Voltage Error mV Top Offset Voltage Error mV Conversion Rate KSPS Conversion Time us Dynamic Supply Current mA Power Dissipation mW Power Dissipation at Power Down uW Digital Output Format (Provide detailed description & timing diagram) SEC ASIC 12/13 MIXED 10-BIT 250KSPS SAR ADC ADC1255X FEEDBACK REQUEST (To be continued) 1. We want to know the detail of the analog input waveform because sample & hold amplifier is not included in the ADC1255X. Which one is adequate for your analog input waveform among the a, b, and c below. If none of the three is adequate, please describe the analog input waveform to be used. If your analog input signal is a sinusoidal wave as c, please let me know what is the maximum frequency of the analog input signal ? It may be necessary to add a external sample & hold amplifier in any case. AIN a. (fixed DC input) b. (holding input) c. (sinusoidal wave) 2. Which one is suitable for your system between single ended input and differential input configurations and why ? 3. Please, mention on the internal/external pin configurations and draw the timing diagram as desired. 4. Freely list those functions you want to be implemented in ADC, if any. SEC ASIC 13/13 MIXED 10-BIT 250KSPS SAR ADC ADC1255X HISTORY CARD Version Date ver 1.0 ver 1.1 Modified Items Comments Original version published (preliminary) 2000.01 Release the formal datasheet SEC ASIC MIXED