ETC AT49LV040T-70TI

Features
•
•
•
•
•
•
•
•
•
Single Voltage for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)
Fast Read Access Time – 70 ns
Internal Program Control and Timer
16K Bytes Boot Block with Lockout
Fast Chip Erase Cycle Time – 10 seconds
Byte-by-byte Programming – 30 µs/Byte Typical
Hardware Data Protection
Data Polling for End of Program Detection
Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
• Typical 10,000 Write Cycles
• Small Packaging
– 8 x 14 mm VSOP/TSOP
Description
The AT49BV/LV040(T) are 3-volt only, 4-megabit Flash memories organized as
524,288 words of 8-bits each. Manufactured with Atmel’s advanced nonvolatile CMOS
technology, the devices offer access times to 70 ns with power dissipation of just
90 mW over the commercial temperature range. When the device is deselected, the
CMOS standby current is less than 50 µA.
The device contains a user-enabled “boot block” protection feature. Two versions of
the feature are available: the AT49BV/LV040 locates the boot block at lowest order
addresses (“bottom boot”); the AT49BV/LV040T locates it at highest order addresses
(“top boot”).
(continued)
4-megabit
(512K x 8)
Single 2.7-volt
Battery-Voltage™
Flash Memory
AT49BV040
AT49BV040T
AT49LV040
AT49LV040T
Pin Configurations
Pin Name
Function
A0 - A18
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
VSOP Top View (8 x 14 mm) or
TSOP Top View (8 x 20 mm)
29
28
27
26
25
24
23
22
21
14
15
16
17
18
19
20
5
6
7
8
9
10
11
12
13
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
4
3
2
1
32
31
30
A12
A15
A16
A18
VCC
WE
A17
PLCC Top View
A11
A9
A8
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
Rev. 0679C–04/00
1
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To allow for simple in-system reprogrammability, the
AT49BV/LV040(T) does not require high input voltages for
programming. Three-volt-only commands determine the
read and programming operation of the device. Reading
data out of the device is similar to reading from an EPROM.
Reprogramming the AT49BV/LV040(T) is performed by
erasing the entire four megabits of memory and then programming on a byte-by-byte basis. The typical byte
programming time is a fast 30 µs. The end of a program
cycle can be optionally detected by the Data Polling
feature. Once the end of a byte program cycle has been
detected, a new access for a read or program can begin.
The typical number of program and erase cycles is in
excess of 10,000 cycles.
The optional 16K bytes boot block section includes a reprogramming write lockout feature to provide data integrity.
The boot sector is designed to contain user-secure code,
and when the feature is enabled, the boot sector is permanently protected from being reprogrammed.
Block Diagram
AT49BV/LV040
VCC
GND
OE
WE
CE
ADDRESS
INPUTS
AT49BV/LV040T
DATA INPUTS/OUTPUTS
I/O7 - I/O0
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
OE, CE, AND WE
LOGIC
8
DATA LATCH
DATA LATCH
INPUT/OUTPUT
BUFFERS
INPUT/OUTPUT
BUFFERS
Y DECODER
Y-GATING
X DECODER
MAIN MEMORY
(496K BYTES)
Y-GATING
7FFFFH
OPTIONAL BOOT
BLOCK (16K BYTES)
04000H
03FFFH
00000H
7FFFFH
OPTIONAL BOOT
BLOCK (16K BYTES)
MAIN MEMORY
(496K BYTES)
7C000H
7BFFFH
00000H
Device Operation
READ: The AT49BV/LV040(T) is accessed like an
EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the
address pins is asserted on the outputs. The outputs are
put in the high-impedance state whenever CE or OE is
high. This dual-line control gives designers flexibility in preventing bus contention.
ERASURE: Before a byte can be reprogrammed, the 512K
bytes memory array (or 496K bytes if the boot block featured is used) must be erased. The erased state of the
memory bits is a logical “1”. The entire device can be
erased at one time by using a six-byte software code. The
software chip erase code consists of six-byte load commands to specific address locations with a specific data
pattern (please refer to “Chip Erase Cycle Waveforms” on
page 8).
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
2
AT49BV/LV040(T)
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BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a four-bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP cycle
time. The Data Polling feature may also be used to indicate
the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 16K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
AT49BV/LV040(T)
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be activated; the boot block’s usage as a write-protected region is
optional to the user. The address range of the
AT49BV/LV040 boot block is 00000H to 03FFFH, while the
address range of the AT49BV/LV040T boot block is
7C000H to 7FFFFH.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular programming method. To activate the lockout feature, a series
of six program commands to specific addresses with specific data must be performed. Please refer to the Command
Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the software product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out for the AT49BV/LV040 and a read from address
7C002H will show if programming the boot block is locked
out for the AT49BV/LV040(T). If the data on I/O0 is low, the
boot block can be programmed; if the data on I/O0 is high,
the program lockout feature has been activated and the
block cannot be programmed. The software product identification code should be used to return to standard
operation.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel.
It may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct programming algorithm for
the Atmel product.
For details, see “Operating Modes” on page 5 (for hardware operation) or “Software Product Identification
Entry/Exit” on page 10. The manufacturer and device
codes are the same for both modes.
DATA POLLING: The AT49BV/LV040(T) features Data
Polling to indicate the end of a program cycle. During a program cycle, an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin. Data Polling
may begin at any time during the program cycle.
TO G G L E B I T: I n a d d i t i o n t o D a t a P o l l i n g , t h e
AT49BV/LV040(T) provides another method for determining the end of a program or erase cycle. During a program
or erase operation, successive attempts to read data from
the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop
toggling and valid data will be read. Examining the toggle
bit may begin at any time during a program cycle.
HARDWARE DATA PROTECTION: The Hardware Data
Protection feature protects against inadvertent programs to
the AT49BV/LV040(T) in the following ways: (a) VCC sense:
if VCC is below 1.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE
high or WE high inhibits program cycles. (c) Noise filter:
pulses of less than 15 ns (typical) on the WE or CE inputs
will not initiate a program cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V
power supply, the address inputs and control inputs (OE,
CE and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to VCC + 0.6V.
3
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Command Definition (in Hex)
Command
Sequence
1st Bus
Cycle
Bus
Cycles
Addr
Data
Read
1
Addr
DOUT
Chip Erase
6
5555
Byte Program
4
Boot Block Lockout(1)
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
10
5555
AA
2AAA
55
5555
A0
Addr
DIN
6
5555
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
40
Product ID Entry
3
5555
AA
2AAA
55
5555
90
(2)
3
5555
AA
2AAA
55
5555
F0
Product ID Exit
(2)
Product ID Exit
1
XXXX
F0
Notes: 1. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49BV/LV040 and 7C000H to 7FFFFH for the
AT49BV/LV040T.
2. Either one of the Product ID Exit commands can be used.
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground ..................................-0.6V to + 13.5V
4
AT49BV/LV040(T)
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*NOTICE:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
AT49BV/LV040(T)
DC and AC Operating Range
Operating
Temperature (Case)
Com.
Ind.
VCC Power Supply
AT49LV040-70
AT49BV/LV040-90
AT49BV040-12
0°C - 70°C
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
3.0V to 3.6V
2.7V to 3.6V/3.0V to 3.6V
2.7V to 3.6V
Operating Modes
Mode
CE
OE
WE
Ai
I/O
Read
VIL
VIL
VIH
Ai
DOUT
Program(2)
VIL
VIH
VIL
Ai
DIN
X
High-Z
Standby/Write Inhibit
(1)
VIH
X
X
Program Inhibit
X
X
VIH
Program Inhibit
X
VIL
X
Output Disable
X
VIH
X
High-Z
Product Identification
Hardware
VIL
VIL
VIH
Software(2)
Notes:
1.
2.
3.
4.
A1 - A18 = VIL, A9 = VH,(3)
A0 = VIL
Manufacturer Code(4)
A1 - A18 = VIL, A9 = VH,(3)
A0 = VIH
Device Code(4)
A0 = VIL, A1 - A18 = VIL
Manufacturer Code(4)
A0 = VIH, A1 - A18 = VIL
Device Code(4)
X can be VIL or VIH.
Refer to AC programming waveforms.
VH = 12.0V ± 0.5V.
Manufacturer Code: 1FH
Device Code: 13H (AT49BV/LV040), 12H (AT49BV/LV040T).
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
50
µA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
1
mA
ICC(1)
VCC Active Current
f = 5 MHz; IOUT = 0 mA, VCC = 3.6V
25
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Notes:
Min
Typ
2.0
IOL = 2.1 mA
Output High Voltage
IOH = -100 µA; VCC = 3.0V
1. In the erase mode, ICC is 50 mA.
2. See details under “Software Product Identification Entry/Exit” on page 10.
V
0.45
2.4
V
V
5
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AC Read Characteristics
AT49LV040-70
Symbol
Parameter
tACC
Min
Max
AT49BV/LV040-90
Min
Max
AT49BV040-12
Min
Max
Units
Address to Output Delay
70
90
120
ns
(1)
CE to Output Delay
70
90
120
ns
tOE(2)
OE to Output Delay
0
35
0
40
0
50
ns
tDF(3)(4)
CE or OE to Output Float
0
25
0
25
0
30
ns
tOH
Output Hold from OE, CE or Address,
whichever comes first
0
tCE
0
0
ns
AC Read Waveforms(1)(2)(3)(4)
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
COUT
Note:
6
Typ
Max
Units
Conditions
4
6
pF
VIN = 0V
pF
VOUT = 0V
8
12
1. This parameter is characterized and is not 100% tested.
AT49BV/LV040(T)
AT49BV/LV040(T)
AC Byte Load Characteristics
Symbol
Parameter
tAS, tOES
Address, OE Setup Time
tAH
Address Hold Time
tCS
Min
Max
Units
0
ns
100
ns
Chip Select Setup Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
200
ns
tDS
Data Setup Time
100
ns
tDH, tOEH
Data, OE Hold Time
0
ns
tWPH
Write Pulse Width High
200
ns
AC Byte Load Waveforms
WE Controlled
CE Controlled
7
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Program Cycle Characteristics
Symbol
Parameter
tBP
Byte Programming Time
tAS
Address Setup Time
0
ns
tAH
Address Hold Time
100
ns
tDS
Data Setup Time
100
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
200
ns
tWPH
Write Pulse Width High
200
ns
tEC
Erase Cycle Time
Program Cycle Waveforms
Chip Erase Cycle Waveforms
Note:
8
OE must be high only when WE and CE are both low.
AT49BV/LV040(T)
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Min
Typ
Max
Units
30
50
µs
10
seconds
AT49BV/LV040(T)
Data Polling Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
Typ
Max
ns
10
ns
OE to Output Delay
Write Recovery Time
1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 6.
Units
0
(2)
tOE
tWR
Notes:
Min
ns
0
ns
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
Min
OE to Output Delay
tOEHP
OE High Pulse
tWR
Notes:
Write Recovery Time
1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 6.
Max
Units
0
ns
10
ns
(2)
tOE
Typ
ns
150
ns
0
ns
Toggle Bit Waveforms(1)(2)(3)
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
9
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Software Product Identification Entry(1)
LOAD DATA AA
TO
ADDRESS 5555
Boot Block Lockout Feature Enable
Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
LOAD DATA 80
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
(2)(3)(4)
MODE
Software Product Identification Exit
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
OR
LOAD DATA AA
TO
ADDRESS 5555
(1)
LOAD DATA F0
TO
ANY ADDRESS
LOAD DATA 55
TO
ADDRESS 2AAA
EXIT PRODUCT
IDENTIFICATION
MODE (4)
LOAD DATA 40
TO
ADDRESS 5555
LOAD DATA F0
TO
ADDRESS 5555
EXIT PRODUCT
IDENTIFICATION
MODE (4)
Notes:
10
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A18 = VIL.
Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH
Device Code: 13H (AT49BV/LV040),
12H (AT49BV/LV040T).
AT49BV/LV040(T)
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PAUSE 1 second
Notes:
(2)
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Boot Block Lockout feature enabled.
AT49BV/LV040(T)
AT49BV040(T) Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
90
25
120
90
120
Ordering Code
Package
Operation Range
0.05
AT49BV040-90JC
AT49BV040-90TC
AT49BV040-90VC
32J
32T
32V
Commercial
(0°C to 70°C)
25
0.05
AT49BV040-90JI
AT49BV040-90TI
AT49BV040-90VI
32J
32T
32V
Industrial
(-40°C to 85°C)
25
0.05
AT49BV040-12JC
AT49BV040-12TC
AT49BV040-12VC
32J
32T
32V
Commercial
(0°C to 70°C)
25
0.05
AT49BV040-12JI
AT49BV040-12TI
AT49BV040-12VI
32J
32T
32V
Industrial
(-40°C to 85°C)
25
0.05
AT49BV040T-90JC
AT49BV040T-90TC
AT49BV040T-90VC
32J
32T
32V
Commercial
(0°C to 70°C)
25
0.05
AT49BV040T-90JI
AT49BV040T-90TI
AT49BV040T-90VI
32J
32T
32V
Industrial
(-40°C to 85°C)
25
0.05
AT49BV040T-12JC
AT49BV040T-12TC
AT49BV040T-12VC
32J
32T
32V
Commercial
(0°C to 70°C)
25
0.05
AT49BV040T-12JI
AT49BV040T-12TI
AT49BV040T-12VI
32J
32T
32V
Industrial
(-40°C to 85°C)
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier Package (PLCC)
32T
32-lead, Plastic Thin Small Outline Package (TSOP) (8 x 20 mm)
32V
32-lead, Plastic Thin Small Outline Package (TSOP) (8 x 14 mm)
11
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AT49LV040(T) Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
70
25
90
70
90
Ordering Code
Package
0.05
AT49LV040-70JC
AT49LV040-70TC
AT49LV040-70VC
32J
32T
32V
Commercial
(0°C to 70°C)
25
0.05
AT49LV040-70JI
AT49LV040-70TI
AT49LV040-70VI
32J
32T
32V
Industrial
(-40°C to 85°C)
25
0.05
AT49LV040-90JC
AT49LV040-90TC
AT49LV040-90VC
32J
32T
32V
Commercial
(0°C to 70°C)
25
0.05
AT49LV040-90JI
AT49LV040-90TI
AT49LV040-90VI
32J
32T
32V
Industrial
(-40°C to 85°C)
25
0.05
AT49LV040T-70JC
AT49LV040T-70TC
AT49LV040T-70VC
32J
32T
32V
Commercial
(0°C to 70°C)
25
0.05
AT49LV040T-70JI
AT49LV040T-70TI
AT49LV040T-70VI
32J
32T
32V
Industrial
(-40°C to 85°C)
25
0.05
AT49LV040T-90JC
AT49LV040T-90TC
AT49LV040T-90VC
32J
32T
32V
Commercial
(0°C to 70°C)
25
0.05
AT49LV040T-90JI
AT49LV040T-90TI
AT49LV040T-90VI
32J
32T
32V
Industrial
(-40°C to 85°C)
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier Package (PLCC)
32T
32-lead, Plastic Thin Small Outline Package (TSOP) (8 x 20 mm)
32V
32-lead, Plastic Thin Small Outline Package (TSOP) (8 x 14 mm)
12
AT49BV/LV040(T)
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Operation Range
AT49BV/LV040(T)
Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
32T, 32-lead, Plastic Thin Small Outline Package
(TSOP) Dimensions in Millimeters and (Inches)*
JEDEC STANDARD MS-016 AE
JEDEC OUTLINE MO-142 BA
.045(1.14) X 45˚
PIN NO. 1
IDENTIFY
.025(.635) X 30˚ - 45˚
.012(.305)
.008(.203)
.553(14.0)
.547(13.9)
.595(15.1)
.585(14.9)
.032(.813)
.026(.660)
.050(1.27) TYP
INDEX
MARK
.530(13.5)
.490(12.4)
18.5(.728)
18.3(.720)
.021(.533)
.013(.330)
.030(.762)
.015(.381)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
.300(7.62) REF
.430(10.9)
.390(9.90)
AT CONTACT
POINTS
0.50(.020)
BSC
7.50(.295)
REF
0.25(.010)
0.15(.006)
8.20(.323)
7.80(.307)
.022(.559) X 45˚ MAX (3X)
.453(11.5)
.447(11.4)
.495(12.6)
.485(12.3)
20.2(.795)
19.8(.780)
1.20(.047) MAX
0.15(.006)
0.05(.002)
0
5 REF
0.20(.008)
0.10(.004)
0.70(.028)
0.50(.020)
*Controlling dimension: millimeters
32V, 32-lead, Plastic Thin Small Outline Package
(TSOP) Dimensions in Millimeters and (Inches)*
JEDEC OUTLINE MO-142 BA
INDEX
MARK
12.5(.492)
12.3(.484)
0.50(.020)
BSC
7.50(.295)
REF
14.2(.559)
13.8(.543)
0.25(.010)
0.15(.006)
8.10(.319)
7.90(.311)
1.20(.047) MAX
0.15(.006)
0.05(.002)
0
5 REF
0.20(.008)
0.10(.004)
0.70(.028)
0.50(.020)
*Controlling dimension: millimeters
13
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