KS0118C GENLOCK ADC INTRODUCTION The KS0118C is a CMOS integrated circuit designed for the GEN LOCK and ND Conversion. It is a Monolithic IC that enabled an analog NTSC composite video signal to digitize at a clock rate that is synchronized and locked to the incoming video horizontal line frequency. It includes clamping function, 8-bit digitizing and creation of a line locked sampling clock. It is possible to correspond to the video signal system of LDP by the use of KA9413, KA 9414-D ICS together, which is designed for the Digital Video Signal Processor. 80-QFP-1420C ORDERING IN FORMATION Device Package KS0118C 80-QFP-1420C FEATURES • • • • • • • • • • • NTSC Video Signal Input Line-locked Sync and Clock Generation Line to Line Jitter < 20 nsec O Differential Gain 2% Differential Phase 2 Programmable Sample Clock Frequency from 25 to 30 MHz Built-in 8 Bit CMOS Analog to Digital Converter Programmable Gain Control and Automatic DC Offset Control for Video Signal Input Programmable PLL Time Constants for Tracking Different Input Types Correctly Tracks Line Drop-outs Provides a Microprocessor 3 Wire Serial Interface Built-in Decimation Filter Single Power Supply: +5V Operating Temperature Î~+75Î -20 KS0118C GENLOCK ADC BLOCK DIAGRAM VIN 70 8 BIT ADC CLAMP DECIMATION FILTER 48 55 CVBS<0:7> LPF DIGITAL OFFSET CONTROL CRYSTAL DRIVER DTO JITTER REDUCTION OUTPUT TIMING PIXEL COUNTER SERIAL MICOM INTERFACE 19 25 27 SCLK 5 SDAT 4 XTL2 SFRS XTL1 SYNC DETECTOR Fig. 1 35 LOCK 39 VS 40 SLICE 16 FSMP PHASE DET/ PLL FILTER KS0118C GENLOCK ADC NC NC NC NC VDD NC GND CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS7 CVBS6 GND VDD VDD VDD (A) GND NC NC NC NC PIN CONFIGURATION 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VDD (A) 75 RVCO 76 CREF2 77 GND 78 NC 79 NC 80 31 NC 30 NC 29 NC 28 NC 27 SDAT 26 NC 25 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Fig. 2 NC 74 NC GND 32 NC NC 73 NC RREF 33 NC KS0118 NC 72 NC SFRS NC 34 NC LDP 71 GND FSMP GND 35 LOCK NC 70 FRZ VDD VIN 36 NC SYG 69 NC CAGC 37 NC NC 68 GND VDD (A) 38 NC VDD (A) 67 VDD (A) CREF1 39 VS XTL2 66 XTL1 VRT 40 SLICE NC 65 RCPLL RSTB VRB KS0118C GENLOCK ADC PIN DESCRIPTION Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol RCPLL RSTB NC XTL1 XTL2 VDD(A) VDD(A) GND NC NC SYG NC FRZ VDD GND FSMP LDP NC SFRS NC NC NC NC NC SCLK NC SDAT NC NC NC NC NC NC NC LOCK NC NC NC VS SLICE I/O I/O I I O O I O I I I I/O O O O Description External Filter Pin for Analog PLL System Reset Signal Input (Active Low) No Connection Pin1 for External Crystal Oscillator Pin2 for External Crystal Oscillator + 5V Supply Voltage for Analog Domain + 5V Supply Voltage for Analog Domain Ground No Connection No Connection Line Locked Horizontal Sync Signal No Connection Connect this Pin to + 5V for proper Operation + 5V Supply Voltage for Digital Domain Ground Freq. & Phase compensated Sample Clock used for ADC Connect this Pin to + 5V for proper Operation No Connection Frame Signal for Serial Data Interface No Connection No Connection No Connection No Connection No Connection Clock Signal Input for Serial Data Interface No Connection Serial Data in Serial Interface No Connection No Connection No Connection No Connection No Connection No Connection No Connection High when the GENLOCK is locked & in Tracking State No Connection No Connection No Connection Vertical Sync Signal Output Sync level. Low when CVBS < 32. This Signal is not Line locked KS0118C GENLOCK ADC PIN DESCRIPTION (Continued) Pin No 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Symbol NC NC NC NC NC VDD GND CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7 GND VDD VDD VDD(A) GND NC NC NC NC VRB VRT CREF1 VDD(A) CAGC VIN GND NC RREF GND VDD(A) RVCO CREF2 GND NC NC I/O O O O O O O O O I/O I/O I/O I I I/O I/O I/O - Description No Connection No Connection No Connection No Connection No Connection + 5V Supply Voltage for Digital Domain Ground 8 Bit Composite Video Baseband Signal 8 Bit Composite Video Baseband Signal 8 Bit Composite Video Baseband Signal 8 Bit Composite Video Baseband Signal 8 Bit Composite Video Baseband Signal 8 Bit Composite Video Baseband Signal 8 Bit Composite Video Baseband Signal 8 Bit Composite Video Baseband Signal Ground + 5V Supply Voltage for Digital Domain + 5V Supply Voltage for Digital Domain + 5V Supply Voltage for Digital Domain Ground No Connection No Connection No Connection No Connection Bottom Voltage Reference for ADC Top Voltage Reference for ADC Decoupling Pin for Reference Voltage +5V Supply Voltage for Analog Domain Capacitor for Offset Control Analog NTSC Video Signal Input (1Vpp) Ground No Connection Current Setting Pin for Internal Analog Circuitry Ground + 5V Supply Voltage for Analog Domain Current Setting Pin for Analog VCO Decoupling Pin for Reference Voltage Ground No Connection No Connection KS0118C GENLOCK ADC ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Supply Voltage Characteristic VDD -0.5 ~+7.0 V Voltage on any Digital Pin VPIN GND ~ VDD Operating Temperature T OPR - 20 ~ + 75 Storage Temperature T STG -55 ~ +125 Î Î V ELECTRICAL CHARACTERISTICS Î, unless otherwise specified) (Ta = 25 Min Typ Max Digital Input High Voltage Characteristic Symbol VIH VDD = 4.75V Test Conditions 4.0 - - V Digital Input Low Voltage VIL VDD = 5.25V - - 1.0 V Digital Output High Voltage VOH VDD = 4.75V 4.0 - - V Digital Output Low Voltage VOL VDD = 5.25V - - 1.0 mA Static Power Current lCCS VDD = 5.25V 34 74 94 mA Dynamic Power Current ICCD VDD = 5.25V 140 - 200 mA Serial uP I/O Set-up Time tUS XTL = 24.576MHz - - 10 ns Serial uP I/O Hold Time tUH XTL = 24.576MHz - - 10 ns Differential Phase DP - - 2.0 - deg Differential Gain DG - - 2.0 - % Signal to Noise Ratio SNR - 35 - - dB uP Maximum Data Rate fMPU VDD = 4.75V Frequency Lock Range FLT XTL = 24.576MHz Unit 5.0 - - MHz 28.60 - 28.66 MHz KS0118C GENLOCK ADC TEST CIRCUIT VDD(A) VDD 0.1 GND } 22 + 0.1 0.1 0.1 V25 + VDD(A) 22 VIN } 10 15 + GND 0.1 + 22 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 0.1 200 GND 22 0.1 VDD(A) VDD 65 40 66 39 67 38 68 37 69 36 70 35 34 71 120 33 72 0.1 V11 30 74 29 28 75 27 + 31 KS0118 2.4K VDD(A) 22 32 73 8K 0.1 76 26 77 25 78 79 3nF 82 30K 80 1 33pF 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23 1K 33pF 10K GND 0.1uF 0.1uF RTSB 22uF + GND X-TAL 24.576MHz + 22uF GND VDD(A) V DD Fig. 3. FSMP GND VDD KS0118C GENLOCK ADC APPLICATION INFORMATION FUNCTION DESCRIPTION 1. GENERAL DESCRIPTION The KS0118C implements the funtions of an 8 Bit ADC, Analog Clamp, Analog PLL Clock Generator and Digital Timing Generation. Throuth the use of VLSl technology, the KS0118C combines analog circuits with digital signal processing to obtain locking characteristics not achievable by ordinary methods. The KS0118C uses 1 external frequency reference to create many different programmable line lock sampling clocks. 2. ANALOG TO DIGITAL CONVERTER The KS0118C uses a two step, 8 bit and auto zero ADC to digitize the analog video input. The VRT and VRB pins are the top and bottom reference voltage for the ADC. These references are generated internally but required 0.1 decoupling capacitors to ground. Ó 3. EXTERNAL FREQUENCY REFERENCE The KS0118C requires an external stable frequency reference to generate the sampling clock. Although a wide range of frequency will work with the GENLOCK, it is recommended that 24.576MHz be used as the reference. This can be derived from a standard crystal or an external clock. 4. ANALOG PHASE LOCK LOOP The KS0118C has an internal PLL used for producing the sampling clock. This PLL requires an external loop filter at pin 1 (RCPLL) as shown in the application circuit. The ground connections for this filter should be placed close to pin 78, while the inputs should be located close to pin 1. The PLL also requires an external resistor to converter the voltage of the RCPLL node to a current for use by the internal VCO. The voltage of the pin 76 (RVCO) will track RCPLL Although the absolute voltage of these pins depends on many factors, it will be between 0.75 and 4.50 voltalge. The voltage will exhibit the standard characteristics of an analog PLL. KS0118C GENLOCK ADC FSMP CVBS ADC CODE = 32 tDSYS tDD SLICE ~ ~ ~ ~ ~ ~ VIN ~ ~ tDSLICE VS tDSVS Fig. 4 Data Path Propagation Delay and Key Timing Signals WHITE LEVEL CODE = 224.234 100IRE 160 ( 170 ) CODES BLANK LEVEL CODE = 84 40 IRE Fig. 5 Digitized Code Levels KS0118C GENLOCK ADC APPLICATION CIRCUIT KS9411 KA9413 VDD(A) VDD 0.1 GND } + 22 0.1 0.1 0.1 V25 VDD(A) 22 } 15 + Composit Video Signal input ( 1Vpp ) from KA9411 10 + GND 0.1 + 22 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 0.1 200 GND 22 0.1 VDD(A) VDD 65 40 66 39 67 38 68 37 69 36 70 35 34 71 120 33 72 0.1 30 29 28 75 27 + 22 31 KS0118 74 VDD(A) V11 32 73 2.4K 8K 0.1 76 26 77 25 78 79 3nF 82 30K 80 1 33pF 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23 1K 10K 33pF 0.1uF 0.1uF 22uF GND + + 22uF X-TAL GND 24.576MHz GND GND VDD VDD(A) VDD KS9411 KA9413 KS9411 KA9413