MICROCHIP PIC32MX4XXF32HT

PIC32MX3XX/4XX Family
Data Sheet
64/100-Pin General Purpose and USB
32-Bit Flash Microcontrollers
© 2009 Microchip Technology Inc.
Preliminary
DS61143F
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
Omniscient Code Generation, PICC, PICC-18, PICkit,
PICDEM, PICDEM.net, PICtail, PIC32 logo, REAL ICE, rfLAB,
Select Mode, Total Endurance, TSHARC, WiperLock and
ZENA are trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS61143F-page ii
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
High-Performance 80 MHz MIPS-Based 32-bit Flash Microcontroller
64/100-Pin General Purpose and USB
High-Performance 32-bit RISC CPU:
• MIPS32® M4K™ 32-bit Core with 5-Stage Pipeline
• 80 MHz Maximum Frequency
• 1.56 DMIPS/MHz (Dhrystone 2.1) Performance
at 0 Wait State Flash Access
• Single-Cycle Multiply and High-Performance
Divide Unit
• MIPS16e™ Mode for Up to 40% Smaller Code
Size
• Two Sets of 32 Core Register Files (32-bit) to
Reduce Interrupt Latency
• Prefetch Cache Module to Speed Execution from
Flash
Microcontroller Features:
• Operating Voltage Range of 2.3V to 3.6V
• 32K to 512K Flash Memory (plus an additional
12KB of Boot Flash)
• 8K to 32K SRAM Memory
• Pin-Compatible with Most PIC24/dsPIC® Devices
• Multiple Power Management Modes
• Multiple Interrupt Vectors with Individually
Programmable Priority
• Fail-Safe Clock Monitor Mode
• Configurable Watchdog Timer with On-Chip
Low-Power RC Oscillator for Reliable Operation
Peripheral Features:
• Atomic SET, CLEAR and INVERT Operation on
Select Peripheral Registers
• Up to 4-Channel Hardware DMA with Automatic
Data Size Detection
• USB 2.0 Compliant Full Speed Device and
On-The-Go (OTG) Controller
• USB has a Dedicated DMA Channel
• 10 MHz to 40 MHz Crystal Oscillator
• Internal 8 MHz and 32 kHz Oscillators
© 2009 Microchip Technology Inc.
• Separate PLLs for CPU and USB Clocks
• Two I2C™ Modules
• Two UART Modules with:
- RS-232, RS-485 and LIN 1.2 support
- IrDA® with On-Chip Hardware Encoder and
Decoder
• Parallel Master and Slave Port (PMP/PSP) with
8-bit and 16-bit Data and Up to 16 Address Lines
• Hardware Real-Time Clock/Calendar (RTCC)
• Five 16-bit Timers/Counters (two 16-bit pairs combine to create two 32-bit timers)
• Five Capture Inputs
• Five Compare/PWM Outputs
• Five External Interrupt Pins
• High-Speed I/O Pins Capable of Toggling at Up to
80 MHz
• High-Current Sink/Source (18 mA/18 mA) on
All I/O Pins
• Configurable Open-Drain Output on Digital I/O
Pins
Debug Features:
• Two Programming and Debugging Interfaces:
- 2-Wire Interface with Unintrusive Access and
Real-time Data Exchange with Application
- 4-wire MIPS® Standard Enhanced JTAG
interface
• Unintrusive Hardware-Based Instruction Trace
• IEEE Std 1149.2 Compatible (JTAG) Boundary
Scan
Analog Features:
• Up to 16-Channel 10-bit Analog-to-Digital
Converter:
- 1000 ksps Conversion Rate
- Conversion Available During Sleep, Idle
• Two Analog Comparators
• 5V Tolerant Input Pins (digital pins only)
Preliminary
DS61143F-page 1
PIC32MX3XX/4XX
TABLE 1:
PIC32MX GENERAL PURPOSE – FEATURES
0
Yes
No
2/2/2
16
2
Yes
Yes
PT, MR
5/5/5
0
Yes
No
2/2/2
16
2
Yes
Yes
PT, MR
PIC32MX320F128H
64
80
128 + 12(1)
16
5/5/5
0
Yes
No
2/2/2
16
2
Yes
Yes
PT, MR
PIC32MX340F128H
64
80
128 + 12(1)
32
5/5/5
4
Yes
No
2/2/2
16
2
Yes
Yes
PT, MR
PIC32MX340F256H
64
80
256 + 12(1)
32
5/5/5
4
Yes
No
2/2/2
16
2
Yes
Yes
PT, MR
PIC32MX340F512H
64
80
512 + 12(1)
32
5/5/5
4
Yes
No
2/2/2
16
2
Yes
Yes
PT, MR
12(1)
10-bit A/D (ch)
Trace
Data Memory (KB)
MHz
Packages(2)
5/5/5
16
JTAG
8
64 + 12(1)
PMP/PSP
32 + 12(1)
80
Comparators
VREG
40
64
EUART/SPI/I2C™
Programmable DMA
Channels
64
PIC32MX320F064H
Device
Program Memory (KB)
PIC32MX320F032H
Pins
Timers/Capture/Compare
GENERAL PURPOSE
PIC32MX320F128L
100
80
128 +
16
5/5/5
0
Yes
No
2/2/2
16
2
Yes
Yes
PT
PIC32MX340F128L
100
80
128 + 12(1)
32
5/5/5
4
Yes
No
2/2/2
16
2
Yes
Yes
PT
PIC32MX360F256L
100
80
256 + 12(1)
32
5/5/5
4
Yes
Yes
2/2/2
16
2
Yes
Yes
PT
PIC32MX360F512L
100
80
512 + 12(1)
32
5/5/5
4
Yes
Yes
2/2/2
16
2
Yes
Yes
PT
Legend:
PT = TQFP
Note 1:
2:
This device features 12 KB Boot Flash memory.
See Legend for an explanation of the acronyms. See Section 29.0 “Packaging Information” for details.
TABLE 2:
MR = QFN
PIC32MX USB – FEATURES
Timers/Capture/Compare
Programmable DMA
Channels
Dedicated USB DMA
Channels
VREG
Trace
EUART/SPI/I2C™
10-bit A/D (ch)
Comparators
PMP/PSP
JTAG
Packages(2)
5/5/5
0
2
Yes
No
2/1/2
16
2
Yes
Yes
PT, MR
Program Memory (KB)
8
(1)
MHz
PIC32MX420F032H
Pins
Device
Data Memory (KB)
USB
64
80
32 + 12(1)
PIC32MX440F128H
64
80
128 + 12
32
5/5/5
4
2
Yes
No
2/1/2
16
2
Yes
Yes
PT, MR
PIC32MX440F256H
64
80
256 + 12(1)
32
5/5/5
4
2
Yes
No
2/1/2
16
2
Yes
Yes
PT, MR
(1)
PT, MR
PIC32MX440F512H
64
80
512 + 12
32
5/5/5
4
2
Yes
No
2/1/2
16
2
Yes
Yes
PIC32MX440F128L
100
80
128 + 12(1)
32
5/5/5
4
2
Yes
No
2/2/2
16
2
Yes
Yes
PT
PIC32MX460F256L
100
80
256 + 12(1)
32
5/5/5
4
2
Yes
Yes 2/2/2
16
2
Yes
Yes
PT
PIC32MX460F512L
100
80
512 + 12(1)
32
5/5/5
4
2
Yes
Yes 2/2/2
16
2
Yes
Yes
PT
Legend:
PT = TQFP
Note 1:
2:
This device features 12 KB Boot Flash memory.
See Legend for an explanation of the acronyms. See Section 29.0 “Packaging Information” for details.
DS61143F-page 2
MR = QFN
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
PIN DIAGRAM:
64-PIN QFN – GENERAL PURPOSE
= Pins are up to 5V tolerant
PMD4/RE4
PMD3/RE3
PMD2/RE2
PMD1/RE1
PMD0/RE0
RF1
RF0
ENVREG
VCAP/VDDCORE
CN16/RD7
CN15/RD6
PMRD/CN14/RD5
PMWR/OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
OC2/RD1
64-Pin QFN (General Purpose)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PMD5/RE5
PMD6/RE6
PMD7/RE7
PMA5/SCK2/CN8/RG6
PMA4/SDI2/CN9/RG7
PMA3/SDO2/CN10/RG8
MCLR
PMA2/SS2/CN11/RG9
VSS
VDD
C1IN+/AN5/CN7/RB5
C1IN-/AN4/CN6/RB4
C2IN+/AN3/CN5/RB3
C2IN-/AN2/SS1/CN4/RB2
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
PGED1/PMA6/AN0/VREF+/CVREF+/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC32MX3XXH
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
OC1/RD0
IC4/PMCS1/PMA14/INT4/RD11
IC3/PMCS2/PMA15/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/RTCC/INT1/RD8
Vss
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/BCLK1/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
AVDD
AVSS
U2CTS/C1OUT/AN8/RB8
PMA7/C2OUT/AN9/RB9
TMS/CVREFOUT/PMA13/AN10/RB10
TDO/PMA12/AN11/RB11
VSS
VDD
TCK/PMA11/AN12/RB12
TDI/PMA10/AN13/RB13
PMALH/PMA1/U2RTS/BCLK2/AN14/RB14
PMALL/PMA0/AN15/OCFB/CN12/RB15
PMA9/U2RX/SDA2/CN17/RF4
PMA8/U2TX/SCL2/CN18/RF5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 3
PIC32MX3XX/4XX
PIN DIAGRAM: 64-PIN TQFP – GENERAL PURPOSE
64-Pin TQFP (General Purpose)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PMD4/RE4
PMD3/RE3
PMD2/RE2
PMD1/RE1
PMD0/RE0
RF1
RF0
ENVREG
VCAP/VDDCORE
CN16/RD7
CN15/RD6
PMRD/CN14/RD5
PMWR/OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
OC2/RD1
= Pins are up to 5V tolerant
PMD5/RE5
PMD6/RE6
PMD7/RE7
PMA5/SCK2/CN8/RG6
PMA4/SDI2/CN9/RG7
PMA3/SDO2/CN10/RG8
MCLR
PMA2/SS2/CN11/RG9
VSS
PIC32MX3XXH
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
OC1/RD0
IC4/PMCS1/PMA14/INT4/RD11
IC3/PMCS2/PMA15/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/RTCC/INT1/RD8
Vss
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/BCLK1/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
AVDD
AVSS
U2CTS/C1OUT/AN8/RB8
PMA7/C2OUT/AN9/RB9
TMS/CVREFOUT/PMA13/AN10/RB10
TDO/PMA12/AN11/RB11
VSS
VDD
TCK/PMA11/AN12/RB12
TDI/PMA10/AN13/RB13
PMALH/PMA1/U2RTS/BCLK2/AN14/RB14
PMALL/PMA0/AN15/OCFB/CN12/RB15
PMA9/U2RX/SDA2/CN17/RF4
PMA8/U2TX/SCL2/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VDD
C1IN+/AN5/CN7/RB5
C1IN-/AN4/CN6/RB4
C2IN+/AN3/CN5/RB3
C2IN-/AN2/SS1/CN4/RB2
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
PGED1/PMA6/AN0/VREF+/CVREF+/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DS61143F-page 4
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
PIN DIAGRAM:
100-PIN TQFP – GENERAL PURPOSE
100-Pin TQFP (General Purpose)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PMD4/RE4
PMD3/RE3
PMD2/RE2
TRD0/RG13
TRD1/RG12
TRD2/RG14
PMD1/RE1
PMD0/RE0
TRD3/RA7
TRCLK/RA6
PMD8/RG0
PMD9/RG1
PMD10/RF1
PMD11/RF0
ENVREG
VCAP/VDDCORE
PMD15/CN16/RD7
PMD14/CN15/RD6
PMRD/CN14/RD5
PMWR/OC5/CN13/RD4
PMD13/CN19/RD13
PMD12/IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
= Pins are up to 5V tolerant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIC32MX3XXL
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
OC1/RD0
IC4/PMCS1/PMA14/RD11
IC3/PMCS2/PMA15/RD10
IC2/RD9
IC1/RTCC/RD8
INT4/RA15
INT3/RA14
VSS
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
TDO/RA5
TDI/RA4
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
PMA7/VREF-/CVREF-/RA9
PMA6/VREF+/CVREF+/RA10
AVDD
AVSS
C1OUT/AN8/RB8
C2OUT/AN9/RB9
CVREFOUT/PMA13/AN10/RB10
PMA12/AN11/RB11
VSS
VDD
TCK/RA1
U2RTS/BCLK2/RF13
U2CTS/RF12
PMA11/AN12/RB12
PMA10/AN13/RB13
PMALH/PMA1/AN14/RB14
PMALL/PMA0/AN15/OCFB/CN12/RB15
VSS
VDD
CN20/U1CTS/RD14
U1RTS/BCLK1/CN21/RD15
PMA9/U2RX/CN17/RF4
PMA8/U2TX/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RG15
VDD
PMD5/RE5
PMD6/RE6
PMD7/RE7
T2CK/RC1
T3CK/RC2
T4CK/RC3
T5CK/RC4
PMA5/SCK2/CN8/RG6
PMA4/SDI2/CN9/RG7
PMA3/SDO2/CN10/RG8
MCLR
PMA2/SS2/CN11/RG9
VSS
VDD
TMS/RA0
INT1/RE8
INT2/RE9
C1IN+/AN5/CN7/RB5
C1IN-/AN4/CN6/RB4
C2IN+/AN3/CN5/RB3
C2IN-/AN2/SS1/CN4/RB2
PGEC1/AN1/CN3/RB1
PGED1/AN0/CN2/RB0
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 5
PIC32MX3XX/4XX
PIN DIAGRAM:
64-PIN QFN – USB
64-Pin QFN (USB)
RF1
RF0
ENVREG
VCAP/VDDCORE
CN16/RD7
CN15/RD6
PMRD/CN14/RD5
PMWR/OC5/IC5/CN13/RD4
OC4/U1TX/RD3
OC3/U1RX/RD2
OC2/U1RTS/BCLK1/RD1
PMD4/RE4
PMD3/RE3
PMD2/RE2
PMD1/RE1
PMD0/RE0
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PMD5/RE5
PMD6/RE6
PMD7/RE7
PMA5/SCK2/CN8/RG6
PMA4/SDI2/CN9/RG7
PMA3/SDO2/CN10/RG8
MCLR
PMA2/SS2/CN11/RG9
VSS
VDD
VBUSON/C1IN+/AN5/CN7/RB5
C1IN-/AN4/CN6/RB4
C2IN+/AN3/CN5/RB3
C2IN-/AN2/CN4/RB2
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
PGED1/EMUD1/PMA6/AN0/VREF+/CVREF+/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC32MX4XXH
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
OC1/INT0/RD0
IC4/PMCS1/PMA14/INT4/RD11
IC3/PMCS2/PMA15/INT3/SCL1/RD10
IC2/U1CTS//INT2/SDA1/RD9
IC1/RTCC/INT1/RD8
Vss
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
D+/RG2
D-/RG3
VUSB
VBUS
USBID/RF3
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
AVDD
AVSS
U2CTS/C1OUT/AN8/RB8
PMA7/C2OUT/AN9/RB9
TMS/CVREFOUT/PMA13/AN10/RB10
TDO/PMA12/AN11/RB11
VSS
VDD
TCK/PMA11/AN12/RB12
TDI/PMA10/AN13/RB13
PMALH/PMA1/U2RTS/BCLK2/AN14/RB14
PMALL/PMA0/AN15/OCFB/CN12/RB15
PMA9/U2RX/SDA2/CN17/RF4
PMA8/U2TX/SCL2/CN18/RF5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
DS61143F-page 6
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
PIN DIAGRAM:
64-PIN TQFP – USB
= Pins are up to 5V tolerant
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PMD4/RE4
PMD3/RE3
PMD2/RE2
PMD1/RE1
PMD0/RE0
RF1
RF0
ENVREG
VCAP/VDDCORE
CN16/RD7
CN15/RD6
PMRD/CN14/RD5
PMWR/OC5/IC5/CN13/RD4
OC4/U1TX/RD3
OC3/U1RX/RD2
OC2/U1RTS/BCLK1/RD1
64-Pin TQFP (USB)
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PGED1/EMUD1/PMA6/AN0/VREF+/CVREF+/CN2/RB0
16
PMD5/RE5
PMD6/RE6
PMD7/RE7
PMA5/SCK2/CN8/RG6
PMA4/SDI2/CN9/RG7
PMA3/SDO2/CN10/RG8
MCLR
PMA2/SS2/CN11/RG9
VSS
VDD
VBUSON/C1IN+/AN5/CN7/RB5
C1IN-/AN4/CN6/RB4
C2IN+/AN3/CN5/RB3
33
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
OC1/INT0/RD0
IC4/PMCS1/PMA14/INT4/RD11
IC3/PMCS2/PMA15/INT3/SCL1/RD10
IC2/U1CTS//INT2/SDA1/RD9
IC1/RTCC/INT1/RD8
Vss
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
D+/RG2
D-/RG3
VUSB
VBUS
USBID/RF3
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
AVDD
AVSS
U2CTS/C1OUT/AN8/RB8
PMA7/C2OUT/AN9/RB9
TMS/CVREFOUT/PMA13/AN10/RB10
TDO/PMA12/AN11/RB11
VSS
VDD
TCK/PMA11/AN12/RB12
TDI/PMA10/AN13/RB13
PMALH/PMA1/U2RTS/BCLK2/AN14/RB14
PMALL/PMA0/AN15/OCFB/CN12/RB15
PMA9/U2RX/SDA2/CN17/RF4
PMA8/U2TX/SCL2/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C2IN-/AN2/CN4/RB2
PIC32MX4XXH
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 7
PIC32MX3XX/4XX
PIN DIAGRAM:
100-PIN TQFP – USB
= Pins are up to 5V tolerant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIC32MX4XXL
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
SDO1/OC1/INT0/RD0
IC4/PMCS1/PMA14/RD11
IC3/SCK1/PMCS2/PMA15/RD10
IC2/SS1/RD9
IC1/RTCC/RD8
SDA1/INT4/RA15
SCL1/INT3/RA14
VSS
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
TDO/RA5
TDI/RA4
SDA2/RA3
SCL2/RA2
D+/RG2
D-/RG3
VUSB
VBUS
U1TX/RF8
U1RX/RF2
USBID/RF3
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
PMA7/VREF-/CVREF-/RA9
PMA6/VREF+/CVREF+/RA10
AVDD
AVSS
C1OUT/AN8/RB8
C2OUT/AN9/RB9
CVREFOUT/PMA13/AN10/RB10
PMA12/AN11/RB11
VSS
VDD
TCK/RA1
U2RTS/BCLK2/RF13
U2CTS/RF12
PMA11/AN12/RB12
PMA10/AN13/RB13
PMALH/PMA1/AN14/RB14
PMALL/PMA0/AN15/OCFB/CN12/RB15
VSS
VDD
CN20/U1CTS/RD14
U1RTS/BCLK1/CN21/RD15
PMA9/U2RX/CN17/RF4
PMA8/U2TX/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RG15
VDD
PMD5/RE5
PMD6/RE6
PMD7/RE7
T2CK/RC1
T3CK/RC2
T4CK/RC3
SDI1/T5CK/RC4
PMA5/SCK2/CN8/RG6
PMA4/SDI2/CN9/RG7
PMA3/SDO2/CN10/RG8
MCLR
PMA2/SS2/CN11/RG9
VSS
VDD
TMS/RA0
INT1/RE8
INT2/RE9
VBUSON/C1IN+/AN5/CN7/RB5
C1IN-/AN4/CN6/RB4
C2IN+/AN3/CN5/RB3
C2IN-/AN2/CN4/RB2
PGEC1/AN1/CN3/RB1
PGED1/AN0/CN2/RB0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PMD4/RE4
PMD3/RE3
PMD2/RE2
TRD0/RG13
TRD1/RG12
TRD2/RG14
PMD1/RE1
PMD0/RE0
TRD3/RA7
TRCLK/RA6
PMD8/RG0
PMD9/RG1
PMD10/RF1
PMD11/RF0
ENVREG
VCAP/VDDCORE
PMD15/CN16/RD7
PMD14/CN15/RD6
PMRD/CN14/RD5
PMWR/OC5/CN13/RD4
PMD13/CN19/RD13
PMD12/IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
100-Pin TQFP (USB)
DS61143F-page 8
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
Table of Contents
High-Performance 80 MHz MIPS-Based 32-bit Flash Microcontroller 64/100-Pin General Purpose and USB ..................................... 1
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 15
3.0 PIC32MX MCU........................................................................................................................................................................... 19
4.0 Memory Organization ................................................................................................................................................................. 25
5.0 Flash Program Memory.............................................................................................................................................................. 55
6.0 Resets ........................................................................................................................................................................................ 57
7.0 Interrupt Controller ..................................................................................................................................................................... 59
8.0 Oscillator Configuration .............................................................................................................................................................. 63
9.0 Prefetch Cache........................................................................................................................................................................... 65
10.0 Direct Memory Access (DMA) Controller ................................................................................................................................... 67
11.0 USB On-The-Go (OTG).............................................................................................................................................................. 69
12.0 I/O Ports ..................................................................................................................................................................................... 71
13.0 Timer1 ........................................................................................................................................................................................ 73
14.0 Timers 2, 3, 4, 5 ......................................................................................................................................................................... 75
15.0 Input Capture.............................................................................................................................................................................. 77
16.0 Output Compare......................................................................................................................................................................... 79
17.0 Serial Peripheral Interface (SPI)................................................................................................................................................. 81
18.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................... 83
19.0 Universal Asynchronous Receiver Transmitter (UART) ............................................................................................................. 85
20.0 Parallel Master Port (PMP)......................................................................................................................................................... 89
21.0 Real-Time Clock and Calendar (RTCC)..................................................................................................................................... 91
22.0 10-bit Analog-to-Digital Converter (ADC) ................................................................................................................................... 93
23.0 Comparator ................................................................................................................................................................................ 95
24.0 Comparator Voltage Reference (CVref) ..................................................................................................................................... 97
25.0 Power-Saving Features.............................................................................................................................................................. 99
26.0 Special Features ...................................................................................................................................................................... 101
27.0 Instruction Set .......................................................................................................................................................................... 113
28.0 Development Support............................................................................................................................................................... 121
28.0 Electrical Characteristics .......................................................................................................................................................... 119
29.0 Packaging Information.............................................................................................................................................................. 157
INDEX ................................................................................................................................................................................................ 167
Worldwide Sales and Service ............................................................................................................................................................ 170
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 9
PIC32MX3XX/4XX
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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DS61143F-page 10
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
1.0
DEVICE OVERVIEW
Note:
This document contains device-specific information for
the PIC32MX3XX/4XX devices.
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
appropriate section of the “PIC32MX
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32)
FIGURE 1-1:
Figure 1-1 shows a general block diagram of the core
and peripheral modules in the PIC32MX3XX/4XX families of devices.
Table 1-1 lists the functions of the various pins shown
in the pinout diagrams.
BLOCK DIAGRAM(1,2)
VDDCORE/VCAP
OSC2/CLKO
OSC1/CLKI
OSC/SOSC
Oscillators
Power-up
Timer
FRC/LPRC
Oscillators
ENVREG
Oscillator
Start-up Timer
Voltage
Regulator
PLL
PLL-USB
Watchdog
Timer
USBCLK
SYSCLK
Timing
Generation
MCLR
Power-on
Reset
Precision
Band Gap
Reference
DIVIDERS
VDD, VSS
Brown-out
Reset
PBCLK
Peripheral Bus Clocked by SYSCLK
CN1-22
PORTA
JTAG
BSCAN
Priority
Interrupt
Controller
EJTAG
INT
Timer1-5
PWM
OC 1-5
DMAC
USB
ICD
32
MIPS 32® M4K® CPU Core
PORTC
IS
32
DS
32
32
32
32
32
PORTD
Bus Matrix
32
32
IC 1-5
SPI 1,2
I2C 1,2
32
PORTE
Prefetch
Module
Peripheral Bus Clocked by PBCLK
PORTB
32
Data RAM
Peripheral Bridge
PMP
10-bit ADC
PORTF
128
128-bit wide
Program Flash Memory
PORTG
Note 1:
2:
Flash
Controller
UART 1,2
Some features are not available on all device variants.
RTCC
Comparators
BOR functionality is provided when the on-board voltage regulator is enabled.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 11
PIC32MX3XX/4XX
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS
Pin
Type
Buffer
Type
Analog
Description
AN0-AN15
I
CLKI
I
Analog input channels.
CLKO
O
OSC1
I
OSC2
I/O
SOSCI
SOSCO
I
O
CN0-CN21
I
ST
Change notification inputs.
Can be software programmed for internal weak pull-ups on all inputs.
IC1-IC5
I
ST
Capture inputs 1-5.
OCFA
OC1-OC5
OCFB
I
O
I
ST
—
ST
Compare Fault A input.
Compare outputs 1 through 5.
Output Compare Fault B Input.
INT0
INT1
INT2
INT3
INT4
I
I
I
I
I
ST
ST
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
External interrupt 3.
External interrupt 4.
RA0-RA15
I/O
ST
PORTA is a bidirectional I/O port.
RB0-RB15
I/O
ST
PORTB is a bidirectional I/O port.
RC0-RC15
I/O
ST
PORTC is a bidirectional I/O port.
RD0-RD15
I/O
ST
PORTD is a bidirectional I/O port.
RE0-RE15
I/O
ST
PORTE is a bidirectional I/O port.
RF0-RF15
I/O
ST
PORTF is a bidirectional I/O port.
RG0, RG1,
RG4-RG15
I/O
ST
PORTG is a bidirectional I/O port.
RG2, RG3
I
ST
PORTG input pins.
T1CK
T2CK
T3CK
T4CK
T5CK
I
I
I
I
I
ST
ST
ST
ST
ST
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
U1CTS
U1RTS
U1RX
U1TX
I
O
I
O
ST
—
ST
—
UART1 clear to send.
UART1 ready to send.
UART1 receive.
UART1 transmit.
U2CTS
U2RTS
U2RX
U2TX
I
O
I
O
ST
—
ST
—
UART2 clear to send.
UART2 ready to send.
UART2 receive.
UART2 transmit.
ST/CMOS External clock source input. Always associated with OSC1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
—
mode. Optionally functions as CLKO in RC and EC modes. Always associated
with OSC2 pin function.
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode;
CMOS otherwise.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise.
—
32.768 kHz low-power oscillator crystal output.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
DS61143F-page 12
Analog = Analog input
O = Output
Preliminary
P = Power
I = Input
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
SCK1
SDI1
SDO1
SS1
I/O
I
O
I/O
ST
ST
—
ST
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
SCK2
SDI2
SDO2
SS2
I/O
I
O
I/O
ST
ST
—
ST
Synchronous serial clock input/output for SPI2.
SPI2 data in.
SPI2 data out.
SPI2 slave synchronization or frame pulse I/O.
SCL1
SDA1
I/O
I/O
ST
ST
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
TMS
TCK
TDI
TDO
I
I
I
O
ST
ST
ST
—
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
RTCC
O
—
Real-Time Clock Alarm Output.
CVREF–
CVREF+
CVREFOUT
I
I
O
ANA
ANA
ANA
Comparator Voltage Reference (low).
Comparator Voltage Reference (high).
Comparator Voltage Reference Output.
C1INC1IN+
C1OUT
I
I
O
ANA
ANA
—
Comparator 1 Negative Input.
Comparator 1 Positive Input.
Comparator 1 Output.
C2INC2IN+
C2OUT
I
I
O
ANA
ANA
—
Comparator 2 Negative Input.
Comparator 2 Positive Input.
Comparator 2 Output.
PMA0
I/O
TTL/ST
PMA1
I/O
TTL/ST
PMA2-PMPA15
PMENB
PMCS1
PMCS2
PMD0-PMD15
O
O
O
O
I/O
—
—
—
—
TTL/ST
PMRD
PMWR
PMALL
O
O
O
—
—
—
PMALH
O
—
Pin Name
PMRD/PMWR
O
—
PMALL
O
—
PMALH
O
—
PMRD/PMWR
O
—
Description
Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output
(Master modes).
Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output
(Master modes).
Parallel Master Port Address (Demultiplexed Master Modes).
Parallel Master Port Enable Strobe (Master mode 1).
Parallel Master Port Chip Select 1 Strobe.
Parallel Master Port Chip Select 2 Strobe.
Parallel Master Port Data (Demultiplexed Master mode) or Address/Data
(Multiplexed Master modes).
Parallel Master Port Read Strobe.
Parallel Master Port Write Strobe.
Parallel Master Port Address Latch Enable low-byte (Multiplexed Master
modes).
Parallel Master Port Address Latch Enable high-byte (Multiplexed Master
modes).
Parallel Master Port Read/Write Strobe (Master mode 1).
Parallel Master Port Address Latch Enable low-byte (Multiplexed Master
modes).
Parallel Master Port Address Latch Enable high-byte (Multiplexed Master
modes).
Parallel Master Port Read/Write Strobe (Master mode 1).
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
© 2009 Microchip Technology Inc.
Analog = Analog input
O = Output
Preliminary
P = Power
I = Input
DS61143F-page 13
PIC32MX3XX/4XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
I
P
O
I/O
I/O
I
ANA
—
—
ANA
ANA
ST
ENVREG
I
ST
Enable for On-Chip Voltage Regulator.
TRCLK
TRD0-TRD3
O
O
—
—
Trace Clock.
Trace Data Bits 0-3
PGED1
PGEC1
PGED2
PGEC2
I/O
I
I/O
I
ST
ST
ST
ST
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
MCLR
I/P
ST
Master Clear (Reset) input. This pin is an active-low Reset to the device.
AVdd
P
P
Positive supply for analog modules. This pin must be connected at all times.
AVss
P
P
Ground reference for analog modules.
Vdd
P
—
Positive supply for peripheral logic and I/O pins.
Vcap/Vddcore
P
—
CPU logic filter capacitor connection.
Vss
P
—
Ground reference for logic and I/O pins.
VREF+
I
Analog
Analog voltage reference (high) input.
VREF-
I
Analog
Analog voltage reference (low) input.
Pin Name
VBUS
VUSB
VBUSON
D+
D–
USBID
Description
USB Bus Power Monitor.
USB Internal Transceiver Supply.
USB Host and OTG Bus Power Control Output.
USB D+.
USB D–.
USB OTG ID Detect.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
DS61143F-page 14
Analog = Analog input
O = Output
Preliminary
P = Power
I = Input
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
2.0
Note:
2.1
GUIDELINES FOR GETTING
STARTED WITH 32-BIT
MICROCONTROLLERS
2.2
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” for a detailed
description of the PIC32MX MCU.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
Basic Connection Requirements
Getting started with the PIC32MX3XX/4XX family of
32-bit Microcontrollers (MCU) requires attention to a
minimal set of device pin connections before
proceeding with development. The following is a list of
pin names, which must always be connected:
• All VDD and VSS pins
(see Section 2.2)
• All AVDD and AVSS pins (regardless if ADC module
is not used)
(see Section 2.2)
• VCAP/VDDCORE
(see Section 2.3)
• MCLR pin
(see Section 2.4)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.8)
Additionally, the following pins may be required:
• VREF+/VREF- pins used when external voltage
reference for ADC module is implemented
Note:
The AVDD and AVSS pins must be
connected independent of ADC use and
ADC voltage reference source.
© 2009 Microchip Technology Inc.
Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD, and
AVSS is required. See Figure 2-1.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within onequarter inch (6 mm) in length.
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
Preliminary
DS61143F-page 15
PIC32MX3XX/4XX
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
0.1 µF
Ceramic
CBP
R
R1
MCLR
C
PIC32MX
VSS
10 Ω
2.2.1
VDD
0.1 µF
Ceramic
CBP
VSS
VDD
AVSS
VDD
AVDD
0.1 µF
Ceramic
CBP
VSS
0.1 µF
Ceramic
CBP
0.1 µF
Ceramic
CBP
2.3.1
BULK CAPACITORS
Pulling The MCLR pin low generates a device reset.
Figure 2-2 shows a typical MCLR circuit. During
device programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R and C will need to be adjusted based on the
application and PCB requirements.
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
Capacitor on Internal Voltage
Regulator (VCAP/VDDCORE)
R
R1
INTERNAL REGULATOR MODE
A low-ESR (< 5 Ohms) capacitor is required on the
VCAP/VDDCORE pin, which is used to stabilize the
internal voltage regulator output. The VCAP/VDDCORE
pin must not be connected to VDD, and must have a
10 µF capacitor, with at least a 6V rating, connected to
ground. The type can be ceramic or tantalum. Refer to
Section 28.0 "Electrical Characteristics" for
additional information. This mode is enabled by
connecting the ENVREG pin to VDD.
2.3.2
The MCLR pin provides for two specific device
functions:
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
The use of a bulk capacitor is recommended to improve
power supply stability. Typical values range from 4.7 µF
to 47 µF. This capacitor should be located as close to
the device as possible.
2.3
Master Clear (MCLR) Pin
• Device Reset
• Device Programming and Debugging
VSS
VCAP/VDDCORE
VDD
VDD
2.4
JP
MCLR
PIC32MX
C
Note 1:
R ≤ 10 kΩ is recommended. A suggested
starting value is 10 kΩ. Ensure that the MCLR
pin VIH and VIL specifications are met.
2:
R1 ≤ 470Ω will limit any current flowing into
MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
3:
The capacitor can be sized to prevent unintentional resets from brief glitches or to extend the
device reset period during POR.
EXTERNAL REGULATOR MODE
In this mode the core voltage is supplied externally
through the VDDCORE pin. A low-ESR capacitor of
10 µF is recommended on the VDDCORE pin. This mode
is enabled by grounding the ENVREG pin.
The placement of this capacitor should be close to the
VCAP/VDDCORE. It is recommended that the trace
length not exceed one-quarter inch (6 mm). Refer to
Section 26.3 "On-Chip Voltage Regulator" for
details.
DS61143F-page 16
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
2.5
ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes, and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternately, refer to the AC/DC characteristics and timing requirements information in the respective device
Flash programming specification for information on
capacitive loading limits and pin input voltage high (VIH)
and input low (VIL) requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 2, MPLAB® ICD 3, or MPLAB® REAL
ICE™.
For more information on ICD 2, ICD 3, and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip website.
• “MPLAB® ICD 2 In-Circuit Debugger User's
Guide” DS51331
• “Using MPLAB® ICD 2” (poster) DS51265
• “MPLAB® ICD 2 Design Advisory” DS51566
• “Using MPLAB® ICD 3” (poster) DS51765
• “MPLAB® ICD 3 Design Advisory” DS51764
• “MPLAB® REAL ICE™ In-Circuit Debugger
User's Guide” DS51616
• “Using MPLAB® REAL ICE™” (poster) DS51749
2.6
JTAG
The TMS, TDO, TDI, and TCK pins are used for testing
and debugging according to the Joint Test Action
Group (JTAG) standard. It is recommended to keep the
trace length between the JTAG connector and the
JTAG pins on the device as short as possible. If the
JTAG connector is expected to experience an ESD
event, a series resistor is recommended, with the value
in the range of a few tens of Ohms, not to exceed 100
Ohms.
Pull-up resistors, series diodes, and capacitors on the
TMS, TDO, TDI, and TCK pins are not recommended
as they will interfere with the programmer/debugger
communications to the device. If such discrete components are an application requirement, they should be
removed from the circuit during programming and
debugging. Alternately, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for
information on capacitive loading limits and pin input
voltage high (VIH) and input low (VIL) requirements.
2.7
Trace
The trace pins can be connected to a hardware-traceenabled programmer to provide a compress real time
instruction trace. When used for trace the TRD3,
TRD2, TRD1, TRD0, and TRCLK pins should be dedicated for this use. The trace hardware requires a 22
Ohm series resistor between the trace pins and the
trace connector.
2.8
External Oscillator Pins
Many MCUs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 8.0 "Oscillator
Configuration" for details).
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
FIGURE 2-3:
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
Oscillator
Secondary
Guard Trace
Guard Ring
Main Oscillator
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 17
PIC32MX3XX/4XX
2.9
Configuration of Analog and
Digital Pins During ICSP
Operations
2.10
If MPLAB ICD 2, ICD 3, or REAL ICE is selected as a
debugger, it automatically initializes all of the A/D input
pins (ANx) as “digital” pins by setting all bits in the
ADPCFG register.
Unused I/Os
Unused I/O pins should not be allowed to float as
inputs. They can be configured as outputs and driven
to a logic-low state.
Alternately, inputs can be reserved by connecting the
pin to VSS through a 1k to 10k resistor and configuring
the pin as an input.
The bits in this register that correspond to the A/D pins
that are initialized by MPLAB ICD 2, ICD 3, or REAL
ICE, must not be cleared by the user application
firmware; otherwise, communication errors will result
between the debugger and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
ADPCFG register during initialization of the ADC
module.
When MPLAB ICD 2, ICD 3, or REAL ICE is used as a
programmer, the user application firmware must
correctly configure the ADPCFG register. Automatic
initialization of this register is only done during
debugger operation. Failure to correctly configure the
register(s) will result in all A/D pins being recognized as
analog input pins, resulting in the port value being read
as a logic '0', which may affect user application
functionality.
DS61143F-page 18
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
Note:
PIC32MX MCU
This data sheet summarizes the features of
the PIC32MX3XX/4XX Family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 2.
“MCU” (DS61113) for a detailed description
of the PIC32MX MCU. The manual is
available from the Microchip web site
(www.Microchip.com/PIC32). Resources for
the MIPS32® M4K® Processor Core are
available
at
www.mips.com/products/cores/32-bit-cores/ mips32-m4k/#.
The MCU module is the heart of the PIC32MX3XX/4XX
Family processor. The MCU fetches instructions,
decodes each instruction, fetches source operands,
executes each instruction, and writes the results of
instruction execution to the proper destinations.
3.1
Features
• 5-stage pipeline
• 32-bit Address and Data Paths
• MIPS32 Enhanced Architecture (Release 2)
- Multiply-Accumulate and Multiply-Subtract
Instructions
- Targeted Multiply Instruction
- Zero/One Detect Instructions
- WAIT Instruction
- Conditional Move Instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency
for interrupt handlers
- Bit field manipulation instructions
FIGURE 3-1:
• MIPS16e™ Code Compression
- 16-bit encoding of 32-bit instructions to
improve code density
- Special PC-relative instructions for efficient
loading of addresses and constants
- SAVE & RESTORE macro instructions for
setting up and tearing down stack frames
within subroutines
- Improved support for handling 8 and 16-bit
data types
• Simple Fixed Mapping Translation (FMT)
mechanism
• Simple Dual Bus Interface
- Independent 32-bit address and data busses
- Transactions can be aborted to improve
interrupt latency
• Autonomous Multiply/Divide Unit
- Maximum issue rate of one 32x16 multiply
per clock
- Maximum issue rate of one 32x32 multiply
every other clock
- Early-in iterative divide. Minimum 11 and
maximum 34 clock latency (dividend (rs) sign
extension-dependent)
• Power Control
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT
instruction)
- Extensive use of local gated clocks
• EJTAG Debug and Instruction Trace
- Support for single stepping
- Virtual instruction and data address/value
- breakpoints
- PC tracing with trace compression
MCU BLOCK DIAGRAM
EJTAG
Trace
TAP
MDU
Execution
Core
(RF/ALU/Shift)
FMT
Bus Interface
System
Coprocessor
© 2009 Microchip Technology Inc.
Trace I/F
Off-Chip
Debug I/F
Dual Bus I/F
Bus Matrix
3.0
Power
Mgmt
Preliminary
DS61143F-page 19
PIC32MX3XX/4XX
3.2
Architecture Overview
3.2.2
The PIC32MX3XX/4XX Family core contains several
logic blocks working together in parallel, providing an
efficient high performance computing engine. The following blocks are included with the core:
• Execution Unit
• Multiply/Divide Unit (MDU)
• System Control Coprocessor (CP0)
• Fixed Mapping Translation (FMT)
• Dual Internal Bus interfaces
• Power Management
• MIPS16e Support
• Enhanced JTAG (EJTAG) Controller
3.2.1
EXECUTION UNIT
The PIC32MX3XX/4XX Family core execution unit
implements a load/store architecture with single-cycle
ALU operations (logical, shift, add, subtract) and an
autonomous multiply/divide unit. The core contains
thirty-two 32-bit general purpose registers used for
integer operations and address calculation. One additional register file shadow set (containing thirty-two registers) is added to minimize context switching overhead
during interrupt/exception processing. The register file
consists of two read ports and one write port and is fully
bypassed to minimize operation latency in the pipeline.
The execution unit includes:
• 32-bit adder used for calculating the data address
• Address unit for calculating the next instruction
address
• Logic for branch determination and branch target
address calculation
• Load aligner
• Bypass multiplexers used to avoid stalls when
executing instructions streams where data
producing instructions are followed closely by
consumers of their results
• Leading Zero/One detect unit for implementing the
CLZ and CLO instructions
MULTIPLY/DIVIDE UNIT (MDU)
The PIC32MX3XX/4XX Family core includes a multiply/divide unit (MDU) that contains a separate pipeline
for multiply and divide operations. This pipeline operates in parallel with the integer unit (IU) pipeline and
does not stall when the IU pipeline stalls. This allows
MDU operations to be partially masked by system stalls
and/or other integer unit instructions.
The high-performance MDU consists of a 32x16 booth
recoded multiplier, result/accumulation registers (HI
and LO), a divide state machine, and the necessary
multiplexers and control logic. The first number shown
(‘32’ of 32x16) represents the rs operand. The second
number (‘16’ of 32x16) represents the rt operand. The
PIC32MX core only checks the value of the latter (rt)
operand to determine how many times the operation
must pass through the multiplier. The 16x16 and 32x16
operations pass through the multiplier once. A 32x32
operation passes through the multiplier twice.
The MDU supports execution of one 16x16 or 32x16
multiply operation every clock cycle; 32x32 multiply
operations can be issued every other clock cycle.
Appropriate interlocks are implemented to stall the
issuance of back-to-back 32x32 multiply operations.
The multiply operand size is automatically determined
by logic built into the MDU.
Divide operations are implemented with a simple 1 bit
per clock iterative algorithm. An early-in detection
checks the sign extension of the dividend (rs) operand.
If rs is 8 bits wide, 23 iterations are skipped. For a 16bit-wide rs, 15 iterations are skipped, and for a 24-bitwide rs, 7 iterations are skipped. Any attempt to issue
a subsequent MDU instruction while a divide is still
active causes an IU pipeline stall until the divide operation is completed.
Table 3-1 lists the repeat rate (peak issue rate of cycles
until the operation can be reissued) and latency (number of cycles until a result is available) for the PIC32MX
core multiply and divide instructions. The approximate
latency and repeat rates are listed in terms of pipeline
clocks.
• Arithmetic Logic Unit (ALU) for performing bitwise
logical operations
• Shifter and Store Aligner
DS61143F-page 20
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 3-1:
PIC32MX3XX/4XX FAMILY CORE HIGH-PERFORMANCE INTEGER
MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES
Opcode
Operand Size (mul rt) (div rs)
Latency
Repeat Rate
MULT/MULTU, MADD/MADDU,
MSUB/MSUBU
16 bits
1
1
32 bits
2
2
MUL
16 bits
2
1
32 bits
3
2
DIV/DIVU
8 bits
12
11
16 bits
19
18
24 bits
26
25
33
32
32 bits
The MIPS architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be
transferred to the general purpose register file.
In addition to the HI/LO targeted operations, the
MIPS32 architecture also defines a multiply instruction,
MUL, which places the least significant results in the
primary register file instead of the HI/LO register pair.
By avoiding the explicit MFLO instruction, required
when using the LO register, and by supporting multiple
destination registers, the throughput of multiply-intensive operations is increased.
Two other instructions, multiply-add (MADD) and multiply-subtract (MSUB), are used to perform the multiplyaccumulate and multiply-subtract operations. The
MADD instruction multiplies two numbers and then adds
TABLE 3-2:
the product to the current contents of the HI and LO
registers. Similarly, the MSUB instruction multiplies two
operands and then subtracts the product from the HI
and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
3.2.3
SYSTEM CONTROL
COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the virtual-to-physical address translation, the exception control system, the processor’s diagnostics capability, the
operating modes (kernel, user, and debug), and
whether interrupts are enabled or disabled. Configuration information, such as presence of options like
MIPS16e, is also available by accessing the CP0 registers, listed in Table 3-2.
COPROCESSOR 0 REGISTERS
Register Register
Number Name
Function
0-6
Reserved
Reserved in the PIC32MX3XX/4XX Family core
7
HWREna
Enables access via the RDHWR instruction to selected hardware registers
8
BadVAddr(1)
Reports the address for the most recent address-related exception
Processor cycle count
9
Count(1)
10
Reserved
Reserved in the PIC32MX3XX/4XX Family core
11
Compare(1)
Timer interrupt control
12
Status(1)
Processor status and control
12
IntCtl(1)
Interrupt system status and control
12
SRSCtl(1)
Shadow register set status and control
12
SRSMap(1)
Provides mapping from vectored interrupt to a shadow set
13
Cause(1)
Cause of last general exception
14
EPC(1)
Program counter at last exception
15
PRId
Processor identification and revision
15
EBASE
Exception vector base register
16
Config
Configuration register
16
Config1
Configuration register 1
16
Config2
Configuration register 2
16
Config3
Configuration register 3
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 21
PIC32MX3XX/4XX
TABLE 3-2:
COPROCESSOR 0 REGISTERS (CONTINUED)
Register Register
Number Name
Function
17-22
Reserved
Reserved in the PIC32MX3XX/4XX Family core
23
Debug(2)
Debug control and exception status
24
DEPC(2)
Program counter at last debug exception
25-29
Reserved
Reserved in the PIC32MX3XX/4XX Family core
30
ErrorEPC(1)
Program counter at last error
31
DESAVE(2)
Debug handler scratchpad register
Note 1:
2:
Registers used in exception processing.
Registers used during debug.
Coprocessor 0 also contains the logic for identifying
and managing exceptions. Exceptions can be caused
by a variety of sources, including alignment errors in
data, external events, or program errors. Table 3-3
shows the exception types in order of priority.
TABLE 3-3:
PIC32MX3XX/4XX FAMILY CORE EXCEPTION TYPES
Exception
Description
Reset
Assertion MCLR or a Power-On Reset (POR)
DSS
EJTAG Debug Single Step
DINT
EJTAG Debug Interrupt. Caused by the assertion of the external EJ_DINT input, or by setting the
EjtagBrk bit in the ECR register
NMI
Interrupt
DIB
AdEL
Assertion of NMI signal
Assertion of unmasked hardware or software interrupt signal
EJTAG debug hardware instruction break matched
Fetch address alignment error
Fetch reference to protected address
IBE
Instruction fetch bus error
DBp
EJTAG Breakpoint (execution of SDBBP instruction)
Sys
Execution of SYSCALL instruction
Bp
Execution of BREAK instruction
RI
Execution of a Reserved Instruction
CpU
Execution of a coprocessor instruction for a coprocessor that is not enabled
CEU
Execution of a CorExtend instruction when CorExtend is not enabled
Ov
Tr
DDBL / DDBS
Execution of an arithmetic instruction that overflowed
Execution of a trap (when trap condition is true)
EJTAG Data Address Break (address only) or EJTAG Data Value Break on Store (address + value)
AdEL
Load address alignment error
Load reference to protected address
AdES
Store address alignment error
Store to protected address
DBE
Load or store bus error
DDBL
DS61143F-page 22
EJTAG data hardware breakpoint matched in load data compare
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
3.3
Power Management
3.4
The PIC32MX3XX/4XX Family core offers a number of
power management features, including low-power
design, active power management, and power-down
modes of operation. The core is a static design that
supports slowing or halting the clocks, which reduces
system power consumption during idle periods.
3.3.1
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
The mechanism for invoking power-down mode is
through execution of the WAIT instruction. For more
information on power management, see Section 25.0
“Power-Saving Features”.
3.3.2
LOCAL CLOCK GATING
The majority of the power consumed by the
PIC32MX3XX/4XX Family core is in the clock tree and
clocking registers. The PIC32MX family uses extensive
use of local gated-clocks to reduce this dynamic power
consumption.
© 2009 Microchip Technology Inc.
EJTAG Debug Support
The PIC32MX3XX/4XX Family core provides for an
Enhanced JTAG (EJTAG) interface for use in the
software debug of application and kernel code. In
addition to standard user mode and kernel modes of
operation, the PIC32MX3XX/4XX Family core provides
a Debug mode that is entered after a debug exception
(derived from a hardware breakpoint, single-step
exception, etc.) is taken and continues until a debug
exception return (DERET) instruction is executed.
During this time, the processor executes the debug
exception handler routine.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for
transferring test data in and out of the
PIC32MX3XX/4XX Family core. In addition to the
standard JTAG instructions, special instructions
defined in the EJTAG specification define what
registers are selected and how they are used.
Preliminary
DS61143F-page 23
PIC32MX3XX/4XX
NOTES:
DS61143F-page 24
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
4.0
Note:
MEMORY ORGANIZATION
4.1
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 3.
“Memory Organization” (DS61115) for a
detailed description of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
PIC32MX3XX/4XX Memory Layout
PIC32MX3XX/4XX microcontrollers implement two
address spaces: Virtual and Physical. All hardware
resources such as program memory, data memory, and
peripherals are located at their respective physical
addresses. Virtual addresses are exclusively used by
the CPU to fetch and execute instructions as well as
access peripherals. Physical addresses are used by
peripherals such as DMA and Flash controller that
access memory independently of CPU.
PIC32MX3XX/4XX microcontrollers provide 4 GB of
unified virtual memory address space. All memory
regions including program, data memory, SFRs, and
Configuration registers reside in this address space at
their respective unique addresses. The program and
data memories can be optionally partitioned into user
and kernel memories. In addition, the data memory can
be made executable, allowing PIC32MX3XX/4XX to
execute from data memory.
Key Features:
•
•
•
•
•
•
•
•
32-bit native data width
Separate User and Kernel mode address space
Flexible program Flash memory partitioning
Flexible data RAM partitioning for data and
program space
Separate boot Flash memory for protected code
Robust bus exception handling to intercept
runaway code.
Simple memory mapping with Fixed Mapping
Translation (FMT) unit
Cacheable and non-cacheable address regions
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 25
PIC32MX3XX/4XX
FIGURE 4-1:
MEMORY MAP ON RESET FOR PIC32MX320F032H, PIC32MX420F032H
DEVICES(1)
Virtual
Memory Map
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xBFC02FF0
Physical
Memory Map
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
SFRs
0xBF800000
0xBD008000
Reserved
KSEG1
0xBF8FFFFF
Reserved
0xBD007FFF
Program Flash(2)
0xBD000000
0xA0002000
Reserved
0xA0001FFF
RAM(2)
0xA0000000
0x9FC02FF0
0x9FC02FFF
0x9FC02FEF
0x1FC03000
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC02FFF
0x1FC02FF0
0x1FC02FEF
Boot Flash
0x9FC02FEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x9D008000
0x9D007FFF
Program Flash(2)
KSEG0
0x1F8FFFFF
Reserved
SFRs
0x1F800000
Reserved
0x9D000000
0x80002000
0x1D008000
0x1D007FFF
Reserved
Program Flash(2)
0x1D000000
0x80001FFF
RAM(2)
Reserved
0x80000000
0x00000000
Note 1:
2:
DS61143F-page 26
RAM(2)
Reserved
0x00002000
0x00001FFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS61115)) and can be changed by initialization code provided by end-user development
tools (refer to the specific development tool documentation for information).
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 4-2:
MEMORY MAP ON RESET FOR PIC32MX320F064H DEVICES(1)
Virtual
Memory Map
0xFFFFFFFF
Physical
Memory Map
0xFFFFFFFF
Reserved
0xBFC03000
0xBFC02FFF
Device
Configuration
Registers
0xBFC02FF0
0xBFC02FEF
Boot Flash
0xBFC00000
Reserved
0xBF900000
SFRs
0xBF800000
Reserved
0xBD010000
KSEG1
0xBF8FFFFF
Reserved
0xBD00FFFF
Program Flash(2)
0xBD000000
Reserved
0xA0004000
0xA0003FFF
RAM(2)
0xA0000000
0x1FC03000
Device
Configuration
Registers
Reserved
0x9FC02FF0
0x9FC02FFF
Device
Configuration
Registers
0x9FC02FEF
0x1FC02FFF
0x1FC02FF0
0x1FC02FEF
Boot Flash
0x9FC02FEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x9D010000
0x9D00FFFF
Program Flash(2)
KSEG0
0x1F8FFFFF
Reserved
SFRs
0x1F800000
Reserved
0x9D000000
0x80004000
0x1D010000
0x1D00FFFF
Reserved
Program Flash(2)
0x1D000000
0x80003FFF
RAM(2)
Reserved
0x80000000
0x00000000
Note 1:
2:
Reserved
RAM
(2)
0x00004000
0x00003FFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS61115)) and can be changed by initialization code provided by end-user development
tools (refer to the specific development tool documentation for information).
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 27
PIC32MX3XX/4XX
FIGURE 4-3:
MEMORY MAP ON RESET FOR PIC32MX320F128H, PIC32MX320F128L
DEVICES(1)
Virtual
Memory Map
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xBFC02FF0
Physical
Memory Map
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
SFRs
0xBF800000
0xBD020000
Reserved
KSEG1
0xBF8FFFFF
Reserved
0xBD01FFFF
Program Flash(2)
0xBD000000
0xA0004000
Reserved
0xA0003FFF
RAM(2)
0xA0000000
0x9FC02FF0
0x9FC02FFF
0x9FC02FEF
0x1FC03000
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC02FFF
0x1FC02FF0
0x1FC02FEF
Boot Flash
0x9FC02FEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x9D020000
0x9D01FFFF
Program Flash(2)
KSEG0
0x1F8FFFFF
Reserved
SFRs
0x1F800000
Reserved
0x9D000000
0x80004000
0x1D020000
0x1D01FFFF
Reserved
Program Flash(2)
0x1D000000
0x80003FFF
RAM(2)
Reserved
0x80000000
0x00000000
Note 1:
2:
DS61143F-page 28
RAM(2)
Reserved
0x00004000
0x00003FFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS61115)) and can be changed by initialization code provided by end-user development
tools (refer to the specific development tool documentation for information).
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 4-4:
MEMORY MAP ON RESET FOR PIC32MX340F128H, PIC32MX340F128L,
PIC32MX440F128H, PIC32MX440F128L DEVICES(1)
Virtual
Memory Map
0xFFFFFFFF
Physical
Memory Map
0xFFFFFFFF
Reserved
0xBFC03000
0xBFC02FFF
Device
Configuration
Registers
0xBFC02FF0
0xBFC02FEF
Boot Flash
0xBFC00000
Reserved
0xBF900000
SFRs
0xBF800000
Reserved
0xBD020000
KSEG1
0xBF8FFFFF
Reserved
0xBD01FFFF
Program Flash(2)
0xBD000000
Reserved
0xA0008000
0xA0007FFF
RAM(2)
0xA0000000
0x1FC03000
Device
Configuration
Registers
Reserved
0x9FC02FF0
0x9FC02FFF
Device
Configuration
Registers
0x9FC02FEF
0x1FC02FFF
0x1FC02FF0
0x1FC02FEF
Boot Flash
0x9FC02FEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x9D020000
0x9D01FFFF
Program Flash(2)
KSEG0
0x1F8FFFFF
Reserved
SFRs
0x1F800000
Reserved
0x9D000000
0x80008000
0x1D020000
0x1D01FFFF
Reserved
Program Flash(2)
0x1D000000
0x80007FFF
RAM(2)
Reserved
0x80000000
0x00000000
Note 1:
2:
RAM(2)
Reserved
0x00008000
0x00007FFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS61115)) and can be changed by initialization code provided by end-user development
tools (refer to the specific development tool documentation for information).
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 29
PIC32MX3XX/4XX
FIGURE 4-5:
MEMORY MAP ON RESET FOR PIC32MX340F256H, PIC32MX360F256L,
PIC32MX440F256H, PIC32MX460F256L DEVICES(1)
Virtual
Memory Map
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xBFC02FF0
Physical
Memory Map
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
SFRs
0xBF800000
0xBD040000
Reserved
KSEG1
0xBF8FFFFF
Reserved
0xBD03FFFF
Program Flash(2)
0xBD000000
0xA0008000
Reserved
0xA0007FFF
RAM(2)
0xA0000000
0x9FC02FF0
0x9FC02FFF
0x9FC02FEF
0x1FC03000
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC02FFF
0x1FC02FF0
0x1FC02FEF
Boot Flash
0x9FC02FEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x9D040000
0x9D03FFFF
Program Flash(2)
KSEG0
0x1F8FFFFF
Reserved
SFRs
0x1F800000
Reserved
0x9D000000
0x80008000
0x1D040000
0x1D03FFFF
Reserved
Program Flash(2)
0x1D000000
0x80007FFF
RAM(2)
Reserved
0x80000000
0x00000000
Note 1:
2:
DS61143F-page 30
RAM(2)
Reserved
0x00008000
0x00007FFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS61115)) and can be changed by initialization code provided by end-user development
tools (refer to the specific development tool documentation for information).
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 4-6:
MEMORY MAP ON RESET FOR PIC32MX340F512H, PIC32MX360F512L,
PIC32MX440F512H, PIC32MX460F512L DEVICES(1)
Virtual
Memory Map
0xFFFFFFFF
Physical
Memory Map
0xFFFFFFFF
Reserved
0xBFC03000
0xBFC02FFF
Device
Configuration
Registers
0xBFC02FF0
0xBFC02FEF
Boot Flash
0xBFC00000
Reserved
0xBF900000
SFRs
0xBF800000
Reserved
0xBD080000
KSEG1
0xBF8FFFFF
Reserved
0xBD07FFFF
Program Flash(2)
0xBD000000
Reserved
0xA0008000
0xA0007FFF
RAM(2)
0xA0000000
0x1FC03000
Device
Configuration
Registers
Reserved
0x9FC02FF0
0x9FC02FFF
Device
Configuration
Registers
0x9FC02FEF
0x1FC02FFF
0x1FC02FF0
0x1FC02FEF
Boot Flash
0x9FC02FEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x9D080000
0x9D07FFFF
Program Flash(2)
KSEG0
0x1F8FFFFF
Reserved
SFRs
0x1F800000
Reserved
0x9D000000
0x80008000
0x1D080000
0x1D07FFFF
Reserved
Program Flash(2)
0x1D000000
0x80007FFF
RAM(2)
Reserved
0x80000000
0x00000000
Note 1:
2:
RAM(2)
Reserved
0x00008000
0x00007FFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS61115)) and can be changed by initialization code provided by end-user development
tools (refer to the specific development tool documentation for information).
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 31
PIC32MX3XX/4XX
4.1.1
PERIPHERAL REGISTERS
LOCATIONS
Table 4-1 through Table 4-25 contain the peripheral
address maps for the PIC32MX3XX/4XX device. Peripherals located on the PB Bus are mapped to 512
byte boundaries. Peripherals on the FPB Bus are
mapped to 4 Kbyte boundaries.
DS61143F-page 32
Preliminary
© 2009 Microchip Technology Inc.
© 2009 Microchip Technology Inc.
TABLE 4-1:
SFR
Virtual
Addr
BUS MATRIX REGISTERS MAP
SFR
Name
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
31:16
—
—
—
—
—
BMX
CHEDMA
—
—
—
—
—
BMX
ERRIXI
BMX
ERRICD
BMX
ERRDMA
BMX
ERRDS
BMX
ERRIS
15:0
—
—
—
—
—
—
—
—
—
BMX
WSDRM
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF88_2000 BMXCON(1)
BF88_2010
BMX
DKPBA(1)
31:16
BF88_2020
BMX
DUDBA(1)
31:16
15:0
—
BF88_2030
BMX
DUPBA(1)
31:16
—
15:0
BF88_2050
Preliminary
Legend:
Note 1:
BMX
BOOTSZ
—
—
—
—
—
—
BMXDUDBA<15:0>
—
—
—
—
—
—
—
—
BMXDUPBA<15:0>
BMXDRMSZ<31:0>
15:0
—
—
—
—
—
—
—
15:0
—
—
BMXPUPBA<19:16>
BMXPUPBA<15:0>
31:16
BMXPFMSZ<31:0>
15:0
31:16
SFR
Name
BF88_1000
INTCON
BF88_1010
INTSTAT
BF88_1020
IPTMR
BF88_1030
IFS0
BF88_1040
IFS1
INTERRUPT REGISTERS MAP(1)
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
—
31:16
—
—
—
—
—
15:0
—
FRZ
—
MVEC
—
31:16
—
—
—
—
—
15:0
—
—
—
—
—
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
—
—
—
—
—
—
—
—
—
SS0
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
—
—
—
—
—
—
—
—
—
—
TRC<2:0>
—
—
—
RIPL<2:0>
31:16
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
VEC<5:0>
IPTMR<31:0>
15:0
31:16
I2C1MIF
I2C1SIF
I2C1BIF
U1TXIF
U1RXIF
U1EIF
SPI1RXIF
SPI1TXIF
SPI1EIF
OC5IF
IC5IF
T5IF
INT4IF
OC4IF
IC4IF
T4IF
15:0
INT3IF
OC3IF
IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
INT1IF
OC1IF
IC1IF
T1IF
INT0IF
CS1IF
CS0IF
CTIF
31:16
—
—
—
—
—
—
USBIF(4)
FCEIF
—
—
—
—
DMA3IF(2) DMA2IF(2) DMA1IF(2) DMA0IF(2)
15:0 RTCCIF
FSCMIF
I2C2MIF
I2C2SIF
I2C2BIF
U2TXIF
U2RXIF
U2EIF SPI2RXIF(3) SPI2TXIF(3) SPI2EIF(3) CMP2IF
CMP1IF
PMPIF
AD1IF
CNIF
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
These bits are not present on PIC32MX320FXXXX/420FXXXX devices.
These bits are not present on PIC32MX420FXXXX/440FXXXX devices.
These bits are not present on PIC32MX320FXXXX/340FXXXX/360FXXXX devices.
PIC32MX3XX/4XX
DS61143F-page 33
SFR
Virtual
Addr
2:
3:
4:
—
BMXBOOTSZ<31:0>
15:0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
TABLE 4-2:
Legend:
Note 1:
—
31:16
31:16
BMX
PUPBA(1)
BF88_2060 BMXPFMSZ
BF88_2070
BMXDKPBA<15:0>
15:0
BF88_2040 BMXDRMSZ
BMXARB<2:0>
SFR
Virtual
Addr
SFR
Name
BF88_1060
IEC0
BF88_1070
IEC1
BF88_1090
BF88_10A0
BF88_10B0
BF88_10C0
BF88_10D0
Preliminary
BF88_10E0
BF88_10F0
BF88_1100
BF88_1110
IPC0
IPC1
IPC2
IPC3
IPC4
IPC5
IPC6
IPC7
IPC8
BF88_1120
IPC9
BF88_1140
IPC11
Legend:
Note 1:
© 2009 Microchip Technology Inc.
2:
3:
4:
INTERRUPT REGISTERS MAP(1) (CONTINUED)
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
31:16
I2C1MIE
I2C1SIE
I2C1BIE
U1TXIE
U1RXIE
U1EIE
SPI1EIE
OC5IE
IC5IE
15:0
INT3IE
OC3IE
IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
INT1IE
OC1IE
IC1IE
31:16
—
—
—
—
—
—
USBIE
FCEIE
—
—
—
—
SPI2EIE(3)
CMP2IE
15:0
RTCCIE
FSCMIE
I2C2MIE
31:16
—
—
—
I2C2SIE
I2C2BIE
Bits
26/10
U2TXIE
INT0IP<2:0>
Bits
25/9
Bits
24/8
SPI1RXIE SPI1TXIE
U2RXIE
U2EIE
Bits
23/7
Bits
22/6
SPI2RXIE(3) SPI2TXIE(3)
Bits
21/5
INT0IS<1:0>
—
—
—
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
T5IE
INT4IE
OC4IE
IC4IE
T4IE
T1IE
INT0IE
CS1IE
CS0IE
CTIE
DMA3IE(2) DMA2IE(2) DMA1IE(2) DMA0IE(2)
CMP1IE
PMPIE
CS1IP<2:0>
AD1IE
CNIE
CS1IS<1:0>
15:0
—
—
—
CS0IP<2:0>
CS0IS<1:0>
—
—
—
CTIP<2:0>
CTIS<1:0>
31:16
—
—
—
INT1IP<2:0>
INT1IS<1:0>
—
—
—
OC1IP<2:0>
OC1IS<1:0>
15:0
—
—
—
IC1IP<2:0>
IC1IS<1:0>
—
—
—
T1IP<2:0>
T1IS<1:0>
31:16
—
—
—
INT2IP<2:0>
INT2IS<1:0>
—
—
—
OC2IP<2:0>
OC2IS<1:0>
15:0
—
—
—
IC2IP<2:0>
IC2IS<1:0>
—
—
—
T2IP<2:0>
T2IS<1:0>
31:16
—
—
—
INT3IP<2:0>
INT3IS<1:0>
—
—
—
OC3IP<2:0>
OC3IS<1:0>
15:0
—
—
—
IC3IP<2:0>
IC3IS<1:0>
—
—
—
T3IP<2:0>
T3IS<1:0>
31:16
—
—
—
INT4IP<2:0>
INT4IS<1:0>
—
—
—
OC4IP<2:0>
OC4IS<1:0>
15:0
—
—
—
IC4IP<2:0>
IC4IS<1:0>
—
—
—
T4IP<2:0>
T4IS<1:0>
31:16
—
—
—
SPI1IP<2:0>
SPI1IS<1:0>
—
—
—
OC5IP<2:0>
OC5IS<1:0>
15:0
—
—
—
IC5IP<2:0>
IC5IS<1:0>
—
—
—
T5IP<2:0>
T5IS<1:0>
31:16
—
—
—
AD1IP<2:0>
AD1IS<1:0>
—
—
—
CNIP<2:0>
CNIS<1:0>
15:0
—
—
—
I2C1IP<2:0>
I2C1IS<1:0>
—
—
—
U1IP<2:0>
U1IS<1:0>
31:16
—
—
—
SPI2IP<2:0>(3)
SPI2IS<1:0>(3)
—
—
—
CMP2IP<2:0>
CMP2IS<1:0>
15:0
—
—
—
CMP1IP<2:0>
CMP1IS<1:0>
—
—
—
PMPIP<2:0>
PMPIS<1:0>
31:16
—
—
—
RTCCIP<2:0>
RTCCIS<1:0>
—
—
—
FSCMIP<2:0>
FSCMIS<1:0>
15:0
—
—
—
I2C2IP<2:0>
I2C2IS<1:0>
—
—
—
U2IP<2:0>
U2IS<1:0>
31:16
—
—
—
DMA3IP<2:0>(2)
DMA3IS<1:0>(2)
—
—
—
DMA2IP<2:0>(2)
DMA2IS<1:0>(2)
15:0
—
—
—
DMA1IP<2:0>(2)
DMA1IS<1:0>(2)
—
—
—
DMA0IP<2:0>(2)
DMA0IS<1:0>(2)
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
USBIP<2:0>(4)
USBIS<1:0>(4)
—
—
—
FCEIP<2:0>
FCEIS<1:0>
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
These bits are not present on PIC32MX320FXXXX/420FXXXX devices.
These bits are not present on PIC32MX420FXXXX/440FXXXX devices.
These bits are not present on PIC32MX320FXXXX/340FXXXX/360FXXXX devices.
PIC32MX3XX/4XX
DS61143F-page 34
TABLE 4-2:
© 2009 Microchip Technology Inc.
TABLE 4-3:
SFR
Virtual
Addr
SFR
Name
BF80_0600
T1CON
BF80_0610
TMR1
BF80_0620
PR1
BF80_0800
T2CON
BF80_0810
TMR2
BF80_0820
PR2
BF80_0A00
T3CON
Preliminary
BF80_0A10
TMR3
BF80_0A20
PR3
BF80_0C00
T4CON
TMR4
BF80_0C20
PR4
BF80_0E00
T5CON
BF80_0E10
TMR5
BF80_0E20
PR5
Legend:
Note 1:
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
TWDIS
TWIP
—
—
—
TGATE
—
TCKPS<1:0>
—
TSYNC
TCS
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
TMR1<15:0>
—
—
—
—
—
—
—
15:0
—
—
PR1<15:0>
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
TGATE
31:16
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
TGATE
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
TCS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TCS
—
—
TCKPS<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TMR3<15:0>
—
—
—
—
—
—
—
15:0
—
—
PR3<15:0>
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
TGATE
31:16
—
—
—
—
—
—
—
—
—
15:0
—
TCKPS<2:0>
—
—
—
—
T32
—
TCS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TCS
—
TMR4<15:0>
—
—
—
—
—
—
—
15:0
—
—
PR4<15:0>
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
TGATE
31:16
—
—
—
—
—
—
—
—
—
15:0
31:16
—
T32
PR2<15:0>
31:16
31:16
TCKPS<2:0>
TMR2<15:0>
15:0
31:16
—
—
TCKPS<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TMR5<15:0>
—
—
—
—
—
—
—
—
—
15:0
PR5<15:0>
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
DS61143F-page 35
PIC32MX3XX/4XX
BF80_0C10
TIMER1-5 REGISTERS MAP(1)
SFR
Virtual
Addr
SFR
Name
BF80_2000 IC1CON(1)
BF80_2010
IC1BUF
BF80_2200 IC2CON(1)
BF80_2210
IC2BUF
BF80_2400 IC3CON(1)
BF80_2410
IC3BUF
BF80_2600 IC4CON(1)
Preliminary
BF80_2610
IC4BUF
BF80_2800 IC5CON(1)
BF80_2810
Legend:
Note 1:
IC5BUF
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
—
—
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
ICFEDGE
ICC32
ICTMR
31:16
ICI<1:0>
Bits
20/4
Bits
19/3
Bits
18/2
—
—
—
ICOV
ICBNE
Bits
17/1
Bits
16/0
—
—
ICM<2:0>
IC1BUF<31:0>
15:0
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
ICFEDGE
ICC32
ICTMR
31:16
—
—
ICI<1:0>
—
—
ICOV
ICBNE
—
—
—
ICM<2:0>
IC2BUF<31:0>
15:0
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
ICFEDGE
ICC32
ICTMR
31:16
—
—
ICI<1:0>
—
—
ICOV
ICBNE
—
—
—
ICM<2:0>
IC3BUF<31:0>
15:0
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
ICFEDGE
ICC32
ICTMR
31:16
—
—
ICI<1:0>
—
—
ICOV
ICBNE
—
—
—
ICM<2:0>
IC4BUF<31:0>
15:0
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
ICFEDGE
ICC32
ICTMR
—
—
ICI<1:0>
—
—
ICOV
ICBNE
—
—
—
ICM<2:0>
31:16
IC5BUF<31:0>
15:0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
TABLE 4-5:
© 2009 Microchip Technology Inc.
SFR
Virtual
Addr
SFR
Name
BF80_3000
OC1CON
BF80_3010
OC1R
BF80_3020
OC1RS
BF80_3200
OC2CON
BF80_3210
OC2R
Legend:
Note 1:
INPUT CAPTURE1-5 REGISTERS MAP
OUTPUT COMPARE 1-5 REGISTERS MAP(1)
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
Bits
16/0
—
—
OCM<2:0>
OC1R<31:0>
15:0
31:16
15:0
OC1RS<31:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
Bits
17/1
—
—
—
OCM<2:0>
OC2R<31:0>
15:0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
PIC32MX3XX/4XX
DS61143F-page 36
TABLE 4-4:
© 2009 Microchip Technology Inc.
TABLE 4-5:
SFR
Virtual
Addr
SFR
Name
BF80_3220
OC2RS
BF80_3400
OC3CON
BF80_3410
OC3R
BF80_3420
OC3RS
Preliminary
BF80_3600
OC4CON
BF80_3610
OC4R
BF80_3620
OC4RS
BF80_3800
OC5CON
BF80_3810
OC5R
BF80_3820
OC5RS
Legend:
Note 1:
OUTPUT COMPARE 1-5 REGISTERS MAP(1) (CONTINUED)
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
31:16
15:0
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
—
Bits
17/1
Bits
16/0
—
—
OC2RS<31:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
OCM<2:0>
OC3R<31:0>
15:0
31:16
15:0
OC3RS<31:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
—
—
—
OCM<2:0>
OC4R<31:0>
15:0
31:16
15:0
OC4RS<31:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
—
—
—
OCM<2:0>
OC5R<31:0>
15:0
31:16
SFR
Name
BF80_5000
I2C1CON
BF80_5010
I2C1STAT
BF80_5020
I2C1ADD
BF80_5030
I2C1MSK
I2C1BRG
I2C1-2 REGISTERS MAP(1)
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
ADD<9:0>
—
—
—
—
—
—
MSK<9:0>
—
—
—
—
—
—
—
—
—
—
I2C1BRG<11:0>
15:0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except I2CxRCV have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
PIC32MX3XX/4XX
DS61143F-page 37
SFR
Virtual
Addr
Legend:
Note 1:
Bits
30/14
OC5RS<31:0>
15:0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
TABLE 4-6:
BF80_5040
Bits
31/15
SFR
Virtual
Addr
SFR
Name
BF80_5050
I2C1TRN
BF80_5260
I2C1RCV
BF80_5200
I2C2CON
BF80_5210
I2C2STAT
BF80_5220
I2C2ADD
BF80_5230
I2C2MSK
BF80_5240
I2C2BRG
Preliminary
BF80_5250
I2C2TRN
BF80_5260
I2C2RCV
Legend:
Note 1:
© 2009 Microchip Technology Inc.
U1STA(1)
BF80_6030 U1RXREG
U1BRG(1)
BF80_6200 U2MODE(1)
Legend:
Note 1:
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
—
—
—
—
—
—
—
—
I2CT1DATA<7:0>
—
—
—
—
—
I2CR1DATA<7:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
SFR
Name
BF80_6020 U1TXREG
BF80_6040
Bits
30/14
ADD<9:0>
—
—
—
—
—
—
MSK<9:0>
—
—
—
—
—
I2C2BRG<11:0>
—
—
—
I2CT1DATA<7:0>
—
—
—
—
—
UART1-2 REGISTERS MAP
BF80_6000 U1MODE(1)
BF80_6010
Bits
31/15
15:0
—
—
—
—
—
—
—
—
I2CR1DATA<7:0>
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except I2CxRCV have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
TABLE 4-7:
SFR
Virtual
Addr
I2C1-2 REGISTERS MAP(1) (CONTINUED)
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
—
—
31:16
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
IREN
RTSMD
—
31:16
—
—
15:0
UTXISEL<1:0>
31:16
—
15:0
UEN<1:0>
—
—
—
—
—
ADM_EN
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
15:0
31:16
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
—
—
Bits
16/0
—
—
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
—
—
—
—
—
—
—
—
—
PDSEL<1:0>
—
STSEL
ADDR<7:0>
URXISEL<1:0>
—
—
Transmit Register
—
—
—
—
—
Receive Register
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BRG<15:0>
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
IREN
RTSMD
—
UEN<1:0>
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL<1:0>
STSEL
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
PIC32MX3XX/4XX
DS61143F-page 38
TABLE 4-6:
© 2009 Microchip Technology Inc.
TABLE 4-7:
SFR
Virtual
Addr
SFR
Name
BF80_6210
U2STA(1)
BF80_6220 U2TXREG
BF80_6230 U2RXREG
BF80_6240
Legend:
Note 1:
U2BRG(1)
Preliminary
SFR
Virtual
Addr
SFR
Name
BF80_5800
SPI1CON
BF80_5810 SPI1STAT
BF80_5820
SPI1BUF
BF80_5830
SPI1BRG
BF80_5A10 SPI2STAT
SPI2BUF
BF80_5A30 SPI2BRG
DS61143F-page 39
2:
Bits
30/14
31:16
—
—
15:0
UTXISEL<1:0>
31:16
—
15:0
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
—
—
—
—
—
ADM_EN
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
ADDEN
RIDLE
—
—
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
PERR
FERR
OERR
URXDA
—
—
—
—
—
—
—
—
—
—
ADDR<7:0>
URXISEL<1:0>
—
—
Transmit Register
—
—
—
—
—
Receive Register
—
—
—
—
—
SPI1-2 REGISTERS MAP(1,2)
Bits
31/15
Bits
30/14
Bits
29/13
FRMSYNC FRMPOL
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
31:16
FRMEN
—
—
—
—
—
—
—
—
—
—
—
SPIFE
—
15:0
ON
FRZ
SIDL
DISSDO
MODE32
MODE16
SMP
CKE
SSEN
CKP
MSTEN
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
SPIBUSY
—
—
—
—
SPIROV
—
—
SPITBE
—
—
SPIRBF
—
—
—
—
—
—
—
31:16
DATA<31:0>
15:0
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
FRMEN
—
—
—
—
—
—
—
—
—
—
—
SPIFE
—
15:0
ON
FRZ
SIDL
DISSDO
MODE32
MODE16
SMP
CKE
SSEN
CKP
MSTEN
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
SPIBUSY
—
—
—
—
SPIROV
—
—
SPITBE
—
—
SPIRBF
—
—
—
—
—
—
—
FRMSYNC FRMPOL
31:16
—
BRG<8:0>
DATA<31:0>
15:0
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
BRG<8:0>
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
SPI2 Module is not present on PIC32MX420FXXXX/440FXXXX devices.
PIC32MX3XX/4XX
BF80_5A00 SPI2CON
Legend:
Note 1:
Bits
31/15
15:0
BRG<15:0>
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
TABLE 4-8:
BF80_5A20
UART1-2 REGISTERS MAP (CONTINUED)
SFR
Virtual
Addr
ADC REGISTERS MAP
SFR
Name
Bits
31/15
BF80_9000 AD1CON1(1)
BF80_9010 AD1CON2(1)
BF80_9020 AD1CON3(1)
BF80_9040 AD1CHS(1)
BF80_9060 AD1PCFG
(1)
BF80_9050 AD1CSSL(1)
BF80_9070 ADC1BUF0
Preliminary
BF80_9080 ADC1BUF1
BF80_9090 ADC1BUF2
BF80_90A0 ADC1BUF3
BF80_90B0 ADC1BUF4
BF80_90C0 ADC1BUF5
BF80_90D0 ADC1BUF6
BF80_90E0 ADC1BUF7
© 2009 Microchip Technology Inc.
BF80_90F0 ADC1BUF8
BF80_9100 ADC1BUF9
BF80_9110 ADC1BUFA
BF80_9120 ADC1BUFB
Legend:
Note 1:
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
—
31:16
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
Bits
25/9
Bits
24/8
Bits
23/7
—
—
—
FORM<2:0>
Bits
22/6
Bits
21/5
—
—
SSRC<2:0>
—
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
—
—
—
—
—
CLRASAM
—
ASAM
SAMP
DONE
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
15:0
VCFG2
VCFG1
VCFG0
OFFCAL
—
CSCNA
—
—
BUFS
—
31:16
—
—
—
—
—
—
—
—
—
—
15:0
ADRC
—
—
31:16
CH0NB
—
—
—
CH0NA
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
PCFG15
PCFG14
PCFG13
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
SMPI<3:0>
—
SAMC<4:0>
—
—
—
—
—
BUFM
ALTS
—
—
ADCS<7:0>
CH0SB<3:0>
CH0SA<3:0>
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CSSL15
CSSL14
CSSL13
CSSL12
CSSL11
CSSL10
CSSL9
CSSL8
CSSL7
CSSL6
CSSL5
CSSL4
CSSL3
CSSL2
CSSL1
CSSL0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
ADC Result Word 0 (ADC1BUF0<31:0>)
ADC Result Word 1 (ADC1BUF1<31:0>)
ADC Result Word 2 (ADC1BUF2<31:0>)
ADC Result Word 3 (ADC1BUF3<31:0>)
ADC Result Word 4 (ADC1BUF4<31:0>)
ADC Result Word 5 (ADC1BUF5<31:0>)
ADC Result Word 6 (ADC1BUF6<31:0>)
ADC Result Word 7 (ADC1BUF7<31:0>)
ADC Result Word 8 (ADC1BUF8<31:0>)
ADC Result Word 9 (ADC1BUF9<31:0>)
ADC Result Word A (ADC1BUFA<31:0>)
ADC Result Word B (ADC1BUFB<31:0>)
15:0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
PIC32MX3XX/4XX
DS61143F-page 40
TABLE 4-9:
© 2009 Microchip Technology Inc.
TABLE 4-9:
SFR
Virtual
Addr
ADC REGISTERS MAP (CONTINUED)
SFR
Name
Bits
31/15
BF80_9130 ADC1BUFC
BF80_9140 ADC1BUFD
BF80_9150 ADC1BUFE
BF80_9160 ADC1BUFF
Legend:
Note 1:
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
ADC Result Word C (ADC1BUFC<31:0>)
15:0
31:16
ADC Result Word D (ADC1BUFD<31:0>)
15:0
31:16
ADC Result Word E (ADC1BUFE<31:0>)
15:0
31:16
Bits
31/15
Preliminary
BF88_3020 DMAADDR
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
SUSPEND
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
RDWR
—
DMACH<1:0>
31:16
DMAADDR<31:0>
15:0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
DMA CRC REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY(1)
SFR
Name
BF88_3030 DCRCCON
BF88_3040 DCRCDATA
BF88_3050 DCRCXOR
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
PLEN<3:0>
—
—
—
15:0
31:16
—
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
—
—
—
—
—
—
—
—
CRCEN
CRCAPP
—
—
—
—
CRCCH<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DCRCDATA<15:0>
—
—
—
—
—
—
—
—
—
DS61143F-page 41
15:0
DCRCXOR<15:0>
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
PIC32MX3XX/4XX
TABLE 4-11:
Legend:
Note 1:
Bits
27/11
31:16
SFR
Name
BF88_3010 DMASTAT
SFR
Virtual
Addr
Bits
28/12
DMA GLOBAL REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY
BF88_3000 DMACON(1)
Legend:
Note 1:
Bits
29/13
ADC Result Word F (ADC1BUFF<31:0>)
15:0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
TABLE 4-10:
SFR
Virtual
Addr
Bits
30/14
SFR
Virtual
Addr
DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY(1)
SFR
Name
BF88_3060 DCH0CON
BF88_3070 DCH0ECON
BF88_3080
DCH0INT
BF88_3090 DCH0SSA
BF88_30A0 DCH0DSA
BF88_30B0 DCH0SSIZ
BF88_30C0 DCH0DSIZ
Preliminary
BF88_30D0 DCH0SPTR
BF88_30E0 DCH0DPTR
BF88_30F0 DCH0CSIZ
BF88_3100 DCH0CPTR
BF88_3110 DCH0DAT
BF88_3120 DCH1CON
© 2009 Microchip Technology Inc.
BF88_3130 DCH1ECON
BF88_3140
DCH1INT
BF88_3150 DCH1SSA
BF88_3160 DCH1DSA
Legend:
Note 1:
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
15:0
Bits
24/8
CHSIRQ<7:0>
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
—
—
CHCHN
CHAEN
—
—
—
—
—
CHEDET
CHPRI<1:0>
CHAIRQ<7:0>
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
CHSSA<31:0>
15:0
31:16
CHDSA<31:0>
15:0
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
15:0
CHSSIZ<7:0>
—
—
—
—
—
CHDSIZ<7:0>
—
—
—
—
—
CHSTR<7:0>
—
—
—
—
—
CHDPTR<7:0>
—
—
—
—
—
CHCSIZ<7:0>
—
—
—
—
—
CHCPTR<7:0>
—
—
—
—
—
CHPDAT<7:0>
CHPRI<1:0>
CHAIRQ<7:0>
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
31:16
15:0
31:16
CHSIRQ<7:0>
—
CHSSA<31:0>
CHDSA<31:0>
15:0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers except DCHxSPTR, DCHxDPTR, and DCHxCPTR have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR,
SET and INV Registers” for more information.
PIC32MX3XX/4XX
DS61143F-page 42
TABLE 4-12:
© 2009 Microchip Technology Inc.
TABLE 4-12:
SFR
Virtual
Addr
DMA CHANNELS 0-3 REGISTERS MAP (CONTINUED)FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES
ONLY(1) (CONTINUED)
SFR
Name
BF88_3170 DCH1SSIZ
BF88_3180 DCH1DSIZ
BF88_3190 DCH1SPTR
BF88_31A0 DCH1DPTR
BF88_31B0 DCH1CSIZ
BF88_31C0 DCH1CPTR
BF88_31D0 DCH1DAT
Preliminary
BF88_31E0 DCH2CON
BF88_31F0 DCH2ECON
BF88_3200
DCH2INT
BF88_3210 DCH2SSA
BF88_3230 DCH2SSIZ
BF88_3240 DCH2DSIZ
BF88_3250 DCH2SPTR
BF88_3260 DCH2DPTR
DS61143F-page 43
BF88_3270 DCH2CSIZ
Legend:
Note 1:
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
15:0
CHSIRQ<7:0>
CHSSIZ<7:0>
—
—
—
—
—
CHDSIZ<7:0>
—
—
—
—
—
CHSPTR<7:0>
—
—
—
—
—
CHDPTR<7:0>
—
—
—
—
—
CHCSIZ<7:0>
—
—
—
—
—
CHCPTR<7:0>
—
—
—
—
—
CHPDAT<7:0>
CHPRI<1:0>
CHAIRQ<7:0>
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
CHSSA<31:0>
15:0
31:16
CHDSA<31:0>
15:0
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
CHSSIZ<7:0>
—
—
—
—
—
CHDSIZ<7:0>
—
—
—
—
—
CHSPTR<7:0>
—
—
—
—
—
CHDPTR<7:0>
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
CHCSIZ<7:0>
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers except DCHxSPTR, DCHxDPTR, and DCHxCPTR have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR,
SET and INV Registers” for more information.
PIC32MX3XX/4XX
BF88_3220 DCH2DSA
Bits
31/15
SFR
Virtual
Addr
DMA CHANNELS 0-3 REGISTERS MAP (CONTINUED)FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES
ONLY(1) (CONTINUED)
SFR
Name
BF88_3280 DCH2CPTR
BF88_3290 DCH2DAT
BF88_32A0 DCH3CON
BF88_32B0 DCH3ECON
BF88_32C0 DCH3INT
BF88_32D0 DCH3SSA
BF88_32E0 DCH3DSA
Preliminary
BF88_32F0 DCH3SSIZ
BF88_3300 DCH3DSIZ
BF88_3310 DCH3SPTR
BF88_3320 DCH3DPTR
BF88_3330 DCH3CSIZ
BF88_3340 DCH3CPTR
© 2009 Microchip Technology Inc.
BF88_3350 DCH3DAT
Legend:
Note 1:
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
15:0
CHSIRQ<7:0>
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
CHEDET
CHCPTR<7:0>
—
—
—
—
—
CHPDAT<7:0>
CHPRI<1:0>
CHAIRQ<7:0>
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
CHSSA<31:0>
15:0
31:16
CHDSA<31:0>
15:0
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
CHSSIZ<7:0>
—
—
—
—
—
CHDSIZ<7:0>
—
—
—
—
—
CHSTR<7:0>
—
—
—
—
—
CHDPTR<7:0>
—
—
—
—
—
CHCSIZ<7:0>
—
—
—
—
—
CHCPTR<7:0>
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
CHPDAT<7:0>
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers except DCHxSPTR, DCHxDPTR, and DCHxCPTR have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR,
SET and INV Registers” for more information.
PIC32MX3XX/4XX
DS61143F-page 44
TABLE 4-12:
© 2009 Microchip Technology Inc.
TABLE 4-13:
SFR
Virtual
Addr
COMPARATOR REGISTERS MAP(1)
SFR
Name
Bits
31/15
BF80_A000 CM1CON
BF80_A010 CM2CON
BF80_A060
Legend:
Note 1:
CMSTAT
SFR
Virtual
Addr
SFR
Name
BF80_9800
CVRCON
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
—
—
—
—
—
—
—
—
—
15:0
ON
COE
CPOL
—
—
—
—
COUT
31:16
—
—
—
—
—
—
—
—
15:0
ON
COE
CPOL
—
—
—
—
COUT
31:16
—
—
—
—
—
—
—
—
31:16
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
—
—
—
—
—
—
—
EVPOL<1:0>
—
CREF
—
—
—
—
—
—
—
—
EVPOL<1:0>
—
CREF
—
—
—
—
—
—
—
—
CCH<1:0>
—
—
CCH<1:0>
—
—
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Preliminary
FLASH CONTROLLER REGISTERS MAP
SFR
Name
Bits
31/15
BF80_F430 NVMDATA
NVMSRC
ADDR
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
NVMWR
NVM
WREN
NVMERR
LVDERR
LVDSTAT
—
—
—
—
—
—
—
NVMOP<3:0>
NVMKEY<31:0>
NVMADDR<31:0>
NVMDATA<31:0>
DS61143F-page 45
NVMSRCADDR<31:0>
15:0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
PIC32MX3XX/4XX
NVMKEY
BF80_F420 NVMADDR(1)
Legend:
Note 1:
Bits
26/10
31:16
31:16
BF80_F440
Bits
27/11
COMPARATOR VOLTAGE REFERENCE REGISTERS MAP(1)
BF80_F400 NVMCON(1)
BF80_F410
Bits
28/12
15:0
ON
—
—
—
—
—
—
—
—
CVROE
CVRR
CVRSS
CVR<3:0>
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
TABLE 4-15:
SFR
Virtual
Addr
Bits
29/13
15:0
—
FRZ
SIDL
—
—
—
—
—
—
—
—
—
—
—
C2OUT
C1OUT
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
TABLE 4-14:
Legend:
Note 1:
Bits
30/14
SFR
Virtual
Addr
SYSTEM CONTROL REGISTERS MAP(1)
SFR
Name
BF80_F000 OSCCON
BF80_F010
OSCTUN
BF80_0000 WDTCON
BF80_F600
RCON
BF80_F610
RSWRST
Legend:
Note 1:
Preliminary
BF88_6020 LATA(1,2,3)
BF88_6030 ODCA(1,2,3)
BF88_6040 TRISB(4,5)
BF88_6050 PORTB(4,5)
© 2009 Microchip Technology Inc.
4:
5:
6:
7:
8:
9:
10:
11:
31:16
—
—
15:0
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
15:0
ON
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
CM
VREGS
EXTR
SWR
—
WDTO
SLEEP
IDLE
BOR
POR
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SFR
Name
BF88_6010 PORTA(1,2,3)
3:
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
23/7
Bits
22/6
RCDIV<2:0>
—
SOSCRDY
—
NOSC<2:0>
CLKLOCK
ULOCK
LOCK
SLPEN
CF
UFRCEN
SOSCEN
OSWEN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PLLODIV<2:0>
COSC<2:0>
—
Bits
25/9
Bits
24/8
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
PBDIV<1:0>
Bits
17/1
Bits
16/0
PLLMULT<2:0>
TUN<5:0>
—
—
—
—
SWDTPS<4:0>
—
—
—
WDTCLR
PORT A-G REGISTERS MAP(11)
BF88_6000 TRISA(1,2,3)
Legend:
Note 1:
2:
Bits
30/14
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SWRST
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
TABLE 4-17:
SFR
Virtual
Addr
Bits
31/15
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
TRISA15
TRISA14
—
—
—
TRISA10
TRISA9
—
31:16
—
—
—
—
—
—
—
—
15:0
RA15
RA14
—
—
—
RA10
RA9
—
31:16
—
—
—
—
—
—
—
—
15:0
LATA15
LATA14
—
—
—
LATA10
LATA9
—
31:16
—
—
—
—
—
—
—
—
15:0
ODCA15
ODCA14
—
—
—
ODCA10
ODCA9
—
31:16
—
—
—
—
—
—
—
—
15:0
31:16
TRISA<7:0>
—
—
—
—
RA<7:0>
—
—
—
—
LATA<7:0>
—
—
—
—
—
ODCA<7:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISB<15:0>
—
—
—
—
—
—
—
—
—
15:0
RB<15:0>
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TRISA, PORTA, LATA and ODCA registers are not implemented on 64-pin devices, and read as ‘0’.
JTAG program/debug port is multiplexed with port pins RA0, RA1, RA4 and RA5 on 100-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the
user’s application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must maintain JTAGEN bit = 1.
On specific 100-pin devices, the instruction TRACE port is multiplexed with PORTA pins RA6, RA7; PORTG pins RG12, RG13 and RG14. At Power-on Reset, these pins are general purpose I/O pins. To maintain
these pins as general purpose I/O pins, the user’s application code must maintain TROEN (DDPCON<2>) bit = 0. To use these pins as instruction TRACE pins, TROEN must be set = 1.
JTAG program/debug port is multiplexed with port pins RB10, RB11, RB12 and RB13 on 64-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the
user’s application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must maintain JTAGEN bit = 1.
Port Pin RB3 is not available as a general purpose I/O pin when the USB module is enabled.
Not implemented on 64-pin devices. Read as ‘0’.
Not implemented on 64-pin USB devices. Read as ‘0’.
Not implemented on 100-pin USB devices. Read as ‘0’.
Not available as a general purpose I/O pin when USB module is enabled.
Not available as a general purpose I/O pin when USB module is enabled. Input only when the USB module is disabled.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
PIC32MX3XX/4XX
DS61143F-page 46
TABLE 4-16:
© 2009 Microchip Technology Inc.
TABLE 4-17:
SFR
Virtual
Addr
SFR
Name
BF88_6060
LATB(4,5)
BF88_6070 ODCB(4,5)
BF88_6080
BF88_6090
BF88_60A0
BF88_60B0
TRISC
PORTC
LATC
ODCC
Preliminary
TRISD
BF88_60D0
PORTD
BF88_60E0
LATD
BF88_60F0
ODCD
BF88_6100
TRISE
BF88_6110
PORTE
BF88_6120
LATE
Legend:
Note 1:
2:
3:
4:
DS61143F-page 47
5:
6:
7:
8:
9:
10:
11:
31:16
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
LATB<15:0>
—
—
—
—
—
—
—
15:0
—
—
ODCB<15:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
TRISC15
TRISC14
TRISC13
TRISC12
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
RC15
RC14
RC13
RC12
—
—
—
—
—
—
—
RC4(6)
RC3(6)
RC2(6)
RC1(6)
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
LATC15
LATC14
LATC13
LATC12
—
—
—
—
—
—
—
LATC4(6)
LATC3(6)
LATC2(6)
LATC1(6)
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ODCC15
ODCC14
ODCC13
ODCC12
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0 TRISD15(6) TRISD14(6) TRISD13(6) TRISD12(6)
31:16
—
—
—
—
15:0
RD15(6)
RD14(6)
RD13(6)
RD12(6)
31:16
—
—
—
—
15:0
LAT15(6)
LAT14(6)
LAT13(6)
LAT12(6)
31:16
—
—
—
—
TRISD<11:8>
—
—
—
TRISC4(6) TRISC3(6) TRISC2(6) TRISC1(6)
ODCC4(6) ODCC3(6) ODCC2(6) ODCC1(6)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LATD<7:0>
—
—
—
—
ODCD<11:8>
—
—
RD<7:0>
LATD<11:8>
15:0 ODCD15(6) ODCD14(6) ODCD13(6) ODCD12(6)
—
—
TRISD<7:0>
RD<11:8>
—
—
—
—
—
ODCD<7:0>
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
RE9(6)
RE8(6)
31:16
—
—
—
—
—
—
—
—
—
—
—
TRISE9(6) TRISE8(6)
—
—
TRISE<7:0>
—
—
—
—
RE<7:0>
—
—
—
—
15:0
—
—
—
—
—
—
LATE9(6) LATE8(6)
LATE<7:0>
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TRISA, PORTA, LATA and ODCA registers are not implemented on 64-pin devices, and read as ‘0’.
JTAG program/debug port is multiplexed with port pins RA0, RA1, RA4 and RA5 on 100-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the
user’s application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must maintain JTAGEN bit = 1.
On specific 100-pin devices, the instruction TRACE port is multiplexed with PORTA pins RA6, RA7; PORTG pins RG12, RG13 and RG14. At Power-on Reset, these pins are general purpose I/O pins. To maintain
these pins as general purpose I/O pins, the user’s application code must maintain TROEN (DDPCON<2>) bit = 0. To use these pins as instruction TRACE pins, TROEN must be set = 1.
JTAG program/debug port is multiplexed with port pins RB10, RB11, RB12 and RB13 on 64-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the
user’s application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must maintain JTAGEN bit = 1.
Port Pin RB3 is not available as a general purpose I/O pin when the USB module is enabled.
Not implemented on 64-pin devices. Read as ‘0’.
Not implemented on 64-pin USB devices. Read as ‘0’.
Not implemented on 100-pin USB devices. Read as ‘0’.
Not available as a general purpose I/O pin when USB module is enabled.
Not available as a general purpose I/O pin when USB module is enabled. Input only when the USB module is disabled.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
PIC32MX3XX/4XX
BF88_60C0
PORT A-G REGISTERS MAP(11) (CONTINUED)
Preliminary
SFR
Virtual
Addr
SFR
Name
BF88_6130
ODCE
BF88_6140
TRISF
BF88_6150
PORTF
BF88_6160
LATF
BF88_6170
ODCF
BF88_6180
TRISG
BF88_6190
PORTG
BF88_61A0
LATG
BF88_61B0
ODCG
Legend:
Note 1:
2:
3:
4:
© 2009 Microchip Technology Inc.
5:
6:
7:
8:
9:
10:
11:
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
RF13(6)
RF12(6)
—
—
—
RF8(6)
RF7(6,8)
RF6(7,8)
RF5
RF4
RF3(9)
RF2(7)
RF1
RF0
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
LATF8(6)
31:16
—
—
—
—
—
15:0
—
—
—
—
—
31:16
—
—
TRISF13(6) TRISF12(6)
LATF13(6) LATF12(6)
—
—
ODCF13(6) ODCF12(6)
—
—
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
—
—
—
—
—
—
—
—
—
—
ODCE9(6) ODCE8(6)
—
ODCE<7:0>
—
—
TRISF8(6) TRISF7(6,8) TRISF6(7,8)
—
LATF7(6,8) LATF6(7,8)
—
—
ODCF8(6) ODCF7(6,8) ODCF6(7,8)
—
—
—
—
—
—
TRISF5
TRISF4
TRISF3
TRISF2(7)
TRISF1
TRISF0
—
—
—
—
—
—
LATF5
LATF4
LATF3
LATF2(7)
LATF1
LATF0
—
—
—
—
—
—
ODCF5
ODCF4
ODCF3
ODCF2(7)
ODCF1
ODCF0
—
—
—
—
—
—
—
—
—
—
—
—
15:0 TRISG15(6) TRISG14(6) TRISG13(6) TRISG12(6)
—
—
TRISG9
TRISG8
TRISG7
TRISG6
—
—
TRISG3
TRISG2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
RG15(6)
RG14(6)
RG13(6)
RG12(6)
—
—
RG9
RG8
RG7
RG6
—
—
RG3(10)
RG2(10)
RG1(6)
RG0(6)
31:16
—
—
—
—
TRISG1(6) TRISG0(6)
—
—
—
—
—
—
—
—
—
—
—
—
15:0 LATG15(6) LATG14(6) LATG13(6) LATG12(6)
—
—
LATG9
LATG8
LATG7
LATG6
—
—
LATG3
LATG2
LATG1(6)
LATG0(6)
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0 ODCG15(6) ODCG14(6) ODCG13(6) ODCG12(6)
—
—
ODCG9
ODCG8
ODCG7
ODCG6
—
—
ODCG3
ODCG2 ODCG1(6) ODCG0(6)
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TRISA, PORTA, LATA and ODCA registers are not implemented on 64-pin devices, and read as ‘0’.
JTAG program/debug port is multiplexed with port pins RA0, RA1, RA4 and RA5 on 100-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the
user’s application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must maintain JTAGEN bit = 1.
On specific 100-pin devices, the instruction TRACE port is multiplexed with PORTA pins RA6, RA7; PORTG pins RG12, RG13 and RG14. At Power-on Reset, these pins are general purpose I/O pins. To maintain
these pins as general purpose I/O pins, the user’s application code must maintain TROEN (DDPCON<2>) bit = 0. To use these pins as instruction TRACE pins, TROEN must be set = 1.
JTAG program/debug port is multiplexed with port pins RB10, RB11, RB12 and RB13 on 64-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the
user’s application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must maintain JTAGEN bit = 1.
Port Pin RB3 is not available as a general purpose I/O pin when the USB module is enabled.
Not implemented on 64-pin devices. Read as ‘0’.
Not implemented on 64-pin USB devices. Read as ‘0’.
Not implemented on 100-pin USB devices. Read as ‘0’.
Not available as a general purpose I/O pin when USB module is enabled.
Not available as a general purpose I/O pin when USB module is enabled. Input only when the USB module is disabled.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
TABLE 4-18:
SFR
Virtual
Addr
SFR
Name
BF88_61C0
CNCON
Legend:
Note 1:
2:
PORT A-G REGISTERS MAP(11) (CONTINUED)
CHANGE NOTICE AND PULL-UP REGISTERS MAP(2)
31:16
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
CNEN and CNPUE bit(s) are not implemented on 64-pin devices, and read as ‘0’.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
PIC32MX3XX/4XX
DS61143F-page 48
TABLE 4-17:
© 2009 Microchip Technology Inc.
TABLE 4-18:
SFR
Virtual
Addr
SFR
Name
BF88_61D0
CNEN
BF88_61E0
CNPUE
Legend:
Note 1:
2:
SFR
Virtual
Addr
SFR
Name
BF80_7000
PMCON
BF80_7010 PMMODE
Preliminary
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
—
—
—
—
—
—
—
—
—
—
CNEN21(1) CNEN20(1) CNEN19(1) CNEN18
—
CNPUE21(1) CNPUE20(1) CNPUE19(1) CNPUE18 CNPUE17 CNPUE16
15:0
31:16
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
CNEN17
CNEN16
CNEN<15:0>
—
—
—
—
—
—
—
—
—
PMADDR
BF80_7030
PMDOUT
BF80_7040
PMDIN
BF80_7050
PMAEN
BF80_7060
PMSTAT
PARALLEL MASTER PORT REGISTERS MAP(1)
Bits
31/15
Bits
30/14
Bits
29/13
31:16
—
—
—
15:0
ON
FRZ
SIDL
31:16
—
—
—
15:0
BUSY
31:16
—
Bits
28/12
Bits
27/11
—
—
ADRMUX<1:0>
—
IRQM<1:0>
—
—
—
INCM<1:0>
—
—
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
—
—
—
—
—
PMPTTL
PTWREN
PTRDEN
—
—
—
MODE16
—
CSF<1:0>
—
MODE<1:0>
—
—
Bits
18/2
Bits
17/1
Bits
16/0
—
—
—
—
—
—
ALP
CS2P
CS1P
—
WRSP
RDSP
—
—
—
—
—
—
—
—
Bits
19/3
WAITM<3:0>
—
WAITE<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADDR<13:0>
31:16
DATAOUT<31:0>
15:0
31:16
DATAIN<31:0>
15:0
—
—
—
—
—
—
—
—
15:0
31:16
Bits
20/4
WAITB<1:0>
15:0 CS2EN/A15 CS1EN/A14
31:16
Bits
21/5
—
PTEN<15:0>
—
—
—
—
—
—
—
—
—
15:0
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
TABLE 4-20:
DS61143F-page 49
SFR
Virtual
Addr
SFR
Name
BF80_F200
DDPCON
PROGRAMMING AND DIAGNOSTICS REGISTERS MAP
31:16
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
—
—
—
—
—
—
—
—
—
—
—
—
—
DDPUSB
DDPU1
DDPU2
DDPSPI1
15:0
—
—
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
—
—
—
—
JTAGEN
TROEN
—
—
PIC32MX3XX/4XX
BF80_7020
Legend:
31:16
Bits
31/15
15:0
CNPUE<15:0>
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
CNEN and CNPUE bit(s) are not implemented on 64-pin devices, and read as ‘0’.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
TABLE 4-19:
Legend:
Note 1:
CHANGE NOTICE AND PULL-UP REGISTERS MAP(2) (CONTINUED)
SFR
Virtual
Addr
PREFETCH REGISTERS MAP
SFR
Name
BF88_4000 CHECON(1)
BF88_4010 CHEACC(1)
BF88_4020 CHETAG(1)
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
—
—
—
—
—
—
—
—
—
—
—
—
31:16 CHEWEN
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
15:0
31:16
—
LTAG
BOOT
Preliminary
BF88_4040
CHEW0
BF88_4050
CHEW1
BF88_4060
CHEW2
BF88_4070
CHEW3
BF88_4080
CHELRU
BF88_4090
CHEHIT
BF88_40A0
CHEMIS
31:16
—
—
—
—
—
15:0
Bits
23/7
Bits
22/6
—
—
DCSZ<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LMASK<15:5>
—
31:16
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
—
—
PREFEN<1:0>
—
—
—
—
—
—
—
—
CHEIDX<3:0>
—
—
—
Bits
17/1
Bits
16/0
—
CHECOH
PFMWS<2:0>
—
LTAG<23:16>
—
—
—
—
—
LVALID
LLOCK
LTYPE
—
—
—
—
—
—
—
—
—
CHEW0<31:0>
15:0
31:16
CHEW1<31:0>
15:0
31:16
CHEW2<31:0>
15:0
31:16
CHEW3<31:0>
15:0
31:16
Bits
24/8
LTAG<15:4>
15:0
BF88_4030 CHEMSK(1)
Bits
25/9
—
—
—
—
—
—
—
15:0
CHELRU<24:16>
CHELRU<15:0>
31:16
CHEHIT<31:0>
15:0
31:16
CHEMIS<31:0>
15:0
31:16
CHEPFABT<31:0>
15:0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
BF88_40C0 CHEPFABT
Legend:
Note 1:
TABLE 4-22:
© 2009 Microchip Technology Inc.
SFR
Virtual
Addr
SFR
Name
BF80_0200
RTCCON
BF80_0210 RTCALRM
Legend:
Note 1:
RTCC REGISTERS MAP(1)
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
31:16
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
RTSEC
SEL
RTC
CLKON
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
CAL<11:0>
RTCWREN RTCSYNC HALFSEC
—
—
—
RTCOE
—
ALRM
CHIME
PIV
AMASK<3:0>
ARPT<7:0>
15:0 ALRMEN
SYNC
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
PIC32MX3XX/4XX
DS61143F-page 50
TABLE 4-21:
© 2009 Microchip Technology Inc.
TABLE 4-22:
SFR
Virtual
Addr
SFR
Name
BF80_0220
RTCTIME
RTCC REGISTERS MAP(1) (CONTINUED)
Bits
31/15
BF80_0230 RTCDATE
BF80_0240 ALRMTIME
BF80_0250 ALRMDATE
Legend:
Note 1:
Preliminary
BFC0_2FF4 DEVCFG2
BFC0_2FF8 DEVCFG1
Bits
27/11
Bits
26/10
Bits
25/9
HR10<3:0>
HR01<3:0>
15:0
SEC10<3:0>
SEC01<3:0>
31:16
YEAR10<3:0>
YEAR01<3:0>
15:0
DAY10<3:0>
DAY01<3:0>
31:16
MIN10<3:0>
MIN01<3:0>
15:0
SEC10<3:0>
SEC01<3:0>
31:16
—
—
—
—
—
—
Bits
24/8
Bits
23/7
Bits
22/6
—
—
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
—
—
—
MIN10<3:0>
—
—
—
—
—
—
—
—
—
MONTH01<3:0>
—
WDAY01<3:0>
MIN10<3:0>
—
Bits
16/0
MIN01<3:0>
MONTH10<3:0>
—
Bits
17/1
MIN01<3:0>
—
—
MONTH10<3:0>
—
—
—
MONTH01<3:0>
DEVCFG: DEVICE CONFIGURATION WORD SUMMARY
31:16
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0 USERID15 USERID14 USERID13 USERID12 USERID11 USERID10 USERID9 USERID8 USERID7 USERID6 USERID5 USERID4 USERID3 USERID2 USERID1 USERID0
31:16
—
—
—
—
15:0 FUPLLEN(1)
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
FCKSM<1:0>
FPBDIV<1:0>
—
OSC
IOFNC
31:16
—
—
—
—
—
CP
—
—
—
—
SFR
Virtual
Addr
SFR
Name
BF80_F220
DEVID
—
—
—
—
—
—
FPLLMULT<2:0>
—
FPLLODIV<2:0>
—
FPLLIDIV<2:0>
FWDTEN
—
—
IESO
—
FSOSCEN
—
BWP
—
—
—
—
PWP19
PWP18
—
—
—
—
—
ICESEL
—
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
POSCMD<1:0>
15:0
PWP15
PWP14
PWP13
PWP12
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
These bits are only available on PIC32MX4XX devices.
TABLE 4-24:
—
FUPLLIDIV<2:0>(1)
WDTPS<4:0>
—
FNOSC<2:0>
PWP17
PWP16
DEBUG<1:0>
DEVICE AND REVISION ID SUMMARY
Bits
31/15
31:16
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
VER<3:0>
15:0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DEVID<27:16>
DEVID<15:0>
Bits
17/1
Bits
16/0
DS61143F-page 51
PIC32MX3XX/4XX
BFC0_2FFC DEVCFG0
Legend:
Bits
28/12
31:16
SFR
Name
BFC0_2FF0 DEVCFG3
Legend:
Note 1:
Bits
29/13
15:0
DAY10<3:0>
DAY01<3:0>
—
—
—
—
WDAY01<3:0>
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 4-23:
SFR
Virtual
Addr
Bits
30/14
SFR
Virtual
Addr
USB REGISTERS MAP
SFR
Name
BF88_5040 U1OTGIR
BF88_5050
U1OTGIE
BF88_5060
U1OTG
STAT
BF88_5070 U1OTGCON
BF88_5080
U1PWRC
BF88_5200
U1IR
Preliminary
BF88_5210
BF88_5220
BF88_5230
BF88_5240
BF88_5250
© 2009 Microchip Technology Inc.
BF80_5260
U1IE
U1EIR
U1EIE
U1STAT
U1CON
U1ADDR
BF88_5270 U1BDTP1
BF88_5280
U1FRML
BF88_5290
U1FRMH
Legend:
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
IDIF
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
IDIE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
ID
—
LSTATE
—
SESVD
SESEND
—
VBUSVD
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
Bits
23/7
Bits
22/6
Bits
21/5
—
—
—
T1MSECIF LSTATEIF
—
—
—
ACTVIF
Bits
19/3
Bits
18/2
Bits
17/1
—
—
—
—
—
VBUSVDIF
SESVDIF SESENDIF
—
T1MSECIE LSTATEIE
DPPULUP DMPULUP
—
Bits
20/4
—
ACTVIE
—
SESVDIE SESENDIE
—
—
—
VBUSVDIE
—
—
—
—
DPPUL
DWN
DMPUL
DWN
VBUSON
OTGEN
—
—
—
—
—
—
USBPWR
VBUSCHG VBUSDIS
15:0
—
—
—
—
—
—
—
—
UACTPND
—
—
USLPGRD
—
—
USUS
PEND
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
STALLIF
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
STALLIE
31:16
—
—
—
—
—
—
—
—
—
RESUME
ATTACHIF
IF
—
—
RESUME
ATTACHIE
IE
—
—
IDLEIF
TRNIF
SOFIF
UERRIF
—
—
—
—
IDLEIE
TRNIE
SOFIE
UERRIE
—
—
—
—
15:0
—
—
—
—
—
—
—
—
BTSEF
BMXEF
DMAEF
BTOEF
DFN8EF
CRC16EF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
BTSEE
BMXEE
DMAEE
BTOEE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
DFN8EE
ENDPT<3:0>
—
—
—
—
PKTDIS
—
URSTIE
DETACHIE
CRC5EF
EOFEF
—
CRC5EE
EOFEE
PIDEF
—
PIDEE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
JSTATE
SE0
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
LSPDEN
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
USBEN
USBRST
HOSTEN
RESUME
PPBRST
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SOFEN
DEVADDR<6:0>
—
—
—
BDTPTRL<7:1>
—
—
PPBI
—
—
DETACHIF
—
—
TOKBUSY
CRC16EE
—
URSTIF
DIR
15:0
15:0
—
—
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bits
16/0
—
—
—
—
FRML<7:0>
—
FRMH<10:8>
PIC32MX3XX/4XX
DS61143F-page 52
TABLE 4-25:
© 2009 Microchip Technology Inc.
TABLE 4-25:
SFR
Virtual
Addr
SFR
Name
BF88_52A0
U1TOK
BF88_52B0
U1SOF
BF88_52C0 U1BDTP2
BF88_52D0 U1BDTP3
BF88_52E0 U1CNFG1
BF88_5300
U1EP0
BF88_5310
U1EP1
Preliminary
BF88_5320
U1EP2
BF88_5330
U1EP3
BF88_5340
U1EP4
U1EP5
BF88_5360
U1EP6
DS61143F-page 53
BF88_5370
U1EP7
BF88_5380
U1EP8
BF88_5390
U1EP9
Legend:
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
UTEYE
UOEMON
USBFRZ
USBSIDL
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
LSPD
RETRYDIS
—
EPCON
DIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PID<3:0>
—
—
EP<3:0>
—
—
—
CNT<7:0>
—
—
—
—
—
BDTPTRH<7:0>
—
—
—
—
—
BDTPTRU<7:0>
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCON
DIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EPCON
DIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCON
DIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCON
DIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EPCON
DIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCON
DIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EPCON
DIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCON
DIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EPCON
DIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
15:0
—
—
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
PIC32MX3XX/4XX
BF88_5350
USB REGISTERS MAP (CONTINUED)
SFR
Virtual
Addr
SFR
Name
BF88_53A0
U1EP10
BF88_53B0
U1EP11
BF88_53C0
U1EP12
BF88_53D0
U1EP13
BF88_53E0
U1EP14
USB REGISTERS MAP (CONTINUED)
Bits
31/15
Bits
30/14
Bits
29/13
Bits
28/12
Bits
27/11
Bits
26/10
Bits
25/9
Bits
24/8
Bits
23/7
Bits
22/6
Bits
21/5
Bits
20/4
Bits
19/3
Bits
18/2
Bits
17/1
Bits
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCON
DIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCON
DIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EPCON
DIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCON
DIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Preliminary
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCON
DIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EPCON
DIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
BF88_53F0
U1EP15
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
15:0
—
—
—
—
—
—
—
—
—
—
PIC32MX3XX/4XX
DS61143F-page 54
TABLE 4-25:
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
5.0
FLASH PROGRAM MEMORY
Note:
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 5.
“Flash Program Memory” (DS61121) for
a detailed description of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
PIC32MX3XX/4XX devices contain an internal
program Flash memory for executing user code. There
are three methods by which the user can program this
memory:
1.
2.
3.
Run-Time Self Programming (RTSP)
In-Circuit Serial Programming™ (ICSP™)
EJTAG Programming
RTSP is performed by software executing from either
Flash or RAM memory. EJTAG is performed using the
EJTAG port of the device and a EJTAG capable programmer. ICSP is performed using a serial data connection to the device and allows much faster
programming times than RTSP. RTSP techniques are
described in this chapter. The ICSP and EJTAG methods are described in the “PIC32MX3XX/4XX Programming Specification” (DS61145) document, which may
be downloaded from the Microchip web site.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 55
PIC32MX3XX/4XX
NOTES:
DS61143F-page 56
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
6.0
Note:
RESETS
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 7.
“Resets” (DS61118) for a detailed
description of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
The Reset module combines all Reset sources and
controls the device Master Reset signal, SYSRST. The
following is a list of device Reset sources:
•
•
•
•
•
•
POR: Power-on Reset
MCLR: Master Clear Reset Pin
SWR: Software Reset
WDTR: Watchdog Timer Reset
BOR: Brown-out Reset
CMR: Configuration Mismatch Reset
A simplified block diagram of the Reset module is
shown in Figure 6-1.
FIGURE 6-1:
SYSTEM RESET BLOCK DIAGRAM
MCLR
Glitch Filter
Sleep or Idle
WDTR
WDT
Time-out
Voltage
Regulator
Enabled
VDD
MCLR
Power-up
Timer
POR
Brown-out
Reset
BOR
SYSRST
VDD Rise
Detect
Configuration
Mismatch
Reset
CMR
SWR
Software Reset
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 57
PIC32MX3XX/4XX
NOTES:
DS61143F-page 58
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
7.0
INTERRUPT CONTROLLER
Note:
The PIC32MX3XX/4XX interrupts module includes the
following features:
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 8.
“Interrupt Controller” (DS61108) for a
detailed description of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
PIC32MX3XX/4XX devices generate interrupt requests
in response to interrupt events from peripheral modules. The Interrupt Control module exists externally to
the CPU logic and prioritizes the interrupt events before
presenting them to the CPU.
Interrupt Requests
FIGURE 7-1:
•
•
•
•
•
•
•
•
•
•
•
•
Up to 96 interrupt sources
Up to 64 interrupt vectors
Single and Multi-Vector mode operations
5 external interrupts with edge polarity control
Interrupt proximity timer
Module Freeze in Debug mode
7 user-selectable priority levels for each vector
4 user-selectable subpriority levels within each
priority
Dedicated shadow set for highest priority level
Software can generate any interrupt
User-configurable interrupt vector table location
User-configurable interrupt vector spacing
INTERRUPT CONTROLLER MODULE
Vector Number
Interrupt Controller
Priority Level
CPU Core
Shadow Set Number
Note:
Several of the registers cited in this section are not in the interrupt controller module. These registers (and
bits) are associated with the CPU. Details about them are available in Section 3.0 "PIC32MX MCU".
To avoid confusion, a typographic distinction is made for registers in the CPU. The register names in this
section, and all other sections of this manual, are signified by uppercase letters only.CPU register names
are signified by upper and lowercase letters. For example, INTSTAT is an Interrupts register; whereas,
IntCtl is a CPU register.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 59
PIC32MX3XX/4XX
TABLE 7-1:
INTERRUPT IRQ AND VECTOR LOCATION
Interrupt Source(1)
IRQ
Vector
Number
Highest Natural Order Priority
CT – Core Timer Interrupt
0
0
Interrupt Bit Location
Flag
Enable
Priority
Subpriority
IFS0<0>
IEC0<0>
IPC0<4:2>
IPC0<1:0>
CS0 – Core Software Interrupt 0
1
1
IFS0<1>
IEC0<1>
IPC0<12:10>
IPC0<9:8>
CS1 – Core Software Interrupt 1
2
2
IFS0<2>
IEC0<2>
IPC0<20:18>
IPC0<17:16>
INT0 – External Interrupt 0
3
3
IFS0<3>
IEC0<3>
IPC0<28:26>
IPC0<25:24>
T1 – Timer1
4
4
IFS0<4>
IEC0<4>
IPC1<4:2>
IPC1<1:0>
IC1 – Input Capture 1
5
5
IFS0<5>
IEC0<5>
IPC1<12:10>
IPC1<9:8>
OC1 – Output Compare 1
6
6
IFS0<6>
IEC0<6>
IPC1<20:18>
IPC1<17:16>
INT1 – External Interrupt 1
7
7
IFS0<7>
IEC0<7>
IPC1<28:26>
IPC1<25:24>
T2 – Timer2
8
8
IFS0<8>
IEC0<8>
IPC2<4:2>
IPC2<1:0>
IC2 – Input Capture 2
9
9
IFS0<9>
IEC0<9>
IPC2<12:10>
IPC2<9:8>
OC2 – Output Compare 2
10
10
IFS0<10>
IEC0<10>
IPC2<20:18>
IPC2<17:16>
INT2 – External Interrupt 2
11
11
IFS0<11>
IEC0<11>
IPC2<28:26>
IPC2<25:24>
T3 – Timer3
12
12
IFS0<12>
IEC0<12>
IPC3<4:2>
IPC3<1:0>
IC3 – Input Capture 3
13
13
IFS0<13>
IEC0<13>
IPC3<12:10>
IPC3<9:8>
OC3 – Output Compare 3
14
14
IFS0<14>
IEC0<14>
IPC3<20:18>
IPC3<17:16>
INT3 – External Interrupt 3
15
15
IFS0<15>
IEC0<15>
IPC3<28:26>
IPC3<25:24>
T4 – Timer4
16
16
IFS0<16>
IEC0<16>
IPC4<4:2>
IPC4<1:0>
IC4 – Input Capture 4
17
17
IFS0<17>
IEC0<17>
IPC4<12:10>
IPC4<9:8>
OC4 – Output Compare 4
18
18
IFS0<18>
IEC0<18>
IPC4<20:18>
IPC4<17:16>
INT4 – External Interrupt 4
19
19
IFS0<19>
IEC0<19>
IPC4<28:26>
IPC4<25:24>
T5 – Timer5
20
20
IFS0<20>
IEC0<20>
IPC5<4:2>
IPC5<1:0>
IC5 – Input Capture 5
21
21
IFS0<21>
IEC0<21>
IPC5<12:10>
IPC5<9:8>
OC5 – Output Compare 5
22
22
IFS0<22>
IEC0<22>
IPC5<20:18>
IPC5<17:16>
SPI1E – SPI1 Fault
23
23
IFS0<23>
IEC0<23>
IPC5<28:26>
IPC5<25:24>
SPI1TX – SPI1 Transfer Done
24
23
IFS0<24>
IEC0<24>
IPC5<28:26>
IPC5<25:24>
SPI1RX – SPI1 Receive Done
25
23
IFS0<25>
IEC0<25>
IPC5<28:26>
IPC5<25:24>
U1E – UART1 Error
26
24
IFS0<26>
IEC0<26>
IPC6<4:2>
IPC6<1:0>
U1RX – UART1 Receiver
27
24
IFS0<27>
IEC0<27>
IPC6<4:2>
IPC6<1:0>
U1TX – UART1 Transmitter
28
24
IFS0<28>
IEC0<28>
IPC6<4:2>
IPC6<1:0>
I2C1B – I2C1 Bus Collision Event
29
25
IFS0<29>
IEC0<29>
IPC6<12:10>
IPC6<9:8>
I2C1S – I2C1 Slave Event
30
25
IFS0<30>
IEC0<30>
IPC6<12:10>
IPC6<9:8>
I2C1M – I2C1 Master Event
31
25
IFS0<31>
IEC0<31>
IPC6<12:10>
IPC6<9:8>
CN – Input Change Interrupt
32
26
IFS1<0>
IEC1<0>
IPC6<20:18>
IPC6<17:16>
AD1 – ADC1 Convert Done
33
27
IFS1<1>
IEC1<1>
IPC6<28:26>
IPC6<25:24>
PMP – Parallel Master Port
34
28
IFS1<2>
IEC1<2>
IPC7<4:2>
IPC7<1:0>
CMP1 – Comparator Interrupt
35
29
IFS1<3>
IEC1<3>
IPC7<12:10>
IPC7<9:8>
CMP2 – Comparator Interrupt
36
30
IFS1<4>
IEC1<4>
IPC7<20:18>
IPC7<17:16>
Note 1:
Not all interrupt sources are available on all devices.
See Table 1: “PIC32MX General Purpose – Features” and Table 2: “PIC32MX USB – Features” for
available peripherals.
DS61143F-page 60
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 7-1:
INTERRUPT IRQ AND VECTOR LOCATION (CONTINUED)
Interrupt Source(1)
IRQ
Vector
Number
Highest Natural Order Priority
SPI2E – SPI2 Fault
37
31
Interrupt Bit Location
Flag
Enable
Priority
Subpriority
IFS1<5>
IEC1<5>
IPC7<28:26>
IPC7<25:24>
SPI2TX – SPI2 Transfer Done
38
31
IFS1<6>
IEC1<6>
IPC7<28:26>
IPC7<25:24>
SPI2RX – SPI2 Receive Done
39
31
IFS1<7>
IEC1<7>
IPC7<28:26>
IPC7<25:24>
U2E – UART2 Error
40
32
IFS1<8>
IEC1<8>
IPC8<4:2>
IPC8<1:0>
U2RX – UART2 Receiver
41
32
IFS1<9>
IEC1<9>
IPC8<4:2>
IPC8<1:0>
U2TX – UART2 Transmitter
42
32
IFS1<10>
IEC1<10>
IPC8<4:2>
IPC8<1:0>
I2C2B – I2C2 Bus Collision Event
43
33
IFS1<11>
IEC1<11>
IPC8<12:10>
IPC8<9:8>
I2C2S – I2C2 Slave Event
44
33
IFS1<12>
IEC1<12>
IPC8<12:10>
IPC8<9:8>
I2C2M – I2C2 Master Event
45
33
IFS1<13>
IEC1<13>
IPC8<12:10>
IPC8<9:8>
FSCM – Fail-Safe Clock Monitor
46
34
IFS1<14>
IEC1<14>
IPC8<20:18>
IPC8<17:16>
RTCC – Real-Time Clock
47
35
IFS1<15>
IEC1<15>
IPC8<28:26>
IPC8<25:24>
DMA0 – DMA Channel 0
48
36
IFS1<16>
IEC1<16>
IPC9<4:2>
IPC9<1:0>
DMA1 – DMA Channel 1
49
37
IFS1<17>
IEC1<17>
IPC9<12:10>
IPC9<9:8>
DMA2 – DMA Channel 2
50
38
IFS1<18>
IEC1<18>
IPC9<20:18>
IPC9<17:16>
DMA3 – DMA Channel 3
51
39
IFS1<19>
IEC1<19>
IPC9<28:26>
IPC9<25:24>
FCE – Flash Control Event
56
44
IFS1<24>
IEC1<24>
IPC11<4:2>
IPC11<1:0>
USB
57
45
IFS1<25>
IEC1<25>
IPC11<12:10>
IPC11<9:8>
(Reserved)
Lowest Natural Order Priority
Note 1:
Not all interrupt sources are available on all devices.
See Table 1: “PIC32MX General Purpose – Features” and Table 2: “PIC32MX USB – Features” for
available peripherals.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 61
PIC32MX3XX/4XX
NOTES:
DS61143F-page 62
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
8.0
Note:
OSCILLATOR
CONFIGURATION
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 6.
“Oscillator Configuration” (DS61112) for
a detailed description of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
The PIC32MX oscillator system has the following
modules and features:
• A total of four external and internal oscillator
options as clock sources
• On-chip PLL (phase-locked loop) with userselectable input divider, multiplier, and output
divider to boost operating frequency on select
internal and external oscillator sources
• On-chip user-selectable divisor postscaler on
select oscillator sources
• Software-controllable switching between various
clock sources
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and permits safe application recovery
or shutdown
• Dedicated on-chip PLL for USB peripheral
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 63
PIC32MX3XX/4XX
FIGURE 8-1:
PIC32MX3XX/4XX FAMILY CLOCK DIAGRAM
USB PLL
UFIN
div x
OSC1
C1(3)
RF(2)
C2(3)
div 2
UFRCEN
FUPLLEN
UFIN = 4 MHz
FUPLLDIV<2:0>
Primary Oscillator
POSC
XTAL
USB Clock (48 MHz)
PLL x24
XT, HS, EC
To Internal
Logic
4 MHz ≤ FIN ≤ 5 MHz
XTPLL, HSPLL,
FIN
ECPLL, FRCPLL
div x
div y
PLL
Enable
Postscaler Peripherals
div x
PBCLK
RS(1)
PLL Input Divider
FPLLIDIV<2:0>
OSC2(4)
FRC
Oscillator
8 MHz typical
PLL Multiplier
PLLMULT<2:0>
COSC<2:0>
TUN<5:0>
div 16
Postscaler
FRCDIV<2:0>
LPRC
Oscillator
PBDIV<2:0>
PLL Output Divider
PLLODIV<2:0>
FRC
CPU and Select Peripherals
FRC /16
FRCDIV
LPRC
31.25 kHz typical
Secondary Oscillator (SOSC)
SOSCO
32.768 kHz
SOSC
SOSCEN and FSOSCEN
Clock Control Logic
SOSCI
Fail-Safe
Clock
Monitor
FSCM INT
FSCM Event
NOSC<2:0>
COSC<2:0>
OSWEN
FSCMEN<1:0>
WDT, PWRT
Timer1, RTCC
Notes: 1. A series resistor, RS, may be required for AT strip cut crystals.
2. The internal feedback resistor, RF, is typically in the range of 2 to 10 MΩ.
3. Refer to the “PIC32MX Family Reference Manual” Section 6. “Oscillator Configuration” (DS61112) for help
determining the best oscillator components.
4. PBCLK out is available on the OSC2 pin in certain clock modes.
DS61143F-page 64
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
PREFETCH CACHE
Note:
9.1
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 4.
“Prefetch Cache” (DS61119) for a detailed
description of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
Prefetch cache increases performance for applications
executing out of the cacheable program flash memory
regions by implementing instruction caching, constant
data caching, and instruction prefetching.
FIGURE 9-1:
•
•
•
•
16 Fully Associative Lockable Cache Lines
16-byte Cache Lines
Up to 4 Cache Lines Allocated to Data
2 Cache Lines with Address Mask to hold
repeated instructions
Pseudo LRU replacement policy
All Cache Lines are software writable
16-byte parallel memory fetch
Predictive Instruction Prefetch
PREFETCH MODULE BLOCK DIAGRAM
FSM
BMX/CPU
•
•
•
•
CTRL
Tag Logic
CTRL
Features
Cache Line
Bus Ctrl
BMX/CPU
9.0
Cache Ctrl
Prefetch Ctrl
Cache
Line
Address
Encode
Hit LRU
Miss LRU
RDATA
Hit Logic
PreFetch
Pre-Fetch
CTRL
RDATA
PreFetch
Pre-Fetch
Tag
PFM
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 65
PIC32MX3XX/4XX
NOTES:
DS61143F-page 66
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
10.0
Note:
DIRECT MEMORY ACCESS
(DMA) CONTROLLER
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 31.
“Direct Memory Access (DMA) Controller” (DS61117) for a detailed description of
this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
The PIC32MX Direct Memory Access (DMA) controller
is a bus master module useful for data transfers
between different devices without CPU intervention.
The source and destination of a DMA transfer can be
any of the memory mapped modules existent in the
PIC32MX (such as Peripheral Bus (PBUS) devices:
SPI, UART, I2C™, etc.) or memory itself.
Following are some of the key features of the DMA
controller module:
• Four Identical Channels, each featuring:
- Auto-Increment Source and Destination
Address Registers
- Source and Destination Pointers
- Memory to Memory and Memory to
Peripheral Transfers
• Automatic Word-Size Detection:
- Transfer Granularity, down to byte level
- Bytes need not be word-aligned at source
and destination
FIGURE 10-1:
DMA BLOCK DIAGRAM
INT Controller
Peripheral Bus
• Fixed Priority Channel Arbitration
• Flexible DMA Channel Operating Modes:
- Manual (software) or automatic (interrupt)
DMA requests
- One-Shot or Auto-Repeat Block Transfer
modes
- Channel-to-channel chaining
• Flexible DMA Requests:
- A DMA request can be selected from any of
the peripheral interrupt sources
- Each channel can select any (appropriate)
observable interrupt as its DMA request
source
- A DMA transfer abort can be selected from
any of the peripheral interrupt sources
- Pattern (data) match transfer termination
• Multiple DMA Channel Status Interrupts:
- DMA channel block transfer complete
- Source empty or half empty
- Destination full or half-full
- DMA transfer aborted due to an external
event
- Invalid DMA address generated
• DMA Debug Support Features:
- Most recent address accessed by a DMA
channel
- Most recent DMA channel to transfer data
• CRC Generation Module:
- CRC module can be assigned to any of the
available channels
- CRC module is highly configurable
System IRQ
Address Decoder
SE
L
Channel 0 Control
I0
Channel 1 Control
I1
Y
Bus Interface
Device Bus + Bus Arbitration
I2
Global Control
(DMACON)
In
Channel n Control
L
SE
Channel Priority
Arbitration
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 67
PIC32MX3XX/4XX
NOTES:
DS61143F-page 68
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
11.0
Note:
USB ON-THE-GO (OTG)
The PIC32MX USB module includes the following
features:
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 27.
“USB On-The-Go (OTG)” (DS61126) for a
detailed description of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
The Universal Serial Bus (USB) module contains analog and digital components to provide a USB 2.0 fullspeed and low-speed embedded host, full-speed
device, or OTG implementation with a minimum of
external components. This module in Host mode is
intended for use as an embedded host and therefore
does not implement a UHCI or OHCI controller.
•
•
•
•
•
•
•
•
•
USB Full-Speed Support for Host and Device
Low-Speed Host Support
USB OTG Support
Integrated Signaling Resistors
Integrated Analog Comparators for VBUS
Monitoring
Integrated USB Transceiver
Transaction Handshaking Performed by
Hardware
Endpoint Buffering Anywhere in System RAM
Integrated DMA to Access System RAM and
Flash
Note:
The USB module consists of the clock generator, the
USB voltage comparators, the transceiver, the Serial
Interface Engine (SIE), a dedicated USB DMA controller, pull-up and pull-down resistors, and the register
interface. A block diagram of the PIC32MX USB OTG
module is presented in Figure 11-1.
The clock generator provides the 48 MHz clock
required for USB full-speed and low-speed communication. The voltage comparators monitor the voltage on
the VBUS pin to determine the state of the bus. The
transceiver provides the analog translation between
the USB bus and the digital logic. The SIE is a state
machine that transfers data to and from the endpoint
buffers, and generates the hardware protocol for data
transfers. The USB DMA controller transfers data
between the data buffers in RAM and the SIE. The integrated pull-up and pull-down resistors eliminate the
need for external signaling components. The register
interface allows the CPU to configure and
communicate with the module.
© 2009 Microchip Technology Inc.
Preliminary
IMPORTANT: The implementation and
use of the USB specifications, as well as
other third-party specifications or technologies, may require licensing; including,
but not limited to, USB Implementers
Forum, Inc. (also referred to as USB-IF).
The user is fully responsible for investigating and satisfying any applicable licensing
obligations.
DS61143F-page 69
PIC32MX3XX/4XX
FIGURE 11-1:
PIC32MX3XX/4XX FAMILY USB INTERFACE DIAGRAM
USBEN
FRC
Oscillator
8 MHz Typical
USB Suspend
CPU Clock Not POSC
Sleep
TUN<5:0>(4)
Primary Oscillator
(POSC)
Div x
OSC1
UFIN(5)
PLL
Div 2
FUPLLEN(6)
FUPLLIDIV(6)
UFRCEN(3)
To Clock Generator for Core and Peripherals
USB Suspend
OSC2
(PB out)(1)
Sleep or Idle
USB Module
USB
Voltage
Comparators
SRP Charge
VBUS
SRP Discharge
48 MHz USB Clock(7)
Full Speed Pull-up
D+(2)
Registers
and
Control
Interface
Host Pull-down
Low Speed Pull-up
SIE
Transceiver
D-(2)
DMA
System
RAM
Host Pull-down
ID Pull-up
ID(8)
VBUSON(8)
Transceiver Power 3.3V
VUSB
Note 1:
2:
3:
4:
5:
6:
7:
8:
PB clock is only available on this pin for select EC modes.
Pins can be used as digital inputs when USB is not enabled.
This bit field is contained in the OSCCON register.
This bit field is contained in the OSCTRM register.
USB PLL UFIN requirements: 4 MHz.
This bit field is contained in the DEVCFG2 register.
A 48 MHz clock is required for proper USB operation.
Pins can be used as GPIO when the USB module is disabled.
DS61143F-page 70
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
12.0
I/O PORTS
These functions depend on which peripheral features
are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose
I/O pin.
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 12. “I/O
Ports” (DS61120) for a detailed description
of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
Note:
Following are some of the key features of this module:
• Individual output pin open-drain enable/disable
• Individual input pin weak pull-up enable/disable
• Monitor selective inputs and generate interrupt
when change in pin state is detected
• Operation during CPU Sleep and Idle modes
• Fast bit manipulation using CLR, SET and INV
registers
Figure 12-1 shows a block diagram of a typical
multiplexed I/O port.
General purpose I/O pins are the simplest of peripherals. They allow the PIC® MCU to monitor and control
other devices. To add flexibility and functionality, some
pins are multiplexed with alternate function(s).
FIGURE 12-1:
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
Peripheral Module
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
PIO Module
RD ODC
Data Bus
D
SYSCLK
Q
ODC
CK
EN Q
WR ODC
1
RD TRIS
0
0
IO Cell
1
D
Q
1
TRIS
CK
EN Q
WR TRIS
0
Output Multiplexers
D
Q
IO Pin
LAT
CK
Q
EN
WR LAT
WR PORT
RD LAT
1
RD PORT
0
Sleep
Q
Q
D
CK
Q
Q
D
CK
SYSCLK
Synchronization
Peripheral Input
Peripheral Input Buffer
R
Legend: R = Peripheral input buffer types may vary. Refer to Table 1-1 for more information.
Note:
This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The
actual structure for any specific port/peripheral combination may be different than it is shown here.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F - page 71
PIC32MX3XX/4XX
12.1
Parallel I/O (PIO) Ports
12.1.2
All port pins have three registers (TRIS, LAT, and
PORT) that are directly associated with their operation.
TRIS is a data direction or tri-state control register that
determines whether a digital pin is an input or an output. Setting a TRISx register bit = 1 configures the corresponding I/O pin as an input; setting a TRISx register
bit = 0 configures the corresponding I/O pin as an output. All port I/O pins are defined as inputs after a device
Reset. Certain I/O pins are shared with analog
peripherals and default to analog inputs after a device
Reset.
PORT is a register used to read the current state of the
signal applied to the port I/O pins. Writing to a PORTx
register performs a write to the port’s latch, LATx register, latching the data to the port’s I/O pins.
LAT is a register used to write data to the port I/O pins.
The LATx latch register holds the data written to either
the LATx or PORTx registers. Reading the LATx latch
register reads the last value written to the
corresponding port or latch register.
Not all port I/O pins are implemented on some devices,
therefore, the corresponding PORTx, LATx and TRISx
register bits will read as zeros.
12.1.1
Pins are configured as digital inputs by setting the corresponding TRIS register bits = 1. When configured as
inputs, they are either TTL buffers or Schmitt Triggers.
Several digital pins share functionality with analog
inputs and default to the analog inputs at POR. Setting
the corresponding bit in the AD1PCFG register = 1
enables the pin as a digital pin.
Digital only pins are capable of input voltages up to
5.5V. Any pin that shares digital and analog
functionality is limited to voltages up to VDD + 0.3V.
.
TABLE 12-1:
Reading SET, CLR and INV registers returns undefined
values. To see the affects of a write operation to a SET,
CLR or INV register, the base register must be read.
To set PORTC bit 0, write to the LATSET register:
LATCSET = 0x0001;
MAXIMUM INPUT PIN
VOLTAGES
Input Pin Mode(s)
VIH (max)
Digital Only
VIH = 5.5v
Digital + Analog
VIH = VDD + 0.03v
Analog
VIH = VDD + 0.03v
Note: Refer to Section 28.0 “Electrical Characteristics” regarding the VIH specification.
Note:
CLR, SET AND INV REGISTERS
Every I/O module register has a corresponding CLR
(clear), SET (set) and INV (invert) register designed to
provide fast atomic bit manipulations. As the name of
the register implies, a value written to a SET, CLR or
INV register effectively performs the implied operation,
but only on the corresponding base register and only
bits specified as ‘1’ are modified. Bits specified as ‘0’
are not modified.
DIGITAL INPUTS
12.1.3
Analog levels on any pin that is defined as
a digital input (including the ANx pins) may
cause the input buffer to consume current
that exceeds the device specifications.
ANALOG INPUTS
Certain pins can be configured as analog inputs used
by the ADC and Comparator modules. Setting the corresponding bits in the AD1PCFG register = 0 enables
the pin as an analog input pin and must have the corresponding TRIS bit set = 1 (input). If the TRIS bit is
cleared = 0 (output), the digital output level (VOH or
VOL) will be converted. Any time a port I/O pin is configured as analog, its digital input is disabled and the corresponding PORTx register bit will read ‘0’. The
AD1PCFG Register has a default value of 0x0000;
therefore, all pins that share ANx functions are analog
(not digital) by default.
To clear PORTC bit 0, write to the LATCLR register:
12.1.4
LATCCLR = 0x0001;
Pins are configured as digital outputs by setting the corresponding TRIS register bits = 0. When configured as
digital outputs, these pins are CMOS drivers or can be
configured as open drain outputs by setting the corresponding bits in the ODCx Open-Drain Configuration
register.
To toggle PORTC bit 0, write to the LATINV register:
LATCINV = 0x0001;
Note:
Using a PORTxINV register to toggle a bit
is recommended because the operation is
performed in hardware atomically, using
fewer instructions as compared to the traditional read-modify-write method shown
below:
PORTC ^= 0x0001;
DS61143F - page 72
DIGITAL OUTPUTS
Digital output pin voltage is limited to VDD.
12.1.5
ANALOG OUTPUTS
Certain pins can be configured as analog outputs, such
as the CVREF output voltage used by the comparator
module. Configuring the Comparator Reference module to provide this output will present the analog output
voltage on the pin, independent of the TRIS register
setting for the corresponding pin.
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
13.0
Note:
TIMER1
13.1
Additional Supported Features
• Selectable clock prescaler
• Timer operation during CPU Idle and Sleep mode
• Fast bit manipulation using CLR, SET and INV
registers
• Asynchronous mode can be used with the SOSC
to function as a Real-Time Clock (RTC).
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 14.
“Timers” (DS61105) for a detailed
description of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
This family of PIC32MX devices features one
synchronous/asynchronous 16-bit timer that can operate as a free-running interval timer for various timing
applications and counting external events. This timer
can also be used with the Low-Power Secondary
Oscillator (SOSC) for real-time clock applications. The
following modes are supported:
•
•
•
•
Synchronous Internal Timer
Synchronous Internal Gated Timer
Synchronous External Timer
Asynchronous External Timer
FIGURE 13-1:
TIMER1 BLOCK DIAGRAM(1)
PR1
Equal
16-bit Comparator
TSYNC (T1CON<2>)
1
Reset
T1IF
Event Flag
Sync
TMR1
0
0
1
Q
TGATE (T1CON<7>)
TGATE (T1CON<7>)
D
Q
TCS (T1CON<1>)
ON (T1CON<15>)
SOSCO/T1CK
x1
SOSCEN
SOSCI
Gate
Sync
PBCLK
10
00
Prescaler
1, 8, 64, 256
2
TCKPS<1:0>
(T1CON<5:4>)
Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in
Configuration Word DEVCFG1.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 73
PIC32MX3XX/4XX
NOTES:
DS61143F-page 74
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
14.0
TIMERS 2, 3, 4, 5
Note:
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 14.
“Timers” (DS61105) for a detailed
description of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
Note:
14.1
Throughout this chapter, references to
registers TxCON, TMRx, and PRx use ‘x’
to represent Timer2 through 5 in 16-bit
modes. In 32-bit modes, ‘x’ represents
Timer2 or 4; ‘y’ represents Timer3 or 5.
Additional Supported Features
• Selectable clock prescaler
• Timers operational during CPU Idle
• Time base for input capture and output compare
modules (Timer2 and Timer3 only)
• ADC event trigger (Timer3 only)
• Fast bit manipulation using CLR, SET and INV
registers
This family of PIC32MX devices features four
synchronous 16-bit timers (default) that can operate as
a free-running interval timer for various timing applications and counting external events. The following
modes are supported:
• Synchronous Internal 16-bit Timer
• Synchronous Internal 16-bit Gated Timer
• Synchronous External 16-bit Timer
Two 32-bit synchronous timers are available by
combining Timer2 with Timer3 and Timer4 with Timer5.
The 32-bit timers can operate in three modes:
• Synchronous Internal 32-bit Timer
• Synchronous Internal 32-bit Gated Timer
• Synchronous External 32-bit Timer
FIGURE 14-1:
TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT)
Sync
TMRx
ADC Event
Trigger(1)
Equal
Comparator x 16
PRx
Reset
TxIF
Event Flag
0
1
TGATE (TxCON<7>)
Q
TGATE (TxCON<7>)
D
Q
TCS (TxCON<1>)
ON (TxCON<15>)
TxCK(2)
x1
Gate
Sync
PBCLK
10
00
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
3
TCKPS (TxCON<6:4>)
Note 1: ADC event trigger is available on Timer3 only.
2: TxCK pins not available on 64-pin devices.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 75
PIC32MX3XX/4XX
FIGURE 14-2:
TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)
Reset
TMRy
MSHalfWord
ADC Event
Trigger(3)
Equal
Sync
LSHalfWord
32-bit Comparator
PRy
TyIF Event
Flag
TMRx
PRx
0
1
TGATE (TxCON<7>)
Q
D
TGATE (TxCON<7>)
Q
TCS (TxCON<1>)
ON (TxCON<15>)
TxCK(2)
x1
Gate
Sync
PBCLK
10
00
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
3
TCKPS (TxCON<6:4>)
Note 1: In this diagram, the use of “x’ in registers TxCON, TMRx, PRx, TxCK refers to either
Timer2 or Timer4; the use of ‘y’ in registers TyCON, TMRy, PRy, TyIF refers to either Timer3 or Timer5.
2: TxCK pins not available on 64-pin devices.
3: ADC event trigger is available only on Timer2/3 pair.
DS61143F-page 76
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
15.0
Note:
INPUT CAPTURE
2.
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 15.
“Input Capture” (DS61122) for a detailed
description of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
The Input Capture module is useful in applications
requiring frequency (period) and pulse measurement.
The PIC32MX3XX/4XX devices support up to five input
capture channels.
The input capture module captures the 16-bit or 32-bit
value of the selected Time Base registers when an
event occurs at the ICx pin. The events that cause a
capture event are listed below in three categories:
1.
Simple Capture Event modes
- Capture timer value on every falling edge of
input at ICx pin
- Capture timer value on every rising edge of
input at ICx pin
FIGURE 15-1:
Capture timer value on every edge (rising and
falling)
3. Capture timer value on every edge (rising and
falling), specified edge first.
4. Prescaler Capture Event modes
- Capture timer value on every 4th rising edge
of input at ICx pin
- Capture timer value on every 16th rising
edge of input at ICx pin
Each input capture channel can select between one of
two 16-bit timers (Timer2 or Timer3) for the time base,
or two 16-bit timers (Timer2 and Timer3) together to
form a 32-bit timer. The selected timer can use either
an internal or external clock.
Other operational features include:
• Device wake-up from capture pin during CPU
Sleep and Idle modes
• Interrupt on input capture event
• 4-word FIFO buffer for capture values
- Interrupt optionally generated after 1, 2, 3 or
4 buffer locations are filled
• Input capture can also be used to provide
additional sources of external interrupts
INPUT CAPTURE BLOCK DIAGRAM
ICx Input
Timer 3 Timer 2
ICTMR
0
1
ICC32
FIFO Control
ICxBUF<31:16>
Prescaler
1, 4, 16
ICxBUF<15:0>
Edge Detect
ICBNE
ICOV
ICM<2:0>
ICFEDGE
ICM<2:0>
ICxCON
ICI<1:0>
Interrupt
Event
Generation
Data Space Interface
Interrupt
© 2009 Microchip Technology Inc.
Preliminary
Peripheral Data Bus
DS61143F-page 77
PIC32MX3XX/4XX
NOTES:
DS61143F-page 78
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
16.0
OUTPUT COMPARE
Note:
The following are some of the key features:
• Multiple output compare modules in a device
• Programmable interrupt generation on compare
event
• Single and Dual Compare modes
• Single and continuous output pulse generation
• Pulse-Width Modulation (PWM) mode
• Hardware-based PWM Fault detection and automatic output disable
• Programmable selection of 16-bit or 32-bit time
bases.
• Can operate from either of two available 16-bit
time bases or a single 32-bit time base.
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 16.
“Output Capture”
(DS61111) for a
detailed description of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
The Output Compare module (OCMP) is used to generate a single pulse or a train of pulses in response to
selected time base events. For all modes of operation,
the OCMP module compares the values stored in the
OCxR and/or the OCxRS registers to the value in the
selected timer. When a match occurs, the OCMP module generates an event based on the selected mode of
operation.
FIGURE 16-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit
OCxIF(1)
OCxRS(1)
Output
Logic
OCxR(1)
3
OCM<2:0>
Mode Select
Comparator
0
16
OCTSEL
1
0
S
R
Q
OCx(1)
Output Enable
OCFA or OCFB
(see Note 2)
1
16
TMR register inputs
from time bases
(see Note 3).
Period match signals
from time bases
(see Note 3).
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
channels 1 through 5.
2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel.
3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 79
PIC32MX3XX/4XX
NOTES:
DS61143F-page 80
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
17.0
Note:
SERIAL PERIPHERAL
INTERFACE (SPI)
Following are some of the key features of this module:
•
•
•
•
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 23.
“Serial Peripheral Interface (SPI)”
(DS61106) for a detailed description of this
peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
Master and Slave Modes Support
Four Different Clock Formats
Framed SPI Protocol Support
User Configurable 8-bit, 16-bit and 32-bit Data
Width
Separate SPI Data Registers for Receive and
Transmit
Programmable Interrupt Event on every 8-bit,
16-bit and 32-bit Data Transfer
Operation during CPU Sleep and Idle Mode
Fast Bit Manipulation using CLR, SET and INV
Registers
•
•
•
•
The SPI module is a synchronous serial interface useful for communicating with external peripherals and
other microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The PIC32MX SPI
module is compatible with Motorola® SPI and SIOP
interfaces.
FIGURE 17-1:
SPI MODULE BLOCK DIAGRAM
Internal
Data Bus
SPIxBUF
Read
Write
SPIxRXB
Registers share address SPIxBUF
SPIxTXB
Transmit
Receive
SPIxSR
SDIx
bit 0
SDOx
SSx/FSYNC
Shift
Control
Slave Select
and Frame
Sync Control
Clock
Control
Edge
Select
Baud Rate
Generator
PBCLK
SCKx
Enable Master Clock
Note: Access SPIxTXB and SPIxRXB registers via SPIxBUF register.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 81
PIC32MX3XX/4XX
NOTES:
DS61143F-page 82
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
18.0
Note:
INTER-INTEGRATED CIRCUIT
(I2C™)
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 24.
“Inter-Integrated Circuit (I2C)” (DS61116)
for a detailed description of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
The I2C module provides complete hardware support
for both Slave and Multi-Master modes of the I2C serial
communication standard. Figure 18-1 shows the I2C
module block diagram.
The PIC32MX3XX/4XX devices have up to two I2C
interface modules, denoted as I2C1 and I2C2. Each
I2C module has a 2-pin interface: the SCLx pin is clock
and the SDAx pin is data.
Each I2C module ‘I2Cx’ (x = 1 or 2) offers the following
key features:
• I2C Interface Supporting both Master and Slave
Operation.
• I2C Slave Mode Supports 7 and 10-bit Address.
• I2C Master Mode Supports 7 and 10-bit Address.
• I2C Port allows Bidirectional Transfers between
Master and Slaves.
• Serial Clock Synchronization for I2C Port can be
used as a Handshake Mechanism to Suspend
and Resume Serial Transfer (SCLREL control).
• I2C Supports Multi-master Operation; Detects Bus
Collision and Arbitrates Accordingly.
• Provides Support for Address Bit Masking.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 83
PIC32MX3XX/4XX
FIGURE 18-1:
I2C™ BLOCK DIAGRAM (X = 1 OR 2)
Internal
Data Bus
I2CxRCV
SCLx
Read
Shift
Clock
I2CxRSR
LSB
SDAx
Address Match
Match Detect
Write
I2CxMSK
Write
Read
I2CxADD
Read
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
Control Logic
I2CxSTAT
Collision
Detect
Read
Write
I2CxCON
Acknowledge
Generation
Read
Clock
Stretching
Write
I2CxTRN
LSB
Read
Shift Clock
Reload
Control
Write
BRG Down Counter
I2CxBRG
Read
PBCLK
DS61143F-page 84
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
19.0
Note:
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 21.
“Universal Asynchronous Receiver Transmitter (UART)” (DS61107) for a detailed
description of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
The UART module is one of the serial I/O modules
available in PIC32MX3XX/4XX family devices. The
UART is a full-duplex, asynchronous communication
channel that communicates with peripheral devices
and personal computers through protocols such as RS232, RS-485, LIN 1.2 and IrDA®. The module also supports the hardware flow control option, with UxCTS and
UxRTS pins, and also includes an IrDA encoder and
decoder.
The primary features of the UART module are:
•
•
•
•
•
•
•
•
•
•
•
•
•
Full-duplex, 8-bit or 9-bit data transmission
Even, odd or no parity options (for 8-bit data)
One or two Stop bits
Hardware auto-baud feature
Hardware flow control option
Fully integrated Baud Rate Generator (BRG) with
16-bit prescaler
Baud rates ranging from 76 bps to 20 Mbps at 80
MHz
4-level-deep First-In-First-Out (FIFO) Transmit
Data Buffer
4-level-deep FIFO Receive Data Buffer
Parity, framing and buffer overrun error detection
Support for interrupt only on address detect (9th
bit = 1)
Separate transmit and receive interrupts
Loopback mode for diagnostic support
• LIN 1.2 protocol support
• IrDA encoder and decoder with 16x baud clock
output for external IrDA encoder/decoder support
Figure 19-1 shows a simplified block diagram of the
UART.
FIGURE 19-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
BCLKx
UxRTS
Hardware Flow Control
© 2009 Microchip Technology Inc.
UxCTS
UARTx Receiver
UxRX
UARTx Transmitter
UxTX
Preliminary
DS61143F-page 85
PIC32MX3XX/4XX
FIGURE 19-2:
Write to UxTXREG
BCLK/16
(Shift Clock)
UxTX
TRANSMISSION (8-BIT OR 9-BIT DATA)
Character 1
Start bit
bit 0
bit 1
Character 1
bit 7/8
Stop bit
UxTXIF Cleared by User
UxTXIF
Character 1 to
Transmit Shift Register
TRMT bit
FIGURE 19-3:
Write to UxTXREG
BCLK/16
(Shift Clock)
UxTX
UxTXIF
(UTXISEL0 = 0)
UxTXIF
(UTXISEL0 = 1)
TRMT bit
DS61143F-page 86
TWO CONSECUTIVE TRANSMISSIONS
Character 1 Character 2
Start bit
bit 0
bit 1
Character 1
bit 7/8
Stop bit
Start bit
bit 0
Character 2
UxTXIF Cleared by User in Software
Character 1 to
Transmit Shift Register
Preliminary
Character 2 to
Transmit Shift Register
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 19-4:
UART RECEPTION
UxRX
Start
bit bit 0
bit1
bit 7 Stop
bit
Start
bit bit 0
bit 7 Stop
bit
UxRXIF
(RXISEL = 0x)
Character 2
to UxRXREG
Character 1
to UxRXREG
RIDLE bit
Note:
This timing diagram shows 2 characters received on the UxRX input.
FIGURE 19-5:
UART RECEPTION WITH RECEIVE OVERRUN
Character 1
UxRX
Start
bit bit 0 bit 1
Characters 2, 3, 4, 5
bit 7/8 Stop
bit
Start
bit bit 0
Character 1, 2, 3, 4
Stored in Receive
FIFO
bit 7/8 Stop
bit
Character 6
Start
bit
bit 7/8 Stop
bit
Character 5
Held in UxRSR
OERR Cleared by User
OERR bit
RIDLE bit
Note:
This diagram shows 6 characters received without the user reading the input buffer. The 5th character
received is held in the Receive Shift register. An overrun error occurs at the start of the 6th character.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 87
PIC32MX3XX/4XX
NOTES:
DS61143F-page 88
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
20.0
PARALLEL MASTER PORT
(PMP)
Key features of the PMP module include:
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 13.
“Parallel Master Port (PMP)” (DS61128)
for a detailed description of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
Note:
The PMP is a parallel 8-bit/16-bit input/output module
specifically designed to communicate with a wide
variety of parallel devices, such as communications
peripherals, LCDs, external memory devices, and
microcontrollers. Because the interface to parallel
peripherals varies significantly, the PMP module is
highly configurable.
•
•
•
•
•
•
•
•
•
•
•
•
8-bit,16-bit interface
Up to 16 programmable address lines
Up to two Chip Select lines
Programmable strobe options
- Individual read and write strobes, or
- Read/write strobe with enable strobe
Address auto-increment/auto-decrement
Programmable address/data multiplexing
Programmable polarity on control signals
Parallel Slave Port support
- Legacy addressable
- Address support
- 4-byte deep auto-incrementing buffer
Programmable Wait states
Operate during CPU Sleep and Idle modes
Fast bit manipulation using CLR, SET and INV
registers
Freeze option for in-circuit debugging
Note:
FIGURE 20-1:
On 64-pin devices, data pins PMD<15:8>
are not available.
PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES
Address Bus
Data Bus
PIC32MX3XX/4XX
Parallel
Master Port
Control Lines
PMA<0>
PMALL
PMA<1>
PMALH
FLASH
EEPROM
SRAM
Up to 16-bit Address
PMA<13:2>
PMA<14>
PMCS1
PMA<15>
PMCS2
PMRD
PMRD/PMWR
Microcontroller
PMWR
PMENB
PMD<7:0>
PMD<15:8>(1)
Note 1:
LCD
FIFO
buffer
16/8-bit Data (with or without multiplexed addressing)
On 64-pin devices, data pins PMD<15:8> are not available in 16-bit Master modes
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 89
PIC32MX3XX/4XX
NOTES:
DS61143F-page 90
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
21.0
Note:
REAL-TIME CLOCK AND
CALENDAR (RTCC)
Following are some of the key features of this module:
•
•
•
•
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 29.
“Real-Time Clock and Calendar (RTCC)”
(DS61125) for a detailed description of this
peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
•
•
•
•
•
•
•
•
•
The PIC32MX RTCC module is intended for applications in which accurate time must be maintained for
extended periods of time with minimal or no CPU intervention. Low-power optimization provides extended
battery lifetime while keeping track of time.
•
•
•
•
FIGURE 21-1:
Time: Hours, Minutes and Seconds
24-Hour Format (Military Time)
Visibility of One-Half-Second Period
Provides Calendar: Weekday, Date, Month and
Year
Alarm Intervals are configurable for Half of a
Second, One Second, 10 Seconds, One Minute,
10 Minutes, One Hour, One Day, One Week, One
Month and One Year
Alarm Repeat with Decrementing Counter
Alarm with Indefinite Repeat: Chime
Year Range: 2000 to 2099
Leap Year Correction
BCD Format for Smaller Firmware Overhead
Optimized for Long-Term Battery Operation
Fractional Second Synchronization
User Calibration of the Clock Crystal Frequency
with Auto-Adjust
Calibration Range: ±0.66 Seconds Error per
Month
Calibrates up to 260 ppm of Crystal Error
Requirements: External 32.768 kHz Clock Crystal
Alarm Pulse or Seconds Clock Output on RTCC
pin
RTCC BLOCK DIAGRAM
32.768 kHz Input
from Secondary
Oscillator (SOSC)
RTCC Prescalers
0.5s
YEAR, MTH, DAY
RTCVAL
RTCC Timer
Alarm
Event
WKDAY
HR, MIN, SEC
Comparator
MTH, DAY
Compare Registers
with Masks
ALRMVAL
WKDAY
HR, MIN, SEC
Repeat Counter
RTCC Interrupt
RTCC Interrupt Logic
Alarm Pulse
Seconds Pulse
RTCC Pin
RTCOE
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 91
PIC32MX3XX/4XX
NOTES:
DS61143F-page 92
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
22.0
10-BIT ANALOG-TO-DIGITAL
CONVERTER (ADC)
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 17.
“10-bit
Analog-to-Digital
Converter
(ADC)” (DS61104) for a detailed
description of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
Note:
The PIC32MX3XX/4XX 10-bit Analog-to-Digital (A/D)
converter (or ADC) includes the following features:
• Successive Approximation Register (SAR)
conversion
• Up to 1000 kilo samples per second (ksps)
conversion speed
• Up to 16 analog input pins
• External voltage reference input pins
• One unipolar, differential Sample-and-Hold
Amplifier (SHA)
• Automatic Channel Scan mode
• Selectable conversion trigger source
• 16-word conversion result buffer
• Selectable Buffer Fill modes
• Eight conversion result format options
• Operation during CPU Sleep and Idle modes
FIGURE 22-1:
A block diagram of the 10-bit ADC is shown in
Figure 22-1. The 10-bit ADC has 16 analog input pins,
designated AN0-AN15. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs may be shared
with other analog input pins and may be common to
other analog module references.
The analog inputs are connected through two multiplexers (MUXs) to one SHA. The analog input MUXs
can be switched between two sets of analog inputs
between conversions. Unipolar differential conversions
are possible on all channels, other than the pin used as
the reference, using a reference input pin (see
Figure 22-1).
The Analog Input Scan mode sequentially converts
user-specified channels. A control register specifies
which analog input channels will be included in the
scanning sequence.
The 10-bit ADC is connected to a 16-word result buffer.
Each 10-bit result is converted to one of eight, 32-bit
output formats when it is read from the result buffer.
ADC1 MODULE BLOCK DIAGRAM
VREF+(1) AVDD
VCFG<2:0>
AN0
ADC1BUF0
ADC1BUF1
AN15
CHANNEL
SCAN
S/H
+
CH0SB<4:0>
CH0SA<4:0>
VREF-(1) AVSS
-
ADC1BUF2
VREFH
VREFL
SAR ADC
CSCNA
AN1
ADC1BUFE
VREFL
ADC1BUFF
CH0NA CH0NB
Alternate
Input Selection
Note
1:
VREF+, VREF- inputs can be multiplexed with other analog inputs.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 93
PIC32MX3XX/4XX
FIGURE 22-2:
ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM
ADRC
ADC Internal
RC Clock(1)
0
TAD
ADCS<7:0>
1
8
X2
TPB
ADC Conversion
Clock Multiplier
1, 2, 3, 4, 5,..., 512
Note
1:
See the ADC electrical characteristics for the exact RC clock value.
DS61143F-page 94
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
23.0
COMPARATOR
Note:
Following are some of the key features of this module:
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 19.
“Comparator”
(DS61110) for a detailed
description of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
• Selectable inputs available include:
- Analog inputs multiplexed with I/O pins
- On-chip internal absolute voltage reference
(IVREF)
- Comparator voltage reference (CVREF)
• Outputs can be inverted
• Selectable interrupt generation
A block diagram of the comparator module is shown in
Figure 23-1.
The PIC32MX3XX/4XX Analog Comparator module
contains one or more comparator(s) that can be configured in a variety of ways.
FIGURE 23-1:
COMPARATOR BLOCK DIAGRAM
Comparator 1
CREF
ON
C1IN+(2)
CPOL
COUT (CM1CON)
C1OUT (CMSTAT)
CVREF(3)
C1OUT
CCH<1:0>
C1
C1IN-
COE
C1IN+
C2IN+
IVREF(3)
Comparator 2
CREF
ON
C2IN+
CPOL
COUT (CM2CON)
C2OUT (CMSTAT)
CVREF(3)
C2OUT
CCH<1:0>
C2
C2IN-
COE
C2IN+
C1IN+
IVREF(3)
Note 1:
2:
3:
IVref is the internal 1.2V reference.
On USB variants, when USB is enabled, this pin is controlled by the USB module and therefore is not
available as a comparator input.
Internally connected.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 95
PIC32MX3XX/4XX
NOTES:
DS61143F-page 96
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
24.0
Note:
COMPARATOR VOLTAGE
REFERENCE (CVREF)
A block diagram of the module is shown in Figure 24-1.
The resistor ladder is segmented to provide two ranges
of voltage reference values and has a power-down function to conserve power when the reference is not being
used. The module’s supply reference can be provided
from either device VDD/VSS or an external voltage reference. The CVREF output is available for the comparators
and typically available for pin output.
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 20.
“Comparator
Voltage
Reference
(DS61109) for a detailed
(CVREF)”
description of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
The comparator voltage reference has the following
features:
• High and low range selection
• Sixteen output levels available for each range
• Internally connected to comparators to conserve
device pins
• Output can be connected to a pin
The CVREF is a 16-tap, resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog
comparators, it also may be used independently of
them.
FIGURE 24-1:
VREF+
AVDD
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
8R
CVRSS = 0
CVR3:CVR0
R
CVREN
CVREF
R
R
16-to-1 MUX
R
16 Steps
R
CVREFOUT
CVRCON<CVROE-
R
R
CVRR
VREFAVSS
© 2009 Microchip Technology Inc.
8R
CVRSS = 1
CVRSS = 0
Preliminary
DS61143F-page 97
PIC32MX3XX/4XX
NOTES:
DS61143F-page 98
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
25.0
Note:
POWER-SAVING FEATURES
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 10.
“Power-Saving Features”
(DS61130)
for a detailed description of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
This section describes power saving for the
PIC32MX3XX/4XX. The PIC32MX devices offer a total
of nine methods and modes that are organized into two
categories that allow the user to balance power consumption with device performance. In all of the methods and modes described in this section, power saving
is controlled by software.
25.1
Power Saving with CPU Running
When the CPU is running, power consumption can be
controlled by reducing the CPU clock frequency, lowering the PBCLK, and by individually disabling modules.
These methods are grouped into the following modes:
• FRC Run mode: the CPU is clocked from the FRC
clock source with or without postscalers.
• LPRC Run mode: the CPU is clocked from the
LPRC clock source.
• SOSC Run mode: the CPU is clocked from the
SOSC clock source.
• Peripheral Bus Scaling mode: peripherals are
clocked at programmable fraction of the CPU
clock (SYSCLK).
25.2
CPU Halted Methods
The device supports two power-saving modes, Sleep
and Idle, both of which halt the clock to the CPU. These
modes operate with all clock sources, as listed below:
• POSC Idle Mode: the system clock is derived
from the POSC. The system clock source
continues to operate.
Peripherals continue to operate, but can
optionally be individually disabled.
• FRC Idle Mode: the system clock is derived from
the FRC with or without postscalers. Peripherals
continue to operate, but can optionally be
individually disabled.
• SOSC Idle Mode: the system clock is derived
from the SOSC. Peripherals continue to operate,
but can optionally be individually disabled.
• LPRC Idle Mode: the system clock is derived from
the LPRC.
Peripherals continue to operate, but can optionally be individually disabled. This is the lowest
power mode for the device with a clock running.
© 2009 Microchip Technology Inc.
• Sleep Mode: the CPU, the system clock source,
and any peripherals that operate from the system
clock source, are halted.
Some peripherals can operate in Sleep using specific clock sources. This is the lowest power mode
for the device.
25.3
Power-Saving Operation
The purpose of all power saving is to reduce power
consumption by reducing the device clock frequency.
To achieve this, low-frequency clock sources can be
selected. In addition, the peripherals and CPU can be
halted or disabled to further reduce power consumption.
25.3.1
SLEEP MODE
Sleep mode has the lowest power consumption of the
device Power-Saving operating modes. The CPU and
most peripherals are halted. Select peripherals can
continue to operate in Sleep mode and can be used to
wake the device from Sleep. See individual peripheral
module sections for descriptions of behavior in Sleep.
Sleep mode includes the following characteristics:
• The CPU is halted.
• The system clock source is typically shut down.
See Section 25.4 “Peripheral Bus Scaling
Method” for specific information.
• There can be a wake-up delay based on the
oscillator selection.
• The Fail-Safe Clock Monitor (FSCM) does not
operate during Sleep mode.
• The BOR circuit, if enabled, remains operative
during Sleep mode.
• The WDT, if enabled, is not automatically cleared
prior to entering Sleep mode.
• Some peripherals can continue to operate in
Sleep mode. These peripherals include I/O pins
that detect a change in the input signal, WDT,
ADC, UART, and peripherals that use an external
clock input or the internal LPRC oscillator, e.g.,
RTCC and Timer 1.
• I/O pins continue to sink or source current in the
same manner as they do when the device is not in
Sleep.
• The USB module can override the disabling of the
POSC or FRC. Refer to the USB section for specific details.
• Some modules can be individually disabled by
software prior to entering Sleep in order to further
reduce consumption.
Preliminary
DS61143F-page 99
PIC32MX3XX/4XX
The processor will exit, or ‘wake-up’, from Sleep on one
of the following events:
• On any interrupt from an enabled source that is
operating in Sleep. The interrupt priority must be
greater than the current CPU priority.
• On any form of device Reset.
• On a WDT time-out. See Section 26.2 “Watchdog Timer (WDT)”.
If the interrupt priority is lower than or equal to current
priority, the CPU will remain halted, but the PBCLK will
start running and the device will enter into Idle mode.
Note:
25.4
There is no FRZ mode for this module.
Peripheral Bus Scaling Method
Most of the peripherals on the device are clocked using
the PBCLK. The peripheral bus can be scaled relative
to the SYSCLK to minimize the dynamic power consumed by the peripherals. The PBCLK divisor is controlled by PBDIV<1:0> (OSCCON<20:19>), allowing
SYSCLK-to-PBCLK ratios of 1:1, 1:2, 1:4, and 1:8. All
peripherals using PBCLK are affected when the divisor
is changed. Peripherals such as the Interrupt Controller, DMA, Bus Matrix, and Prefetch Cache are clocked
directly from SYSCLK, as a result, they are not affected
by PBCLK divisor changes.
25.5
In the Idle mode, the CPU is halted but the System
clock (SYSCLK) source is still enabled. This allows
peripherals to continue operation when the CPU is
halted. Peripherals can be individually configured to
halt when entering Idle by setting their respective SIDL
bit. Latency when exiting Idle mode is very low due to
the CPU oscillator source remaining active.
Notes: Changing the PBCLK divider ratio
requires recalculation of peripheral timing.
For example, assume the UART is configured for 9600 baud with a PB clock ratio of
1:1 and a POSC of 8 MHz. When the PB
clock divisor of 1:2 is used, the input frequency to the baud clock is cut in half;
therefore, the baud rate is reduced to 1/2
its former value. Due to numeric truncation
in calculations (such as the baud rate divisor), the actual baud rate may be a tiny
percentage different than expected. For
this reason, any timing calculation
required for a peripheral should be performed with the new PB clock frequency
instead of scaling the previous value
based on a change in PB divisor ratio.
Oscillator start-up and PLL lock delays
are applied when switching to a clock
source that was disabled and that uses a
crystal and/or the PLL. For example,
assume the clock source is switched from
POSC to LPRC just prior to entering
Sleep in order to save power. No oscillator start-up delay would be applied when
exiting Idle. However, when switching
back to POSC, the appropriate PLL and
or oscillator startup/lock delays would be
applied.
Most of the peripherals on the device are clocked using
the PBCLK. The peripheral bus can be scaled relative
to the SYSCLK to minimize the dynamic power consumed by the peripherals. The PBCLK divisor is controlled by PBDIV<1:0> (OSCCON<20:19>), allowing
SYSCLK-to-PBCLK ratios of 1:1, 1:2, 1:4, and 1:8. All
peripherals using PBCLK are affected when the divisor
is changed. Peripherals such as USB, Interrupt Controller, DMA, Bus Matrix, and Prefetch Cache are
clocked directly from SYSCLK, as a result, they are not
affected by PBCLK divisor changes
Changing the PBCLK divisor affects:
• The CPU to peripheral access latency. The CPU
has to wait for next PBCLK edge for a read to
complete. In 1:8 mode this results in a latency of
one to seven SYSCLKs.
• The power consumption of the peripherals. Power
consumption is directly proportional to the frequency at which the peripherals are clocked. The
greater the divisor, the lower the power consumed
by the peripherals.
To minimize dynamic power the PB divisor should be
chosen to run the peripherals at the lowest frequency
that provides acceptable system performance. When
selecting a PBCLK divider, peripheral clock requirements such as baud rate accuracy should be taken into
account. For example, the UART peripheral may not be
able to achieve all baud rate values at some PBCLK
divider depending on the SYSCLK value.
DS61143F-page 100
Idle Mode
The device enters Idle mode when the SLPEN
(OSCCON<4>) bit is clear and a WAIT instruction is
executed.
The processor will wake or exit from Idle mode on the
following events:
• On any interrupt event for which the interrupt
source is enabled. The priority of the interrupt
event must be greater than the current priority of
CPU. If the priority of the interrupt event is lower
than or equal to current priority of CPU, the CPU
will remain halted and the device will remain in
Idle mode.
• On any source of device Reset.
• On a WDT time-out interrupt. See Section 26.2
“Watchdog Timer (WDT)”.
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
26.0
SPECIAL FEATURES
Note:
26.1
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” (DS61132) for
detailed descriptions of these features.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
Configuration Bits
The Configuration bits can be programmed to select
various device configurations.
PIC32MX3XX/4XX devices include several features
intended to maximize application flexibility and reliability, and minimize cost through elimination of external
components. These are:
•
•
•
•
Flexible Device Configuration
Watchdog Timer
JTAG Interface
In-Circuit Serial Programming (ICSP)
REGISTER 26-1:
DEVCFG0: DEVICE CONFIGURATION WORD 0
r-0
r-1
r-1
R/P-1
r-1
r-1
r-1
R/P-1
—
—
—
CP
—
—
—
BWP
bit 31
bit 24
r-1
r-1
r-1
r-1
—
—
—
—
R/P-1
R/P-1
R/P-1
R/P-1
PWP<7:4>
bit 23
bit 16
R/P-1
R/P-1
R/P-1
R/P-1
PWP<3:0>
r-1
r-1
r-1
r-1
—
—
—
—
bit 15
bit 8
r-1
r-1
r-1
r-1
R/P-1
r-1
—
—
—
—
ICESEL
—
R/P-1
R/P-1
DEBUG<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
P = Programmable bit
r = Reserved bit
bit 31
Reserved: Write ‘0’
bit 30-29
Reserved: Write ‘1’
bit 28
CP: Code-Protect bit
Prevents boot and program Flash memory from being read or modified by an external
programming device.
1 = Protection disabled
0 = Protection enabled
bit 27-25
Reserved: Write ‘1’
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 101
PIC32MX3XX/4XX
REGISTER 26-1:
DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED)
bit 24
BWP: Boot Flash Write-Protect bit
Prevents boot Flash memory from being modified during code execution.
1 = Boot Flash is writable
0 = Boot Flash is not writable
bit 23-20
Reserved: Write ‘1’
bit 19-12
PWP<7:0>: Program Flash Write-Protect bits
Prevents selected program Flash memory pages from being modified during code execution.
The PWP bits represent the one’s compliment of the number of write protected program Flash memory
pages.
11111111 = Disabled
11111110 = 0xBD00_0FFF
11111101 = 0xBD00_1FFF
11111100 = 0xBD00_2FFF
11111011 = 0xBD00_3FFF
11111010 = 0xBD00_4FFF
11111001 = 0xBD00_5FFF
11111000 = 0xBD00_6FFF
11110111 = 0xBD00_7FFF
11110110 = 0xBD00_8FFF
11110101 = 0xBD00_9FFF
11110100 = 0xBD00_AFFF
11110011 = 0xBD00_BFFF
11110010 = 0xBD00_CFFF
11110001 = 0xBD00_DFFF
11110000 = 0xBD00_EFFF
11101111 = 0xBD00_FFFF
...
01111111 = 0xBD07_FFFF
bit 11-4
Reserved: Write ‘1’
bit 3
ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit
1 = PGEC2/PGED2 pair is used
0 = PGEC1/PGED1 pair is used
bit 2
Reserved: Write ‘1’
bit 1-0
DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled)
11 = Debugger disabled
10 = Debugger enabled
01 = Reserved (same as ‘11’ setting)
00 = Reserved (same as ‘11’ setting)
DS61143F-page 102
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
REGISTER 26-2:
DEVCFG1: DEVICE CONFIGURATION WORD 1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
bit 31
bit 24
R/P-1
r-1
r-1
FWDTEN
—
—
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
WDTPS<4:0>
bit 23
bit 16
R/P-1
R/P-1
R/P-1
FCKSM<1:0>
R/P-1
FPBDIV<1:0>
r-1
R/P-1
—
OSCIOFNC
R/P-1
R/P-1
POSCMD<1:0>
bit 15
bit 8
R/P-1
r-1
R/P-1
r-1
r-1
IESO
—
FSOSCEN
—
—
R/P-1
R/P-1
R/P-1
FNOSC<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
P = Programmable bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
bit 31-24
Reserved: Write ‘1’
bit 23
FWDTEN: Watchdog Timer Enable bit
1 = The WDT is enabled and cannot be disabled by software
0 = The WDT is not enabled; it can be enabled in software
bit 22-21
Reserved: Write ‘1’
bit 20-16
WDTPS<4:0>: Watchdog Timer Postscale Select bits
10100 = 1:1048576
10011 = 1:524288
10010 = 1:262144
10001 = 1:131072
10000 = 1:65536
01111 = 1:32768
01110 = 1:16384
01101 = 1:8192
01100 = 1:4096
01011 = 1:2048
01010 = 1:1024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
All other combinations not shown result in operation = ‘10100’
© 2009 Microchip Technology Inc.
Preliminary
r = Reserved bit
DS61143F-page 103
PIC32MX3XX/4XX
REGISTER 26-2:
DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED)
bit 15-14
FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
bit 13-12
FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits
11 = PBCLK is SYSCLK divided by 8
10 = PBCLK is SYSCLK divided by 4
01 = PBCLK is SYSCLK divided by 2
00 = PBCLK is SYSCLK divided by 1
bit 11
Reserved: Write ‘1’
bit 10
OSCIOFNC: CLKO Enable Configuration bit
1 = CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for
the External Clock mode (EC) for the CLKO to be active (POSCMD<1:0> = 11 OR 00)
0 = CLKO output disabled
bit 9-8
POSCMD<1:0>: Primary Oscillator Configuration bits
11 = Primary oscillator disabled
10 = HS oscillator mode selected
01 = XT oscillator mode selected
00 = External clock mode selected
bit 7
IESO: Internal External Switchover bit
1 = Internal External Switchover mode enabled (Two-Speed Start-up enabled)
0 = Internal External Switchover mode disabled (Two-Speed Start-up disabled)
bit 6
Reserved: Write ‘1’
bit 5
FSOSCEN: Secondary Oscillator Enable bit
1 = Enable Secondary Oscillator
0 = Disable Secondary Oscillator
bit 4-3
Reserved: Write ‘1’
bit 2-0
FNOSC<2:0>: Oscillator Selection bits
000 = Fast RC Oscillator (FRC)
001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL)
010 = Primary Oscillator (XT, HS, EC)(1)
011 = Primary Oscillator with PLL module (XT+PLL, HS+PLL, EC+PLL)
100 = Secondary Oscillator (SOSC)
101 = Low-Power RC Oscillator (LPRC)
110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler
111 = Fast RC Oscillator with divide-by-N (FRCDIV)
Note 1: Do not disable POSC (POSCMD = 00) when using this oscillator source.
DS61143F-page 104
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
REGISTER 26-3:
DEVCFG2: DEVICE CONFIGURATION WORD 2
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
bit 31
bit 24
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
R/P-1
R/P-1
R/P-1
FPLLODIV<2:0>
bit 23
bit 16
R/P-1
r-1
r-1
r-1
r-1
FUPLLEN
—
—
—
—
R/P-1
R/P-1
R/P-1
FUPLLIDIV<2:0>
bit 15
bit 8
r-1
R/P-1
—
R/P-1
R/P-1
r-1
FPLLMULT<2:0>
R/P-1
—
R/P-1
R/P-1
FPLLIDIV<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
P = Programmable bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
bit 31-19
Reserved: Write ‘1’
bit 18-16
FPLLODIV[2:0]: Default Postscaler for PLL bits
111 = PLL output divided by 256
110 = PLL output divided by 64
101 = PLL output divided by 32
100 = PLL output divided by 16
011 = PLL output divided by 8
010 = PLL output divided by 4
001 = PLL output divided by 2
000 = PLL output divided by 1
bit 15
FUPLLEN: USB PLL Enable bit
1 = Enable USB PLL
0 = Disable and bypass USB PLL
bit 14-11
Reserved: Write ‘1’
bit 10-8
FUPLLIDIV[2:0]: PLL Input Divider bits
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider
bit 7
Reserved: Write ‘1’
© 2009 Microchip Technology Inc.
Preliminary
r = Reserved bit
DS61143F-page 105
PIC32MX3XX/4XX
REGISTER 26-3:
DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED)
bit 6-4
FPLLMULT[2:0]: PLL Multiplier bits
111 = 24x multiplier
110 = 21x multiplier
101 = 20x multiplier
100 = 19x multiplier
011 = 18x multiplier
010 = 17x multiplier
001 = 16x multiplier
000 = 15x multiplier
bit 3
Reserved: Write ‘1’
bit 2-0
FPLLIDIV[2:0]: PLL Input Divider bits
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider
REGISTER 26-4:
DEVCFG3: DEVICE CONFIGURATION WORD 3
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
bit 31
bit 24
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
bit 23
bit 16
R/P-x
R/P-x
R/P-x
R/P-x
R/P-x
R/P-x
R/P-x
R/P-x
USERID<15:8>
bit 15
bit 8
R/P-x
R/P-x
R/P-x
R/P-x
R/P-x
R/P-x
R/P-x
R/P-x
USERID<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
P = Programmable bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
r = Reserved bit
bit 31-16
Reserved: Write ‘1’
bit 15-0
USERID<15:0>: This is a 16-bit value that is user defined and is readable via ICSP™ and JTAG
DS61143F-page 106
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
REGISTER 26-5:
R
DEVID: DEVICE AND REVISION ID REGISTER
R
R
R
R
VER<3:0>
R
R
R
DEVID<27:24>
bit 31
bit 24
R
R
R
R
R
R
R
R
DEVID<23:16>
bit 23
bit 16
R
R
R
R
R
R
R
R
DEVID<15:8>
bit 15
bit 8
R
R
R
R
R
R
R
R
DEVID<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
P = Programmable bit
bit 31-28
VER<3:0>: Revision Identifier bits(1)
bit 27-0
DEVID<27:0>: Device ID(1)
r = Reserved bit
Note: See the PIC32MX Programming Specification for a list of Revision and Device ID values.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 107
PIC32MX3XX/4XX
26.2
Watchdog Timer (WDT)
This section describes the operation of the WDT and
Power-Up Timer of the PIC32MX3XX/4XX.
The WDT, when enabled, operates from the internal
Low-Power Oscillator (LPRC) clock source and can be
used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in
software. Various WDT time-out periods can be
selected using the WDT postscaler. The WDT can also
be used to wake the device from Sleep or Idle mode.
FIGURE 26-1:
The following are some of the key features of the WDT
module:
• Configuration or software controlled
• User-configurable time-out period
• Can wake the device from Sleep or Idle
WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM
PWRT Enable
WDT Enable
LPRC
Control
PWRT Enable
1:64 Output
LPRC
Oscillator
PWRT
1
Clock
25-bit Counter
WDTCLR = 1
25
WDT Enable
Wake
0
1
WDT Counter Reset
Device Reset
NMI (Wake-up)
Power Save
Decoder
FWDTPS<4:0>(DEVCFG1<20:16>)
26.3
On-Chip Voltage Regulator
All PIC32MX3XX/4XX device’s core and digital logic
are designed to operate at a nominal 1.8V. To simplify
system
designs,
most
devices
in
the
PIC32MX3XX/4XX incorporate an on-chip regulator
providing the required core logic voltage from VDD.
The internal 1.8V regulator is controlled by the
ENVREG pin. Tying this pin to VDD enables the regulator, which in turn provides power to the core. A low
ESR capacitor (such as tantalum) must be connected
to the VDDCORE/VCAP pin (Figure 26-2). This helps to
maintain the stability of the regulator. The recommended value for the filer capacitor is provided in
Section 28.1 “DC Characteristics”.
Note:
It is important that the low ESR capacitor
is placed as close as possible to the
VDDCORE/VCAP pin.
DS61143F-page 108
Tying the ENVREG pin to VSS disables the regulator. In
this case, separate power for the core logic at a nominal 1.8V must be supplied to the device on the
VDDCORE/VCAP pin.
Alternately, the VDDCORE/VCAP and VDD pins can be
tied together to operate at a lower nominal voltage.
Refer to Figure 26-2 for possible configurations.
26.3.1
ON-CHIP REGULATOR AND POR
When the voltage regulator is enabled, it takes fixed
delay for it to generate output. During this time, designated as TPU, code execution is disabled. TPU is applied
every time the device resumes operation after any
power-down, including Sleep mode.
If the regulator is disabled, a separate Power-Up Timer
(PWRT) is automatically enabled. The PWRT adds a
fixed delay of TPWRT at device start-up. See
Section 28.0 “Electrical Characteristics” for more
information on TPU AND TPWRT.
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
26.3.2
ON-CHIP REGULATOR AND BOR
When
the
on-chip
regulator
is
enabled,
PIC32MX3XX/4XX devices also have a simple brownout capability. If the voltage supplied to the regulator is
inadequate to maintain a regulated level, the regulator
Reset circuitry will generate a Brown-out Reset. This
event is captured by the BOR flag bit (RCON<1>). The
brown-out voltage levels are specific in Section 28.1
“DC Characteristics”.
FIGURE 26-2:
26.3.3
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, VDDCORE must
never exceed VDD by 0.3 volts.
CONNECTIONS FOR THE ON-CHIP REGULATOR
Regulator Enabled (ENVREG tied to VDD):
Regulator Disabled (ENVREG tied to ground):
3.3V
1.8V(1)
PIC32MX
ENVREG
ENVREG
VDDCORE/VCAP
CEFC
(10 μF typ)
3.3V(1)
PIC32MX
VDD
VDD
Note 1:
POWER-UP REQUIREMENTS
VDDCORE/VCAP
VSS
VSS
These are typical operating voltages. Refer to Section 28.1 “DC Characteristics” for the full operating ranges of VDD
and VDDCORE.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 109
PIC32MX3XX/4XX
26.4
Programming and Diagnostics
PIC32MX3XX/4XX devices provide a complete range
of programming and diagnostic features that can
increase the flexibility of any application using them.
These features allow system designers to include:
• Simplified field programmability using two-wire InCircuit Serial Programming™ (ICSP™) interfaces
• Debugging using ICSP
• Programming and debugging capabilities using
the EJTAG extension of JTAG
• JTAG boundary scan testing for device and board
diagnostics
PIC32MX devices incorporate two programming and
diagnostic modules, and a trace controller, that provide
a range of functions to the application developer.
FIGURE 26-3:
BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING, AND TRACE PORTS
PGEC1
PGED1
ICSP™
Controller
PGEC2
PGED2
ICESEL
TDI
TDO
JTAG
Controller
TCK
Core
TMS
JTAGEN
DEBUG<1:0>
TRCLK
TRD0
TRD1
Instruction Trace
Controller
TRD2
TRD3
DEBUG<1:0>
DS61143F-page 110
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
REGISTER 26-6:
DDPCON: DEBUG DATA PORT CONTROL REGISTER
r-x
r-x
r-x
r-x
r-x
r-x
r-x
r-x
—
—
—
—
—
—
—
—
bit 31
bit 24
r-x
r-x
r-x
r-x
r-x
r-x
r-x
r-x
—
—
—
—
—
—
—
—
bit 23
bit 16
r-x
r-x
r-x
r-x
r-x
r-x
r-x
r-x
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
r-x
r-x
DDPUSB
DDPU1
DDPU2
DDPSPI1
JTAGEN
TROEN
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
P = Programmable bit
bit 31-8
Reserved: Write ‘0’; ignore read
bit 7
DDPUSB: Debug Data Port Enable for USB bit
1 = USB peripheral ignores USBFRZ (U1CNFG1<5>) setting
0 = USB peripheral follows USBFRZ setting.
bit 6
DDPU1: Debug Data Port Enable for UART1 bit
1 = UART1 peripheral ignores FRZ (U1MODE<14>) setting
0 = UART1 peripheral follows FRZ setting
bit 5
DDPU2: Debug Data Port Enable for UART2 bit
1 = UART2 peripheral ignores FRZ (U2MODE<14) setting
0 = UART2 peripheral follows FRZ setting
bit 4
DDPSPI1: Debug Data Port Enable for SPI1 bit
1 = SPI1 peripheral ignores FRZ (SPI1CON<14>) setting
0 = SPI1 peripheral follows FRZ setting
bit 3
JTAGEN: JTAG Port Enable bit
1 = Enable JTAG Port
0 = Disable JTAG Port
bit 2
TROEN: Trace Output Enable bit
1 = Enable Trace Port
0 = Disable Trace Port
bit 1-0
Reserved: Write ‘1’; ignore read
© 2009 Microchip Technology Inc.
Preliminary
r = Reserved bit
DS61143F-page 111
PIC32MX3XX/4XX
NOTES:
DS61143F-page 112
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
27.0
INSTRUCTION SET
Note:
The PIC32MX3XX/4XX family instruction set complies
with the MIPS32 Release 2 instruction set architecture.
PIC32MX does not support the following features:
Refer to “MIPS32® Architecture for Programmers Volume II: The MIPS32®
Instruction Set” at www.mips.com for more
information.
• CoreExtend instructions
• Coprocessor 1 instructions
• Coprocessor 2 instructions
Table 27-1 provides a summary of the instructions that
are implemented by the PIC32MX3XX/4XX family
core.
TABLE 27-1:
MIPS32® INSTRUCTION SET
Instruction
Description
Function
ADD
Integer Add
Rd = Rs + Rt
ADDI
Integer Add Immediate
Rt = Rs + Immed
ADDIU
Unsigned Integer Add Immediate
ADDU
Unsigned Integer Add
Rt = Rs +U Immed
Rd = Rs +U Rt
AND
Logical AND
Rd = Rs & Rt
ANDI
Logical AND Immediate
B
Unconditional Branch
(Assembler idiom for: BEQ r0, r0, offset)
Rt = Rs & (016 || Immed)
PC += (int)offset
BAL
Branch and Link
(Assembler idiom for: BGEZAL r0, offset)
GPR[31] = PC + 8
PC += (int)offset
BEQ
Branch On Equal
if Rs == Rt
PC += (int)offset
BEQL
Branch On Equal Likely(1)
if Rs == Rt
PC += (int)offset
else
Ignore Next Instruction
BGEZ
Branch on Greater Than or Equal To Zero
if !Rs[31]
PC += (int)offset
BGEZAL
Branch on Greater Than or Equal To Zero And Link
GPR[31] = PC + 8
if !Rs[31]
PC += (int)offset
BGEZALL
Branch on Greater Than or Equal To Zero And Link
Likely(1)
GPR[31] = PC + 8
if !Rs[31]
PC += (int)offset
else
Ignore Next Instruction
BGEZL
Branch on Greater Than or Equal To Zero Likely(1)
if !Rs[31]
PC += (int)offset
else
Ignore Next Instruction
BGTZ
Branch on Greater Than Zero
if !Rs[31] && Rs != 0
PC += (int)offset
BGTZL
Branch on Greater Than Zero Likely(1)
if !Rs[31] && Rs != 0
PC += (int)offset
else
Ignore Next Instruction
BLEZ
Branch on Less Than or Equal to Zero
if Rs[31] || Rs == 0
PC += (int)offset
Note 1:
This instruction is deprecated and should not be used.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 113
PIC32MX3XX/4XX
TABLE 27-1:
MIPS32® INSTRUCTION SET (CONTINUED)
Instruction
Description
Function
(1)
BLEZL
Branch on Less Than or Equal to Zero Likely
BLTZ
Branch on Less Than Zero
if Rs[31]
PC += (int)offset
BLTZAL
Branch on Less Than Zero And Link
GPR[31] = PC + 8
if Rs[31]
PC += (int)offset
BLTZALL
Branch on Less Than Zero And Link Likely(1)
GPR[31] = PC + 8
if Rs[31]
PC += (int)offset
else
Ignore Next Instruction
BLTZL
Branch on Less Than Zero Likely(1)
if Rs[31]
PC += (int)offset
else
Ignore Next Instruction
BNE
Branch on Not Equal
if Rs != Rt
PC += (int)offset
BNEL
Branch on Not Equal Likely(1)
if Rs != Rt
PC += (int)offset
else
Ignore Next Instruction
BREAK
Breakpoint
Break Exception
CLO
Count Leading Ones
Rd = NumLeadingOnes(Rs)
CLZ
Count Leading Zeroes
Rd = NumLeadingZeroes(Rs)
DERET
Return from Debug Exception
PC = DEPC
Exit Debug Mode
Rt = Status; StatusIE = 0
LO = (int)Rs / (int)Rt
HI = (int)Rs % (int)Rt
if Rs[31] || Rs == 0
PC += (int)offset
else
Ignore Next Instruction
DI
Atomically Disable Interrupts
DIV
Divide
DIVU
Unsigned Divide
LO = (uns)Rs / (uns)Rt
HI = (uns)Rs % (uns)Rt
EHB
Execution Hazard Barrier
Stop instruction execution
until execution hazards are
cleared
Rt = Status; StatusIE = 1
if StatusERL
PC = ErrorEPC
else
PC = EPC
StatusEXL = 0
StatusERL = 0
LL = 0
EI
Atomically Enable Interrupts
ERET
Return from Exception
EXT
Extract Bit Field
Rt = ExtractField(Rs, pos,
size)
INS
Insert Bit Field
Rt = InsertField(Rs, Rt, pos,
size)
J
Unconditional Jump
PC = PC[31:28] || offset<<2
Note 1:
This instruction is deprecated and should not be used.
DS61143F-page 114
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 27-1:
MIPS32® INSTRUCTION SET (CONTINUED)
Instruction
Description
Function
JAL
Jump and Link
GPR[31] = PC + 8
PC = PC[31:28] || offset<<2
JALR
Jump and Link Register
Rd = PC + 8
PC = Rs
JALR.HB
Jump and Link Register with Hazard Barrier
Like JALR, but also clears execution and
instruction hazards
JR
Jump Register
PC = Rs
JR.HB
Jump Register with Hazard Barrier
Like JR, but also clears execution and
instruction hazards
LB
Load Byte
Rt = (byte)Mem[Rs+offset]
LBU
Unsigned Load Byte
Rt = (ubyte))Mem[Rs+offset]
LH
Load Halfword
Rt = (half)Mem[Rs+offset]
LHU
Unsigned Load Halfword
Rt = (uhalf)Mem[Rs+offset]
LL
Load Linked Word
Rt = Mem[Rs+offset>
LLbit = 1
LLAdr = Rs + offset
LUI
Load Upper Immediate
Rt = immediate << 16
LW
Load Word
Rt = Mem[Rs+offset]
LWPC
Load Word, PC relative
Rt = Mem[PC+offset]
LWL
Load Word Left
Re = Re MERGE Mem[Rs+offset]
LWR
Load Word Right
Re = Re MERGE Mem[Rs+offset]
MADD
Multiply-Add
HI | LO += (int)Rs * (int)Rt
MADDU
Multiply-Add Unsigned
HI | LO += (uns)Rs * (uns)Rt
MFC0
Move From Coprocessor 0
Rt = CPR[0, Rd, sel]
MFHI
Move From HI
Rd = HI
MFLO
Move From LO
Rd = LO
MOVN
Move Conditional on Not Zero
if Rt ¼ 0 then
Rd = Rs
MOVZ
Move Conditional on Zero
if Rt = 0 then
Rd = Rs
MSUB
Multiply-Subtract
HI | LO -= (int)Rs * (int)Rt
MSUBU
Multiply-Subtract Unsigned
HI | LO -= (uns)Rs * (uns)Rt
MTC0
Move To Coprocessor 0
CPR[0, n, Sel] = Rt
MTHI
Move To HI
HI = Rs
MTLO
Move To LO
LO = Rs
MUL
Multiply with register write
HI | LO =Unpredictable
Rd = ((int)Rs * (int)Rt)31..0
MULT
Integer Multiply
HI | LO = (int)Rs * (int)Rd
MULTU
Unsigned Multiply
HI | LO = (uns)Rs * (uns)Rd
NOP
No Operation
(Assembler idiom for: SLL r0, r0, r0)
NOR
Logical NOR
Rd = ~(Rs | Rt)
OR
Logical OR
Rd = Rs | Rt
ORI
Logical OR Immediate
Rt = Rs | Immed
RDHWR
Read Hardware Register (if enabled by HWREna
Register)
Re = HWR[Rd]
Note 1:
This instruction is deprecated and should not be used.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 115
PIC32MX3XX/4XX
TABLE 27-1:
MIPS32® INSTRUCTION SET (CONTINUED)
Instruction
Description
Function
RDPGPR
Read GPR from Previous Shadow Set
Rt = SGPR[SRSCtlPSS, Rd]
ROTR
Rotate Word Right
ROTRV
Rotate Word Right Variable
SB
Store Byte
Rd = Rtsa-1..0 || Rt31..sa
Rd = RtRs-1..0 || Rt31..Rs
(byte)Mem[Rs+offset] = Rt
SC
Store Conditional Word
if LLbit = 1
mem[Rs+offset> = Rt
Rt = LLbit
SDBBP
Software Debug Break Point
Trap to SW Debug Handler
SEB
Sign-Extend Byte
Rd = SignExtend (Rs-7...0)
SEH
Sign-Extend Half
Rd = SignExtend (Rs-15...0)
SH
Store Half
(half)Mem[Rs+offset> = Rt
SLL
Shift Left Logical
Rd = Rt << sa
SLLV
Shift Left Logical Variable
Rd = Rt << Rs[4:0]
SLT
Set on Less Than
if (int)Rs < (int)Rt
Rd = 1
else
Rd = 0
SLTI
Set on Less Than Immediate
if (int)Rs < (int)Immed
Rt = 1
else
Rt = 0
SLTIU
Set on Less Than Immediate Unsigned
if (uns)Rs < (uns)Immed
Rt = 1
else
Rt = 0
SLTU
Set on Less Than Unsigned
if (uns)Rs < (uns)Immed
Rd = 1
else
Rd = 0
SRA
Shift Right Arithmetic
Rd = (int)Rt >> sa
SRAV
Shift Right Arithmetic Variable
Rd = (int)Rt >> Rs[4:0]
SRL
Shift Right Logical
Rd = (uns)Rt >> sa
SRLV
Shift Right Logical Variable
Rd = (uns)Rt >> Rs[4:0]
SSNOP
Superscalar Inhibit No Operation
NOP
SUB
Integer Subtract
Rt = (int)Rs - (int)Rd
SUBU
Unsigned Subtract
Rt = (uns)Rs - (uns)Rd
SW
Store Word
Mem[Rs+offset] = Rt
SWL
Store Word Left
Mem[Rs+offset] = Rt
SWR
Store Word Right
Mem[Rs+offset] = Rt
SYNC
Synchronize
Orders the cached coherent and
uncached loads and stores for access to
the shared memory
SYSCALL
System Call
SystemCallException
TEQ
Trap if Equal
if Rs == Rt
TrapException
TEQI
Trap if Equal Immediate
if Rs == (int)Immed
TrapException
Note 1:
This instruction is deprecated and should not be used.
DS61143F-page 116
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 27-1:
MIPS32® INSTRUCTION SET (CONTINUED)
Instruction
Description
Function
TGE
Trap if Greater Than or Equal
if (int)Rs >= (int)Rt
TrapException
TGEI
Trap if Greater Than or Equal Immediate
if (int)Rs >= (int)Immed
TrapException
TGEIU
Trap if Greater Than or Equal Immediate Unsigned
if (uns)Rs >= (uns)Immed
TrapException
TGEU
Trap if Greater Than or Equal Unsigned
if (uns)Rs >= (uns)Rt
TrapException
TLT
Trap if Less Than
if (int)Rs < (int)Rt
TrapException
TLTI
Trap if Less Than Immediate
if (int)Rs < (int)Immed
TrapException
TLTIU
Trap if Less Than Immediate Unsigned
if (uns)Rs < (uns)Immed
TrapException
TLTU
Trap if Less Than Unsigned
if (uns)Rs < (uns)Rt
TrapException
TNE
Trap if Not Equal
if Rs != Rt
TrapException
TNEI
Trap if Not Equal Immediate
if Rs != (int)Immed
TrapException
WAIT
Wait for Interrupt
Go to a low power mode and stall until
interrupt occurs
WRPGPR
Write to GPR in Previous Shadow Set
SGPR[SRSCtlPSS, Rd> = Rt
WSBH
Word Swap Bytes Within Halfwords
XOR
Exclusive OR
Rd = Rt23..16 || Rt31..24 || Rt7..0
|| Rt15..8
Rd = Rs ^ Rt
Exclusive OR Immediate
Rt = Rs ^ (uns)Immed
XORI
Note 1:
This instruction is deprecated and should not be used.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 117
PIC32MX3XX/4XX
NOTES:
DS61143F-page 118
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
28.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of PIC32MX3XX/4XX electrical characteristics. Additional information will be provided
in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC32MX3XX/4XX are listed below. Exposure to these maximum rating conditions
for extended periods may affect device reliability. Functional operation of the device at these or any other conditions
above the parameters indicated in the operation listings of this specification is not implied.
Absolute Maximum Ratings (Note 1)
Ambient temperature under bias.............................................................................................................. .-40°C to +85°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V)
Voltage on any digital only pin with respect to VSS .................................................................................. -0.3V to +5.5V
Voltage on VDDCORE with respect to VSS ................................................................................................... -0.3V to 2.0V
Maximum current out of VSS pin(s) .......................................................................................................................300 mA
Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (Note 2) ....................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 28-2).
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 119
PIC32MX3XX/4XX
28.1
DC Characteristics
TABLE 28-1:
OPERATING MIPS VS. VOLTAGE
Characteristic
DC5
Note 1:
Max. Frequency
VDD Range
(in Volts)
Temp. Range
(in °C)
PIC32MX3XX/4XX
2.3-3.6V
-40°C to +85°C
80 MHz (Note 1)
40 MHz maximum for PIC32MX 40MHz family variants.
TABLE 28-2:
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min.
Typical
Max.
Unit
Operating Junction Temperature Range
TJ
-40
—
+125
°C
Operating Ambient Temperature Range
TA
-40
—
+85
°C
PIC32MX3XX/4XX
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – S IOH)
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/θJA
W
I/O Pin Power Dissipation:
I/O = S ({VDD – VOH} x IOH) + S (VOL x IOL))
Maximum Allowed Power Dissipation
TABLE 28-3:
THERMAL PACKAGING CHARACTERISTICS
Characteristics
Symbol Typical
θJA
θJA
θJA
Package Thermal Resistance, 100-Pin TQFP (12x12x1 mm)
Package Thermal Resistance, 64-Pin TQFP (10x10x1 mm)
Package Thermal Resistance, 64-Pin QFN (9x9x0,9 mm)
Note 1:
Max.
Unit
Notes
43
—
°C/W
1
47
—
°C/W
1
28
—
°C/W
1
Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.
TABLE 28-4:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.
Typical
Max.
Units
Conditions
Operating Voltage
DC10
Supply Voltage
2.3
—
3.6
V
DC12
VDR
RAM Data Retention Voltage
(Note 1)
1.75
—
—
V
DC16
VPOR
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
1.75
—
1.95
V
DC17
SVDD
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
0.05
—
—
V/ms
VDD
Note 1:
This is the limit to which VDD can be lowered without losing RAM data.
DS61143F-page 120
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 28-5:
DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
DC CHARACTERISTICS
Parameter
No.
Typical(3)
Max.
Units
Conditions
Operating Current (IDD)
DC20
8.5
13
mA
DC20c
4.0
—
mA
DC21
23.5
32
mA
DC21c
16.4
—
mA
DC22
48
61
mA
DC22c
45
—
mA
DC23
55
75
mA
DC23c
55
—
mA
—
Code executing from SRAM
—
Code executing from SRAM
—
Code executing from SRAM
—
—
—
2.3V
Code executing from SRAM
DC24
—
100
µA
-40°C
DC24a
—
130
µA
+25°C
DC24b
—
670
µA
+85°C
DC25
94
—
µA
-40°C
DC25a
125
—
µA
+25°C
DC25b
302
—
µA
+85°C
DC25c
71
—
µA
Code executing from SRAM
DC26
—
110
µA
-40°C
DC26a
—
180
µA
+25°C
DC26b
—
700
µA
+85°C
Note 1:
2:
3:
4:
—
4 MHz
20 MHz
(Note 4)
60 MHz
(Note 4)
80 MHz
2.3V
3.3V
LPRC (31 kHz)
(Note 4)
3.6V
A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors,
such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,
oscillator type as well as temperature can have an impact on the current consumption.
The test conditions for IDD measurements are as follows: Oscillator mode = EC+PLL with OSC1 driven by
external square wave from rail to rail and PBCLK divisor = 1:8. CPU, Program Flash and SRAM data
memory are operational, Program Flash memory Wait states = 7, program cache and prefetch are disabled and SRAM data memory Wait states = 1. All peripheral modules are disabled (ON bit = 0). WDT and
FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD.
Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.
Parameters are for design guidance only and are not tested.
This parameter is characterized, but not tested in manufacturing.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 121
PIC32MX3XX/4XX
TABLE 28-6:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
DC CHARACTERISTICS
Parameter
No.
Typical(2)
Max.
Units
Conditions
Idle Current (IIDLE): Core OFF, Clock ON Base Current (Note 1)
DC30
—
5
mA
2.3V
DC30a
1.4
—
mA
—
DC30b
—
5
mA
3.6V
DC31
—
15
mA
2.3V
DC31a
13
—
mA
—
DC31b
—
17
mA
3.6V
DC32
—
22
mA
2.3V
DC32a
20
—
mA
—
DC32b
—
25
mA
3.6V
DC33
—
29
mA
2.3V
DC33a
24
—
mA
—
DC33b
—
32
mA
3.6V
DC34
—
36
µA
-40°C
DC34a
—
62
µA
+25°C
DC34b
—
392
µA
+85°C
DC35
35
—
µA
-40°C
DC35a
65
—
µA
+25°C
DC35b
242
—
µA
+85°C
DC36
—
43
µA
-40°C
DC36a
—
106
µA
+25°C
—
414
µA
+85°C
DC36b
Note 1:
2:
3:
4 MHz
20 MHz,
(Note 3)
60 MHz
(Note 3)
80 MHz
2.3V
3.3V
LPRC (31 kHz)
(Note 3)
3.6V
The test conditions for base IDLE current measurements are as follows: System clock is enabled and
PBCLK divisor = 1:8. CPU in Idle mode (CPU core halted). Only digital peripheral modules are enabled
(ON bit = 1) and being clocked. WDT and FSCM are disabled. All I/O pins are configured as inputs and
pulled to VSS. MCLR = VDD.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
This parameter is characterized, but not tested in manufacturing.
DS61143F-page 122
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 28-7:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
DC CHARACTERISTICS
Parameter
No.
Typical(2)
Max.
Units
Conditions
Power-Down Current (IPD) (Note 1)
DC40
7
30
μA
-40°C
DC40a
24
30
μA
+25°C
DC40b
205
300
μA
+85°C
DC40c
25
—
μA
+25°C
DC40d
9
70
μA
-40°C
DC40e
25
70
μA
+25°C
DC40g
115
200
(Note 5)
μA
+70°C
DC40f
200
400
μA
+85°C
2.3V
Base Power-Down Current (Note 6)
3.3V
Base Power-Down Current
3.6V
Base Power-Down Current
2.3V
Watchdog Timer Current: ΔIWDT (Notes 3, 6)
3.3V
Watchdog Timer Current: ΔIWDT (Note 3)
3.6V
Watchdog Timer Current: ΔIWDT (Note 3)
2.3V
RTCC + Timer1 w/32kHz Crystal: ΔIRTCC
(Notes 3, 6)
Module Differential Current
DC41
—
10
μA
-40°C
DC41a
—
10
μA
+25°C
DC41b
—
10
μA
+85°C
DC41c
5
—
μA
+25°C
DC41d
—
10
μA
-40°C
DC41e
—
10
μA
+25°C
DC41f
—
12
μA
+85°C
DC42
—
10
μA
-40°C
DC42a
—
17
μA
+25°C
DC42b
—
37
μA
+85°C
DC42c
23
—
μA
+25°C
DC42e
—
10
μA
-40°C
DC42f
—
30
μA
+25°C
DC42g
—
44
μA
+85°C
DC42
—
1100
μA
-40°C
DC42a
—
1100
μA
+25°C
DC42b
—
1000
μA
+85°C
DC42c
880
—
μA
DC42e
—
1100
μA
-40°C
DC42f
—
1100
μA
+25°C
DC42g
—
1000
μA
+85°C
Note 1:
2:
3:
4:
5:
6:
3.3V
RTCC + Timer1 w/32kHz Crystal: ΔIRTCC
(Note 3)
3.6V
RTCC + Timer1 w/32kHz Crystal: ΔIRTCC
(Note 3)
2.5V
ADC: ΔIADC (Notes 3, 4, 6)
ADC: ΔIADC (Notes 3, 4)
3.6V
ADC: ΔIADC (Notes 3, 4)
Base IPD is measured with all digital peripheral modules enabled (ON bit = 1) and being clocked, CPU clock
is disabled. All I/Os are configured as outputs and pulled low. WDT and FSCM are disabled.
Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The Δ current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.
Data is characterized at +70°C and not tested. Parameter is for design guidance only.
This parameter is characterized, but not tested in manufacturing.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 123
PIC32MX3XX/4XX
TABLE 28-8:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Param.
Symbol
No.
VIL
DI10
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise
stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for Industrial
Min.
Typical(1)
Max.
Units
with TTL Buffer
VSS
—
0.15 VDD
V
(Note 4)
with Schmitt Trigger Buffer
VSS
—
0.2 VDD
V
(Note 4)
Characteristics
Conditions
Input Low Voltage
I/O pins:
DI15
MCLR
VSS
—
0.2 VDD
V
(Note 4)
DI16
OSC1 (XT mode)
VSS
—
0.2 VDD
V
(Note 4)
DI17
OSC1 (HS mode)
VSS
—
0.2 VDD
V
(Note 4)
DI18
SDAx, SCLx
VSS
—
0.3 VDD
V
SMBus disabled
(Note 4)
DI19
SDAx, SCLx
VSS
—
0.8
V
SMBus enabled
(Note 4)
0.8 VDD
—
VDD
V
(Note 4)
VIH
DI20
Input High Voltage
I/O pins:
with Analog Functions
Digital Only
0.8 VDD
—
V
(Note 4)
0.25VDD + 0.8V
—
5.5
V
(Note 4)
with Schmitt Trigger Buffer
0.8 VDD
—
5.5
V
(Note 4)
MCLR
0.8 VDD
—
VDD
V
(Note 4)
with TTL Buffer
DI25
DI26
OSC1 (XT mode)
0.7 VDD
—
VDD
V
(Note 4)
DI27
OSC1 (HS mode)
0.7 VDD
—
VDD
V
(Note 4)
DI28
SDAx, SCLx
0.7 VDD
—
5.5
V
SMBus disabled
(Note 4)
DI29
SDAx, SCLx
2.1
—
5.5
V
SMBus enabled,
2.3V ≤ VPIN ≤ 5.5
(Note 4)
ICNPU
CNxx Pull up Current
50
250
400
μA
VDD = 3.3V, VPIN = VSS
IIL
Input Leakage Current
(Note 3)
DI30
DI50
I/O Ports
—
—
+1
μA
VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
DI51
Analog Input Pins
—
—
+1
μA
VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
DI55
MCLR
—
—
+1
μA
VSS ≤ VPIN ≤ VDD
DI56
OSC1
—
—
+1
μA
VSS ≤ VPIN ≤ VDD,
XT and HS modes
Note 1:
2:
3:
4:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
This parameter is characterized, but not tested in manufacturing.
DS61143F-page 124
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 28-9:
DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICS
Param.
Symbol
No.
VOL
DO10
Characteristics
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise
stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for Industrial
Min.
Units
Conditions
—
—
0.4
V
IOL = 7 mA, VDD = 3.6V
—
—
0.4
V
IOL = 6 mA, VDD = 2.3V
—
—
0.4
V
IOL = 3.5 mA, VDD = 3.6V
—
—
0.4
V
IOL = 2.5 mA, VDD = 2.3V
2.4
—
—
V
IOH = -12 mA, VDD = 3.6V
1.4
—
—
V
IOH = -12 mA, VDD = 2.3V
2.4
—
—
V
IOH = -12 mA, VDD = 3.6V
1.4
—
—
V
IOH = -12 mA, VDD = 2.3V
OSC2/CLKO
VOH
Max.
Output Low Voltage
I/O Ports
DO16
Typical
Output High Voltage
DO20
I/O Ports
DO26
OSC2/CLKO
TABLE 28-10: DC CHARACTERISTICS: PROGRAM MEMORY(3)
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Programming temperature 0°C ≤ TA ≤ +70°C (25°C recommended)
Min.
Typical(1)
Max.
Units
Conditions
Program Flash Memory
D130
EP
Cell Endurance
1000
—
—
E/W
D131
VPR
VDD for Read
VMIN
—
3.6
V
VMIN = Minimum operating
voltage
D132
VPEW
VDD for Erase or Write
3.0
—
3.6
V
0°C to +40°C
D134
TRETD
Characteristic Retention
20
—
—
Year Provided no other specifications
are violated
D135
IDDP
Supply Current during
Programming
—
10
—
mA
0°C to +40°C
TWW
Word Write Cycle Time
20
—
40
μs
0°C to +40°C
D136
TRW
Row Write Cycle Time
(Note 2)
(128 words per row)
3
4.5
—
ms
0°C to +40°C
D137
TPE
Page Erase Cycle Time
20
—
—
ms
0°C to +40°C
TCE
Chip Erase Cycle Time
80
—
—
ms
0°C to +40°C
Note 1:
2:
3:
-40°C to +85°C
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities
during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus
loads are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The
default Arbitration mode is mode 1 (CPU has lowest priority).
Refer to PIC32MX Flash Programming Specification (DS61145) for operating conditions during
programming and erase cycles.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 125
PIC32MX3XX/4XX
TABLE 28-11: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Required Flash wait states
SYSCLK
Units
0 Wait State
0 to 30
MHz
1 Wait State
31 to 60
2 Wait States
61 to 80
Note 1:
Comments
40 MHz maximum for PIC32MX 40MHz family variants.
TABLE 28-12: COMPARATOR SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for Industrial
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.
Typical
Max.
Units
Comments
D300
VIOFF
Input Offset Voltage
—
±7.5
±25
mV
AVDD = VDD,
AVSS = VSS
D301
VICM
Input Common Mode Voltage
0
—
VDD
V
AVDD = VDD,
AVSS = VSS
(Note 2)
D302
CMRR
Common Mode Rejection Ratio
55
—
—
dB
Max VICM = (VDD - 1)V
(Note 2)
D303
TRESP
Response Time
—
150
400
nsec
AVDD = VDD,
AVSS = VSS
(Notes 1, 2)
D304
ON2OV
Comparator Enabled to Output
Valid
—
—
10
μs
Comparator module is
configured before setting
the comparator ON bit.
(Note 2)
Note 1:
2:
Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
These parameters are characterized but not tested.
TABLE 28-13: VOLTAGE REFERENCE SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for Industrial
DC CHARACTERISTICS
Param.
No.
D310
Symbol
Characteristics
Min.
Typical
Max.
Units
VDD/24
—
VDD/32
LSb
VRES
Resolution
D311
VRAA
Absolute Accuracy
—
—
1/2
LSb
D312
TSET
Settling Time(1)
—
—
10
μs
Note 1:
Comments
Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from ‘0000’ to ‘1111’. This
parameter is characterized, but not tested in manufacturing.
DS61143F-page 126
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 28-14: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for Industrial
DC CHARACTERISTICS
Param.
No.
Symbol
Characteristics
D320
VDDCORE Regulator Output Voltage
D321
CEFC
D322
TPWRT
External Filter Capacitor Value
© 2009 Microchip Technology Inc.
Min.
Typical
Max.
Units
1.62
1.80
1.98
V
4.7
10
—
μF
Capacitor must be low series
resistance (< 3 ohms)
—
64
—
ms
ENVREG = 0
Preliminary
Comments
DS61143F-page 127
PIC32MX3XX/4XX
28.2
AC Characteristics and Timing
Parameters
The information contained in this section defines
PIC32MX3XX/4XX AC characteristics and timing
parameters.
TABLE 28-15: AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Operating voltage VDD range.
AC CHARACTERISTICS
FIGURE 28-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2
VDD/2
RL
CL
Pin
VSS
CL
Pin
RL = 464Ω
CL = 50 pF for all pins
50 pF for OSC2 pin (EC mode)
VSS
TABLE 28-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param.
Symbol
No.
Min.
Typical(1)
Characteristics
Max.
Units
Conditions
DO56
CIO
All I/O pins and OSC2
—
—
50
pF
EC mode
DO58
CB
SCLx, SDAx
—
—
400
pF
In I2C™ mode
Note 1:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
FIGURE 28-2:
EXTERNAL CLOCK TIMING
OS20
OS30
OS31
OSC1
OS30
DS61143F-page 128
Preliminary
OS31
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 28-17: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Min.
Typical(1)
Max.
Units
Conditions
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
4
—
—
50 (Note 3)
50 (Note 5)
MHz
MHz
EC (Note 5)
ECPLL (Note 4)
Oscillator Crystal Frequency
3
—
10
MHz
XT (Note 5)
OS12
4
—
10
MHz
XTPLL
(Notes 4, 5)
OS13
10
—
25
MHz
HS (Note 5)
OS14
10
—
25
MHz
HSPLL
(Notes 4, 5)
OS15
32
32.768
100
kHz
SOSC (Note 5)
—
—
—
—
See parameter
OS10 for FOSC
value
OS10
FOSC
OS11
Characteristics
OS20
TOSC
TOSC = 1/FOSC = TCY (Note 2)
OS30
TOSL,
TOSH
External Clock In (OSC1)
High or Low Time
0.45 x TOSC
—
—
nsec
EC (Note 5)
OS31
TOSR,
TOSF
External Clock In (OSC1)
Rise or Fall Time
—
—
0.05 x TOSC
nsec
EC (Note 5)
OS40
TOST
Oscillator Start-up Timer Period
(Only applies to HS, HSPLL,
XT, XTPLL and SOSC Clock
Oscillator modes)
—
1024
—
TOSC
(Note 5)
OS41
TFSCM
Primary Clock Fail Safe
Time-out Period
—
2
—
ms
(Note 5)
OS42
GM
External Oscillator
Transconductance
—
12
—
Note 1:
2:
3:
4:
5:
mA/V VDD = 3.3V
TA = +25°C
(Note 5)
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are characterized but are
not tested.
Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device
executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin.
40 MHz maximum for PIC32MX 40 MHz family variants.
PLL input requirements: 4 MHZ ≤ FPLLIN ≤ 5 MHZ (use PLL prescaler to reduce FOSC). This parameter is
characterized, but tested at 10 MHz only at manufacturing.
This parameter is characterized, but not tested in manufacturing.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 129
PIC32MX3XX/4XX
TABLE 28-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical(2)
Max.
Units
OS50
FPLLI
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
4
—
5
MHz
OS51
FSYS
On-Chip VCO System
Frequency
60
—
120
MHz
OS52
TLOCK
PLL Start-up Time (Lock Time)
—
—
2
ms
OS53
DCLK
CLKO Stability
(Period Jitter or Cumulative)
-0.25
—
+0.25
%
Note 1:
2:
Conditions
ECPLL, HSPLL, XTPLL,
FRCPLL modes
Measured over 100 ms
period
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
TABLE 28-19:
INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Param.
No.
Characteristics
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Min.
Typical
Max.
Units
+2
%
Conditions
Internal FRC Accuracy @ 8.00 MHz (Note 1)
F20
Note 1:
FRC
-2
—
Frequency calibrated at 25°C and 3.3V. TUN bits can be used to compensate for temperature drift.
TABLE 28-20: INTERNAL RC ACCURACY
AC CHARACTERISTICS
Param.
No.
Characteristics
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Min.
Typical
Max.
Units
-15
—
+15
%
Conditions
LPRC @ 31.25 kHz (Note 1)
F21
Note 1:
Change of LPRC frequency as VDD changes.
DS61143F-page 130
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 28-3:
I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
DO31
DO32
Note: Refer to Figure 28-1 for load conditions.
TABLE 28-21: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
DO31
TIOR
DO32
TIOF
DI35
DI40
Note 1:
2:
Characteristics(2)
Min.
Typical(1)
Max.
Units
Port Output Rise Time
—
5
10
nsec
Port Output Fall Time
—
5
10
nsec
TINP
INTx Pin High or Low Time
10
—
—
nsec
TRBP
CNx High or Low Time (input)
2
—
—
TSYSCLK
Conditions
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
This parameter is characterized, but not tested in manufacturing.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 131
PIC32MX3XX/4XX
FIGURE 28-4:
POWER-ON RESET TIMING CHARACTERISTICS
Internal Voltage Regulator Enabled
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDD
VPOR
(TSYSDLY)
SY02
Power Up Sequence
(Note 2)
CPU starts fetching code
SY00
(TPU)
(Note 1)
Internal Voltage Regulator Enabled
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
VDD
VPOR
(TSYSDLY)
SY02
Power Up Sequence
(Note 2)
SY00
(TPU)
(Note 1)
CPU starts fetching code
SY10
(TOST)
External VDDCORE Provided
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDD
VDDCORE
VPOR
(TSYSDLY)
SY02
Power Up Sequence
(Note 3)
SY01
(TPWRT)
(Note 1)
CPU starts fetching code
Note 1: The Power-up period will be extended if the Power-up sequence completes before the device
exits from BOR (VDD < VDDMIN).
2: Includes interval voltage regulator stabilization delay.
3: Power-Up Timer (PWRT); only active when the internal voltage regulator is disabled
DS61143F-page 132
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 28-5:
EXTERNAL RESET TIMING CHARACTERISTICS
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
MCLR
TMCLR
(SY20)
BOR
TBOR
(SY30)
(TSYSDLY)
SY02
Reset Sequence
CPU starts fetching code
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
(TSYSDLY)
SY02
Reset Sequence
CPU starts fetching code
TOST
(SY10)
TABLE 28-22: RESETS TIMING
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical(2)
Max.
Units
Conditions
SY00
TPU
Power-up Period
Internal Voltage Regulator Enabled
—
400
600
μs
-40°C to +85°C
SY01
TPWRT
Power-up Period
External VDDCORE Applied
(Power-Up-Timer Active)
48
64
80
ms
-40°C to +85°C
SY02
TSYSDLY System Delay Period:
Time required to reload Device
Configuration Fuses plus SYSCLK
delay before first instruction is
fetched.
—
1 μs
+
—
—
-40°C to +85°C
MCLR Pulse Width (low)
—
2
—
μs
-40°C to +85°C
BOR Pulse Width (low)
—
1
—
μs
-40°C to +85°C
SY20
SY30
Note 1:
2:
TMCLR
TBOR
8 SYSCLK
cycles
These parameters are characterized, but not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 133
PIC32MX3XX/4XX
FIGURE 28-6:
TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
OS60
Tx20
TMRx
Note: Refer to Figure 28-1 for load conditions.
TABLE 28-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
TA10
TA11
TA15
TTXH
TTXL
TTXP
Characteristics(2)
TxCK
High Time
TxCK
Low Time
Min.
[(12.5nsec or 1TPB) / N]
+ 25nsec
—
—
nsec Must also meet
parameter TA15.
Asynchronous,
with prescaler
10
—
—
nsec
Synchronous,
with prescaler
[(12.5nsec or 1TPB) / N]
+ 25nsec
—
—
nsec Must also meet
parameter TA15.
Asynchronous,
with prescaler
10
—
—
nsec
[(25nsec or 2TPB) / N]
+ 50nsec
—
—
nsec
20
—
—
nsec N = prescale
value
(1, 8, 64, 256)
—
100
kHz
1
TPB
TxCK
Synchronous,
Input Period with prescaler
OS60
FT1
SOSC1/T1CK Oscillator
Input Frequency Range
(oscillator enabled by setting TCS bit (T1CON<1>))
32
TA20
TCKEXT-
Delay from External TxCK
Clock Edge to Timer Increment
—
Note 1:
2:
Conditions
Synchronous,
with prescaler
Asynchronous,
with prescaler
MRL
Typical Max. Units
Timer1 is a Type A.
This parameter is characterized, but not tested in manufacturing.
DS61143F-page 134
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 28-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Max.
Units
Conditions
Must also meet N = prescale
value
parameter
(1, 2, 4, 8, 16,
TB15.
Must also meet 32, 64, 256)
TB10
TTXH
TxCK
High Time
Synchronous,
with prescaler
[(12.5nsec or 1TPB) / N]
+ 25nsec
—
nsec
TB11
TTXL
TxCK
Low Time
Synchronous,
with prescaler
[(12.5nsec or 1TPB) / N]
+ 25nsec
—
nsec
[(25nsec or 2TPB) / N]
+ 50nsec
—
nsec
—
1
TPB
TB15
TTXP
TB20
TCKEXT- Delay from External TxCK
Clock Edge to Timer IncreMRL
ment
Note 1:
TxCK
Synchronous,
Input Period with prescaler
parameter
TB15.
These parameters are characterized, but not tested in manufacturing.
FIGURE 28-7:
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note: Refer to Figure 28-1 for load conditions.
TABLE 28-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Param.
Symbol
No.
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Characteristics(1)
Min.
Max.
Units
Conditions
IC10
TCCL
ICx Input Low Time
[(12.5nsec or 1TPB) / N]
+ 25nsec
—
nsec
Must also
meet
parameter
IC15.
IC11
TCCH
ICx Input High Time
[(12.5nsec or 1TPB) / N]
+ 25nsec
—
nsec
Must also
meet
parameter
IC15.
IC15
TCCP
ICx Input Period
[(25nsec or 2TPB) / N]
+ 50nsec
—
nsec
Note 1:
These parameters are characterized, but not tested in manufacturing.
© 2009 Microchip Technology Inc.
Preliminary
N = prescale
value (1, 4, 16)
DS61143F-page 135
PIC32MX3XX/4XX
FIGURE 28-8:
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC10
OC11
Note: Refer to Figure 28-1 for load conditions.
TABLE 28-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical(2)
Max.
Units
Conditions
OC10
TCCF
OCx Output Fall Time
—
—
—
nsec
See parameter DO32.
OC11
TCCR
OCx Output Rise Time
—
—
—
nsec
See parameter DO31.
Note 1:
2:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
FIGURE 28-9:
OC/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA/OCFB
OC15
OCx
Note: Refer to Figure 28-1 for load conditions.
TABLE 28-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param
No.
Symbol
Characteristics(1)
Min
Typical(2)
Max
Units
Conditions
OC15
TFD
Fault Input to PWM I/O Change
—
—
25
nsec
OC20
TFLT
Fault Input Pulse Width
50
—
—
nsec
Note 1:
2:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
DS61143F-page 136
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 28-10:
SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
Bit 14 - - - - - -1
MSb
SDOx
SP31
SDIx
LSb
SP30
MSb In
LSb In
Bit 14 - - - -1
SP40 SP41
Note: Refer to Figure 28-1 for load conditions.
TABLE 28-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typical(2) Max.
Units
Conditions
SP10
TSCL
SCKx Output Low Time
(Note 3)
TSCK/2
—
—
nsec
SP11
TSCH
SCKx Output High Time
(Note 3)
TSCK/2
—
—
nsec
SP20
TSCF
SCKx Output Fall Time
(Note 4)
—
—
—
nsec
See parameter DO32.
SP21
TSCR
SCKx Output Rise Time
(Note 4)
—
—
—
nsec
See parameter DO31.
SP30
TDOF
SDOx Data Output Fall Time
(Note 4)
—
—
—
nsec
See parameter DO32.
SP31
TDOR
SDOx Data Output Rise Time
(Note 4)
—
—
—
nsec
See parameter DO31.
SP35
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
15
nsec
SP40
TDIV2SCH,
TDIV2SCL
Setup Time of SDIx Data Input
to SCKx Edge
10
—
—
nsec
SP41
TSCH2DIL,
TSCL2DIL
Hold Time of SDIx Data Input
to SCKx Edge
10
—
—
nsec
Note 1:
2:
3:
4:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The minimum clock period for SCKx is 40 nsec. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 137
PIC32MX3XX/4XX
FIGURE 28-11:
SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKX
(CKP = 0)
SP11
SCKX
(CKP = 1)
SP10
SP21
SP20
SP20
SP21
SP35
LSb
Bit 14 - - - - - -1
MSb
SDOX
SP30,SP31
SDIX
MSb In
SP40
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 28-1 for load conditions.
TABLE 28-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°Cfor Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typical(2)
Max.
Units
Conditions
SP10
TSCL
SCKx Output Low Time
(Note 3)
TSCK/2
—
—
nsec
SP11
TSCH
SCKx Output High Time
(Note 3)
TSCK/2
—
—
nsec
SP20
TSCF
SCKx Output Fall Time
(Note 4)
—
—
—
nsec
See parameter DO32.
SP21
TSCR
SCKx Output Rise Time
(Note 4)
—
—
—
nsec
See parameter DO31.
SP30
TDOF
SDOx Data Output Fall Time
(Note 4)
—
—
—
nsec
See parameter DO32.
SP31
TDOR
SDOx Data Output Rise Time
(Note 4)
—
—
—
nsec
See parameter DO31.
SP35
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
15
nsec
SP36
TDOV2SC, SDOx Data Output Setup to
TDOV2SCL First SCKx Edge
15
—
—
nsec
SP40
TDIV2SCH, Setup Time of SDIx Data Input
TDIV2SCL to SCKx Edge
10
—
—
nsec
Note 1:
2:
3:
4:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The minimum clock period for SCKx is 40 nsec. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
DS61143F-page 138
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 28-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°Cfor Industrial
AC CHARACTERISTICS
Param.
No.
SP41
Symbol
TSCH2DIL,
TSCL2DIL
Note 1:
2:
3:
4:
Characteristics(1)
Hold Time of SDIx Data Input
to SCKx Edge
Min.
Typical(2)
Max.
Units
10
—
—
nsec
Conditions
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The minimum clock period for SCKx is 40 nsec. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
FIGURE 28-12:
SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
MSb
SDOX
Bit 14 - - - - - -1
LSb
SP51
SP30,SP31
SDIX
MSb In
SP40
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 28-1 for load conditions.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 139
PIC32MX3XX/4XX
TABLE 28-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typical(2)
Max.
Units
SP70
TSCL
SCKx Input Low Time
(Note 3)
TSCK/2
—
—
nsec
SP71
TSCH
SCKx Input High Time
(Note 3)
TSCK/2
—
—
nsec
Conditions
SP72
TSCF
SCKx Input Fall Time
—
5
10
nsec
SP73
TSCR
SCKx Input Rise Time
—
5
10
nsec
SP30
TDOF
SDOx Data Output Fall Time
(Note 4)
—
—
—
nsec
See parameter DO32.
SP31
TDOR
SDOx Data Output Rise Time
(Note 4)
—
—
—
nsec
See parameter DO31.
SP35
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
15
nsec
SP40
TDIV2SCH, Setup Time of SDIx Data Input
TDIV2SCL to SCKx Edge
10
—
—
nsec
SP41
TSCH2DIL,
TSCL2DIL
10
—
—
nsec
SP50
TSSL2SCH, SSx ↓ to SCKx ↑ or SCKx Input
TSSL2SCL
60
—
—
nsec
SP51
TSSH2DOZ SSx ↑ to SDOx Output
High-Impedance
(Note 3)
5
—
25
nsec
SP52
TSCH2SSH SSx after SCKx Edge
TSCL2SSH
TSCK + 20
—
—
nsec
Note 1:
2:
3:
4:
Hold Time of SDIx Data Input
to SCKx Edge
—
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The minimum clock period for SCKx is 40 nsec.
Assumes 50 pF load on all SPIx pins.
DS61143F-page 140
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 28-13:
SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
SP52
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP30,SP31
SDIx
SDI
MSb In
SP40
SP51
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 28-1 for load conditions.
TABLE 28-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typical(2)
Max.
Units
Conditions
SP70
TSCL
SCKx Input Low Time
(Note 3)
TSCK/2
—
—
nsec
SP71
TSCH
SCKx Input High Time
(Note 3)
TSCK/2
—
—
nsec
SP72
TSCF
SCKx Input Fall Time
—
5
10
nsec
SP73
TSCR
SCKx Input Rise Time
—
5
10
nsec
SP30
TDOF
SDOx Data Output Fall Time
(Note 4)
—
—
—
nsec
See parameter
DO32.
SP31
TDOR
SDOx Data Output Rise Time
(Note 4)
—
—
—
nsec
See parameter
DO31.
SP35
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
15
nsec
SP40
TDIV2SCH, Setup Time of SDIx Data Input
TDIV2SCL to SCKx Edge
10
—
—
nsec
SP41
TSCH2DIL,
TSCL2DIL
10
—
—
nsec
Note 1:
2:
3:
4:
Hold Time of SDIx Data Input
to SCKx Edge
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The minimum clock period for SCKx is 40 nsec.
Assumes 50 pF load on all SPIx pins.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 141
PIC32MX3XX/4XX
TABLE 28-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Characteristics(1)
Symbol
Min.
Typical(2)
Max.
Units
SP50
TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑
TSSL2SCL Input
60
—
—
nsec
SP51
TSSH2DOZ SSx ↑ to SDOX Output
High-Impedance
(Note 4)
5
—
25
nsec
SP52
TSCH2SSH SSx ↑ after SCKx Edge
TSCL2SSH
TSCK + 20
—
—
nsec
SP60
TSSL2DOV SDOx Data Output Valid after
SSx Edge
—
—
25
nsec
Note 1:
2:
3:
4:
Conditions
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The minimum clock period for SCKx is 40 nsec.
Assumes 50 pF load on all SPIx pins.
FIGURE 28-14:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 28-1 for load conditions.
FIGURE 28-15:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM11
IM26
IM10
IM25
IM33
SDAx
In
IM40
IM40
IM45
SDAx
Out
Note: Refer to Figure 28-1 for load conditions.
DS61143F-page 142
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 28-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
IM10
IM11
IM20
Min.(1)
Max.
Units
Conditions
TPB * (BRG + 2)
—
μs
—
400 kHz mode
TPB * (BRG + 2)
—
μs
—
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
μs
—
Clock High Time 100 kHz mode
TPB * (BRG + 2)
—
μs
—
400 kHz mode
TPB * (BRG + 2)
—
μs
—
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
μs
—
—
300
nsec
Characteristics
TLO:SCL Clock Low Time 100 kHz mode
THI:SCL
TF:SCL
SDAx and SCLx 100 kHz mode
Fall Time
400 kHz mode
20 + 0.1 CB
300
nsec
—
100
nsec
—
1000
nsec
20 + 0.1 CB
300
nsec
—
300
nsec
100 kHz mode
250
—
nsec
400 kHz mode
100
—
nsec
1 MHz mode
(Note 2)
100
—
nsec
1 MHz mode
(Note 2)
IM21
TR:SCL
SDAx and SCLx 100 kHz mode
Rise Time
400 kHz mode
1 MHz mode
(Note 2)
IM25
IM26
IM30
IM31
IM33
IM34
TSU:DAT Data Input
Setup Time
THD:DAT Data Input
Hold Time
TSU:STA Start Condition
Setup Time
THD:STA Start Condition
Hold Time
TSU:STO Stop Condition
Setup Time
THD:STO Stop Condition
Hold Time
Note 1:
2:
100 kHz mode
0
—
μs
400 kHz mode
0
0.9
μs
1 MHz mode
(Note 2)
0
0.3
μs
100 kHz mode
TPB * (BRG + 2)
—
μs
400 kHz mode
TPB * (BRG + 2)
—
μs
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
μs
100 kHz mode
TPB * (BRG + 2)
—
μs
400 kHz mode
TPB * (BRG + 2)
—
μs
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
μs
100 kHz mode
TPB * (BRG + 2)
—
μs
400 kHz mode
TPB * (BRG + 2)
—
μs
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
μs
100 kHz mode
TPB * (BRG + 2)
—
nsec
400 kHz mode
TPB * (BRG + 2)
—
nsec
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
nsec
CB is specified to be
from 10 to 400 pF.
CB is specified to be
from 10 to 400 pF.
—
—
Only relevant for
Repeated Start
condition.
After this period, the
first clock pulse is
generated.
—
—
BRG is the value of the I2C™ Baud Rate Generator.
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 143
PIC32MX3XX/4XX
TABLE 28-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
IM40
TAA:SCL
IM45
Output Valid
From Clock
TBF:SDA Bus Free Time
IM50
CB
Note 1:
2:
Min.(1)
Max.
Units
Conditions
100 kHz mode
—
3500
nsec
—
400 kHz mode
—
1000
nsec
—
1 MHz mode
(Note 2)
—
350
nsec
—
The amount of time the
bus must be free
before a new
transmission can start.
Characteristics
100 kHz mode
4.7
—
μs
400 kHz mode
1.3
—
μs
1 MHz mode
(Note 2)
0.5
—
μs
—
400
pF
Bus Capacitive Loading
I2C™
BRG is the value of the
Baud Rate Generator.
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
FIGURE 28-16:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 28-1 for load conditions.
FIGURE 28-17:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS26
IS31
IS25
IS33
SDAx
In
IS40
IS40
IS45
SDAx
Out
Note: Refer to Figure 28-1 for load conditions.
DS61143F-page 144
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 28-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
IS10
IS11
IS20
Symbol
TLO:SCL
THI:SCL
TF:SCL
Characteristics
Clock Low Time
Clock High Time
SDAx and SCLx
Fall Time
Min.
Max.
Units
100 kHz mode
4.7
—
μs
PBCLK must operate at a
minimum of 800 KHz.
400 kHz mode
1.3
—
μs
PBCLK must operate at a
minimum of 3.2 MHz.
1 MHz mode
(Note 1)
0.5
—
μs
100 kHz mode
4.0
—
μs
PBCLK must operate at a
minimum of 800 KHz.
400 kHz mode
0.6
—
μs
PBCLK must operate at a
minimum of 3.2 MHz.
1 MHz mode
(Note 1)
0.5
—
μs
100 kHz mode
—
300
nsec
400 kHz mode
20 + 0.1 CB
300
nsec
—
100
nsec
100 kHz mode
—
1000
nsec
400 kHz mode
20 + 0.1 CB
300
nsec
—
300
nsec
100 kHz mode
250
—
nsec
400 kHz mode
100
—
nsec
1 MHz mode
(Note 1)
100
—
nsec
100 kHz mode
0
—
nsec
400 kHz mode
0
0.9
μs
1 MHz mode
(Note 1)
0
0.3
μs
100 kHz mode
4700
—
μs
400 kHz mode
600
—
μs
1 MHz mode
(Note 1)
250
—
μs
100 kHz mode
4000
—
μs
400 kHz mode
600
—
μs
1 MHz mode
(Note 1)
250
—
μs
100 kHz mode
4000
—
μs
400 kHz mode
600
—
μs
1 MHz mode
(Note 1)
600
—
μs
1 MHz mode
(Note 1)
IS21
TR:SCL
SDAx and SCLx
Rise Time
1 MHz mode
(Note 1)
IS25
IS26
IS30
IS31
IS33
Note 1:
TSU:DAT
THD:DAT
TSU:STA
THD:STA
TSU:STO
Data Input
Setup Time
Data Input
Hold Time
Start Condition
Setup Time
Start Condition
Hold Time
Stop Condition
Setup Time
Conditions
CB is specified to be from
10 to 400 pF.
CB is specified to be from
10 to 400 pF.
Only relevant for Repeated
Start condition.
After this period, the first
clock pulse is generated.
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 145
PIC32MX3XX/4XX
TABLE 28-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
IS34
IS40
Symbol
THD:STO
TAA:SCL
Characteristics
Stop Condition
Hold Time
Min.
IS50
Note 1:
TBF:SDA
4000
—
nsec
400 kHz mode
600
—
nsec
1 MHz mode
(Note 1)
250
Output Valid From 100 kHz mode
Clock
400 kHz mode
CB
Bus Free Time
Units
100 kHz mode
3500
nsec
0
1000
nsec
0
350
nsec
100 kHz mode
4.7
—
μs
400 kHz mode
1.3
—
μs
1 MHz mode
(Note 1)
0.5
—
μs
—
400
pF
Bus Capacitive Loading
Conditions
nsec
0
1 MHz mode
(Note 1)
IS45
Max.
The amount of time the bus
must be free before a new
transmission can start.
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
TABLE 28-34: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics
Standard Operating Conditions: 2.5V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Min.
Typical
Max.
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply
Greater of
VDD – 0.3
or 2.5
—
Lesser of
VDD + 0.3
or 3.6
V
AD02
AVSS
Module VSS Supply
VSS
—
VSS + 0.3
V
AVDD
V
(Note 1)
Reference Inputs
VREFH
Reference Voltage High
AVSS + 2.0
—
2.5
—
3.6
V
VREFH = AVDD (Note 3)
AD06
VREFL
Reference Voltage Low
AVSS
—
VREFH –
2.0
V
(Note 1)
AD07
VREF
Absolute Reference
Voltage
(VREFH – VREFL)
2.0
—
AVDD
V
(Note 3)
AD08
IREF
Current Drain
—
250
—
400
3
μA
μA
ADC operating
ADC off
VREFL
—
AD05
AD05a
Analog Input
AD12
VINH-VINL Full-Scale Input Span
VINL
Note 1:
2:
3:
Absolute VINL Input
Voltage
AVSS – 0.3
VREFH
V
AVDD/2
V
These parameters are not characterized or tested in manufacturing.
With no missing codes.
These parameters are characterized, but not tested in manufacturing.
DS61143F-page 146
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 28-34: ADC MODULE SPECIFICATIONS (CONTINUED)
AC CHARACTERISTICS
Param.
No.
Symbol
Absolute Input Voltage
VIN
AD17
Characteristics
RIN
Standard Operating Conditions: 2.5V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Min.
Typical
AVSS – 0.3
Max.
Units
AVDD +
0.3
V
Conditions
Leakage Current
—
+/- 0.001
+/-0.610
μA
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
Source Impedance = 10KΩ
Recommended
Impedance of Analog
Voltage Source
—
—
5K
Ω
(Note 1)
ADC Accuracy – Measurements with External VREF+/VREF-
AD20c Nr
Resolution
10 data bits
bits
AD21c INL
Integral Nonlinearity
—
—
<+/-1
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
AD22c DNL
Differential Nonlinearity
—
—
<+/-1
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
(Note 2)
AD23c GERR
Gain Error
—
—
<+/-1
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
AD24n EOFF
Offset Error
—
—
<+/-1
LSb VINL = AVSS = 0V,
AVDD = 3.3V
AD25c —
Monotonicity
—
—
—
—
Guaranteed
bits
(Note 3)
ADC Accuracy – Measurements with Internal VREF+/VREF-
AD20d Nr
Resolution
AD21d INL
Integral Nonlinearity
—
—
<+/-1
LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Note 3)
AD22d DNL
Differential Nonlinearity
—
—
<+/-1
LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Notes 2, 3)
AD23d GERR
Gain Error
—
—
<+/-4
LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Note 3)
AD24d EOFF
Offset Error
—
—
<+/-2
LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Note 3)
AD25d
Monotonicity
—
—
—
Note 1:
2:
3:
—
10 data bits
—
Guaranteed
These parameters are not characterized or tested in manufacturing.
With no missing codes.
These parameters are characterized, but not tested in manufacturing.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 147
PIC32MX3XX/4XX
TABLE 28-35: 10-BIT CONVERSION RATE PARAMETERS
PIC32MX 10-bit A/D Converter Conversion Rates (Note 2)
ADC Speed
1 MIPS to 400
ksps
(Note 1)
TAD
Sampling
RS Max
Minimum Time Min
65 ns
132 ns
500Ω
VDD
Temperature
3.0V to
3.6V
-40°C to
+85°C
ADC Channels Configuration
VREF- VREF+
CHX
ANx
Up to 400 ksps
200 ns
200 ns
5.0 kΩ
2.5V to
3.6V
SHA
ADC
-40°C to
+85°C
VREF- VREF+
or
or
AVSS AVDD
CHX
ANx
SHA
ADC
ANx or VREF-
Up to 300 ksps
200 ns
200 ns
5.0 kΩ
2.5V to
3.6V
-40°C to
+85°C
VREF- VREF+
or
or
AVSS AVDD
CHX
ANx
SHA
ADC
ANx or VREF-
Note 1:
2:
External VREF- and VREF+ pins must be used for correct operation.
These parameters are characterized, but not tested in manufacturing.
DS61143F-page 148
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 28-36: A/D CONVERSION TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.
Typical(1)
Max.
Units
Conditions
Clock Parameters
AD50
TAD
A/D Clock Period (Note 2)
65
—
—
nsec
See Table 28-35.
AD51
TRC
A/D Internal RC Oscillator Period
—
250
—
nsec
(Note 3)
Conversion Rate
AD55
TCONV
Conversion Time
—
12 TAD
—
—
—
AD56
FCNV
Throughput Rate
(Sampling Speed)
—
—
1000
KSPS
AVDD = 3.0V to 3.6V
—
—
400
KSPS
AVDD = 2.5V to 3.6V
Sample Time
1
—
31
TAD
TSAMP must be ≥ 132
nsec.
—
1.0 TAD
—
—
Auto-Convert Trigger
(SSRC<2:0> = 111)
not selected.
AD57
TSAMP
Timing Parameters
AD60
TPCS
Conversion Start from Sample
Trigger(3)
AD61
TPSS
Sample Start from Setting
Sample (SAMP) bit
0.5 TAD
—
1.5 TAD
—
—
AD62
TCSS
Conversion Completion to
Sample Start (ASAM = 1)
(Note 3)
—
0.5 TAD
—
—
—
AD63
TDPU
Time to Stabilize Analog Stage
from A/D OFF to A/D ON
(Note 3)
—
—
2
μs
—
Note 1:
2:
3:
These parameters are characterized, but not tested in manufacturing.
Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
Characterized by design but not tested.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 149
PIC32MX3XX/4XX
FIGURE 28-18:
A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS
(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)
AD50
ADCLK
Instruction
Execution Set SAMP
Clear SAMP
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
AD61
AD60
AD55
TSAMP
AD55
CONV
ADxIF
Buffer(0)
Buffer(1)
1
2
3
4
5
6
7
8
5
6
7
8
1 – Software sets ADxCON. SAMP to start sampling.
2 – Sampling starts after discharge period. TSAMP is described in the “PIC32MX Family Reference Manual” (DS61132).
3 – Software clears ADxCON. SAMP to start conversion.
4 – Sampling ends, conversion sequence starts.
5 – Convert bit 9.
6 – Convert bit 8.
7 – Convert bit 0.
8 – One TAD for end of conversion.
DS61143F-page 150
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 28-19:
A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01,
SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001
AD50
ADCLK
Instruction
Execution
Set ADON
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
TSAMP
AD55
TSAMP
AD55
TCONV
CONV
ADxIF
Buffer(0)
Buffer(1)
1
2
3
4
5
6
7
3
4
5
6
8
3
4
1 – Software sets ADxCON. ADON to start AD operation.
5 – Convert bit 0.
2 – Sampling starts after discharge period.
TSAMP is described in the “PIC32MX
Family Reference Manual” (DS61132).
6 – One TAD for end of conversion.
3 – Convert bit 9.
8 – Sample for time specified by SAMC<4:0>.
7 – Begin conversion of next channel.
4 – Convert bit 8.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 151
PIC32MX3XX/4XX
FIGURE 28-20:
PARALLEL SLAVE PORT TIMING
CS
PS5
RD
PS6
WR
PS4
PS7
PMD<7:0>
PS1
PS3
PS2
TABLE 28-37: PARALLEL SLAVE PORT REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typical
Max.
Units
PS1
TdtV2wrH Data In Valid before WR or CS Inactive
(setup time)
20
—
—
nsec
PS2
TwrH2dtI
WR or CS Inactive to Data–
In Invalid (hold time)
20
—
—
nsec
PS3
TrdL2dtV
RD and CS Active to Data–
Out Valid
—
—
60
nsec
PS4
TrdH2dtI
RD Active or CS Inactive to Data–
Out Invalid
0
—
10
nsec
PS5
Tcs
CS Active Time
25
—
—
nsec
PS6
TWR
WR Active Time
25
—
—
nsec
PS7
TRD
RD Active Time
25
—
—
nsec
Note 1:
Conditions
These parameters are characterized, but not tested in manufacturing.
DS61143F-page 152
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 28-21:
PARALLEL MASTER PORT READ TIMING DIAGRAM
TPB
TPB
TPB
TPB
TPB
TPB
TPB
TPB
PB Clock
PM4
Address
PMA<13:18>
PM6
PMD<7:0>
Data
Data
Address<7:0>
Address<7:0>
PM2
PM7
PM3
PMRD
PM5
PMWR
PM1
PMALL/PMALH
PMCS<2:1>
TABLE 28-38: PARALLEL MASTER PORT READ TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical
Max.
Units
PM1
TLAT
PMALL/PMALH Pulse Width
—
1 TPB
—
—
PM2
TADSU
Address Out Valid to PMALL/PMALH
Invalid (address setup time)
—
2 TPB
—
—
PM3
TADHOLD PMALL/PMALH Invalid to Address Out
Invalid (address hold time)
—
1 TPB
—
—
PM4
TAHOLD
PMRD Inactive to Address Out Invalid
(address hold time)
1
—
—
nsec
PM5
TRD
PMRD Pulse Width
—
1 TPB
—
—
PM6
TDSU
PMRD or PMENB Active to Data In
Valid (data setup time)
5
—
—
nsec
PM7
TDHOLD
PMRD or PMENB Inactive to Data In
Invalid (data hold time)
—
0
—
nsec
Note 1:
Conditions
These parameters are characterized, but not tested in manufacturing.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 153
PIC32MX3XX/4XX
FIGURE 28-22:
PARALLEL MASTER PORT WRITE TIMING DIAGRAM
TPB
TPB
TPB
TPB
TPB
TPB
TPB
TPB
PB Clock
Address
PMA<13:18>
PM2 + PM3
Address<7:0>
PMD<7:0>
Data
PM12
PM13
PMRD
PM11
PMWR
PM1
PMALL/PMALH
PMCS<2:1>
TABLE 28-39: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical
Max.
Units
PM11
TWR
PMWR Pulse Width
—
1 TPB
—
—
PM12
TDVSU
Data Out Valid before PMWR or
PMENB goes Inactive (data setup time)
—
2 TPB
—
—
PM13
TDVHOLD PMWR or PMEMB Invalid to Data Out
Invalid (data hold time)
—
1 TPB
—
—
Note 1:
Conditions
These parameters are characterized, but not tested in manufacturing.
DS61143F-page 154
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 28-40: OTG ELECTRICAL SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typ
Max.
Units
Conditions
3.0
—
3.6
V
Voltage on bus must
be in this range for
proper USB operation.
USB313 VUSB
USB Voltage
USB315 VILUSB
Input Low Voltage for USB Buffer
—
—
0.8
V
USB316 VIHUSB
Input High Voltage for USB Buffer
2.0
—
—
V
USB318 VDIFS
Differential Input Sensitivity
—
—
0.2
V
USB319 VCM
Differential Common Mode Range
0.8
—
2.5
V
USB320 ZOUT
Driver Output Impedance
28.0
—
44.0
Ω
USB321 VOL
Voltage Output Low
0.0
—
0.3
V
1.5 kΩ load connected
to 3.6V
USB322 VOH
Voltage Output High
2.8
—
3.6
V
1.5 kΩ load connected
to ground
Note 1:
The difference
between D+ and Dmust exceed this value
while VCM is met.
These parameters are characterized, but not tested in manufacturing.
FIGURE 28-23:
EJTAG TIMING CHARACTERISTICS
TTCKeye
TTCKhigh
TTCKlow
Trf
TCK
Trf
TMS
TDI
TTsetup TThold
Trf
Trf
TDO
TRST*
TTRST*low
TTDOout
Defined
Trf
© 2009 Microchip Technology Inc.
TTDOzstate
Preliminary
Undefined
DS61143F-page 155
PIC32MX3XX/4XX
TABLE 28-41: EJTAG TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
Description(1)
Min.
Max.
Units
EJ1
TTCKCYC
TCK Cycle Time
25
—
nsec
EJ2
TTCKHIGH
TCK High Time
10
—
nsec
EJ3
TTCKLOW
TCK Low Time
10
—
nsec
EJ4
TTSETUP
TAP Signals Setup Time Before
Rising TCK
5
—
nsec
EJ5
TTHOLD
TAP Signals Hold Time After
Rising TCK
3
—
nsec
EJ6
TTDOOUT
TDO Output Delay Time From
Falling TCK
—
5
nsec
EJ7
TTDOZSTATE TDO 3-State Delay Time From
Falling TCK
—
5
nsec
EJ8
TTRSTLOW
TRST Low Time
25
—
nsec
EJ9
TRF
TAP Signals Rise/Fall Time, All
Input and Output
—
—
nsec
Note 1:
Conditions
These parameters are characterized, but not tested in manufacturing.
DS61143F-page 156
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
29.0
PACKAGING INFORMATION
29.1
Package Marking Information
64-Lead TQFP (10x10x1 mm)
Example
PIC32MX360F
512L-80I/PT
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
e3
0510017
Example
100-Lead TQFP (12x12x1 mm)
PIC32MX360F
256L-80I/PT
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
e3
0510017
64-Lead QFN (9x9x0.9 mm)
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
*
Note:
PIC32MX360F
512L-80I/MR
e3
0510017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3)
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 157
PIC32MX3XX/4XX
29.2
Package Details
The following sections give the technical details of the packages.
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Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
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© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 159
PIC32MX3XX/4XX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS61143F-page 160
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 161
PIC32MX3XX/4XX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS61143F-page 162
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
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© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 163
PIC32MX3XX/4XX
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DS61143F-page 164
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
APPENDIX A: REVISION HISTORY
Revision F (June 2009)
Revision E (July 2008)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
Global changes include:
• Updated the PIC32MX340F128H features in
Table 1 to include 4 programmable DMA
channels.
• Changed all instances of OSCI to OSC1 and
OSCO to OSC2
• Changed all instances of VDDCORE and
VDDCORE/VCAP to VCAP/VDDCORE
• Deleted registers in most sections, refer to the
related section of the PIC32MX3XX/4XX Family
Reference Manual (DS61132).
The other changes are referenced by their respective
section in the following table.
TABLE A-1:
MAJOR SECTION UPDATES
Section Name
Update Description
“High-Performance 80 MHz MIPSBased 32-bit Flash Microcontroller
64/100-Pin General Purpose and
USB”
Added a Packages” column to Table 1 and Table 2.
Corrected all pin diagrams to update the following pin names.
Previous:
Current:
PGC!/EMUC1
PGEC1
PGD!/EMUD1
PGED1
PGC2/EMUC2
PGEC2
PGD2/EMUD2
PGED2
Shaded appropriate pins in each diagram to indicate which pins are 5V tolerant.
Added 64-Lead QFN package pin diagrams, one for General Purpose and
one for USB.
Section 1.0 “Device Overview”
Reconstructed Figure 1-1 to include Timers, ADC, and RTCC in the block
diagram.
Section 2.0 “Guidelines for Getting
Started with 32-bit Microcontrollers”
Added a new section to the data sheet that provides the following information:
• Basic Connection Requirements
• Capacitors
• Master Clear PIN
• ICSP Pins
• External Oscillator Pins
• Configuration of Analog and Digital Pins
• Unused I/Os
Section 4.0 “Memory Organization”
Updated the memory maps, Figure 4-1 through Figure 4-6.
All summary peripheral register maps were relocated to Section 4.0
“Memory Organization”.
Section 7.0 “Interrupt Controller”
Removed the “Address” column from Table 7-1.
Section 12.0 “I/O Ports”
Added a second paragraph to Section 12.1.3 “Analog Inputs” to clarify
that all pins that share ANx functions are analog by default, because the
AD1PCFG register has a default value of 0x0000.
Section 26.0 “Special Features”
Modified bit names and locations in Register 26-5 “DEVID: Device and
Revision ID Register”.
Replaced “TSTARTUP” with “TPU”, and “64-ms nominal delay” with “TPWRT”,
in Section 26.3.1 “On-Chip Regulator and POR”.
The information that appeared in the Watchdog Timer and the Programming and Diagnostics sections of 61143E version of this data sheet has
been incorporated into the Special Features section:
Section 26.2 “Watchdog Timer (WDT)”
Section 26.4 “Programming and Diagnostics”
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 165
PIC32MX3XX/4XX
TABLE A-1:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
Section 28.0 “Electrical
Characteristics”
Update Description
In Section 28.1 “DC Characteristics”:
Added the 64-Lead QFN package to Table 28-3.
Updated data in Table 28-5.
Updated data in Table 28-7.
Updated data in Section 28.2 “AC Characteristics and Timing Parameters”, Table 28-4, Table 28-5, Table 28-7 and Table 28-8.
Updated data in Table 28-10.
Added OS42 parameter to Table 28-17.
Replaced Table 28-23.
Replaced Table 28-24.
Replaced Table 28-25.
Updated Table 28-36.
Section 29.0 “Packaging Information” Added 64-Lead QFN package marking information to Section 29.1
“Package Marking Information”.
Added the 64-Lead QFN (MR) package drawing and land pattern to
Section 29.2 “Package Details”.
“Product Identification System”
DS61143F-page 166
Added the MR package designator for the 64-Lead (9x9x0.9) QFN.
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
INDEX
A
Pinout I/O Descriptions (table) 12
Power-on Reset (POR)
and On-Chip Voltage Regulator 109
AC Characteristics 128
Internal RC Accuracy 130
AC Electrical Specifications
Parallel Master Port Read Requirements 153
Parallel Master Port Write Requirements 154
Parallel Slave Port Requirements 152
S
Serial Peripheral Interface (SPI) 57, 67, 81, 89, 91, 100
Special Features 101
T
B
Block Diagrams
A/D Module 93
Comparator I/O Operating Modes 95
Comparator Voltage Reference 97
Connections for On-Chip Voltage Regulator 109
Input Capture 77
JTAG Compliant Application Showing Daisy-Chaining of
Components 110
Output Compare Module 79
Reset System 57
RTCC 91
Type B Timer 19, 65, 75
UART 85
WDT 108
Brown-out Reset (BOR)
and On-Chip Voltage Regulator 109
C
Comparator
Operation 96
Comparator Voltage Reference
Configuring 98
CPU Module 15, 19
D
DC Characteristics 120
I/O Pin Input Specifications 124
I/O Pin Output Specifications 125
Idle Current (IIDLE) 122
Operating Current (IDD) 121
Power-Down Current (IPD) 123
Program Memory 125
Temperature and Voltage Specifications 120
E
Electrical Characteristics 119
AC 128
Errata 10
F
Timer1 Module 59, 65, 73, 75
Timing Diagrams
10-bit A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM
= 0, SSRC = 000) 150
I2Cx Bus Data (Master Mode) 142
I2Cx Bus Data (Slave Mode) 144
I2Cx Bus Start/Stop Bits (Master Mode) 142
I2Cx Bus Start/Stop Bits (Slave Mode) 144
Input Capture (CAPx) 135
OC/PWM 136
Output Compare (OCx) 136
Parallel Master Port Write 153, 154
Parallel Slave Port 152
SPIx Master Mode (CKE = 0) 137
SPIx Master Mode (CKE = 1) 138
SPIx Slave Mode (CKE = 0) 139
SPIx Slave Mode (CKE = 1) 141
Timer1, 2, 3, 4, 5, 6, 7, 8, 9 External Clock 134
Transmission (8-bit or 9-bit Data) 86
UART Reception with Receive Overrun 87
Timing Requirements
CLKO and I/O 131
Timing Specifications
I2Cx Bus Data Requirements (Master Mode) 142
I2Cx Bus Data Requirements (Slave Mode) 144
Output Compare Requirements 136
Simple OC/PWM Mode Requirements 136
SPIx Master Mode (CKE = 0) Requirements 137
SPIx Master Mode (CKE = 1) Requirements 138
SPIx Slave Mode (CKE = 1) Requirements 141
V
VDDCORE/VCAP Pin 108
Voltage Reference Specifications 126
Voltage Regulator (On-Chip) 108
W
Watchdog Timer
Operation 108
WWW, On-Line Support 10
Flash Program Memory 55
RTSP Operation 55
I
I/O Ports 71, 85
Parallel I/O (PIO) 72
P
Packaging 157
Details 158
Marking 157
PIC32 Family USB Interface Diagram 70
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 167
PIC32MX3XX/4XX
NOTES:
DS61143F-page 168
Preliminary
© 2009 Microchip Technology Inc.
PIC32MX3XX/4XX
Product Identification System
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PIC32 MX 3XX F 512 H T - 80 I / PT - XXX
Examples:
PIC32MX320F032H-40I/PT:
General purpose PIC32MX, 32 KB program
memory, 64-pin, Industrial temp.,
TQFP package.
Microchip Brand
Architecture
Product Groups
Flash Memory Family
PIC32MX360F256L-80I/PT:
General purpose PIC32MX, 256 KB program
memory, 100-pin, Industrial temp.,
TQFP package.
Program Memory Size (KB)
Pin Count
Tape and Reel Flag (if applicable)
Speed
Temperature Range
Package
Pattern
Flash Memory Family
Architecture
MX = 32-bit RISC MCU core
Product Groups
3xx = General purpose microcontroller family
4xx = USB
Flash Memory Family
F = Flash program memory
Program Memory Size 32
64
128
256
512
= 32K
= 64K
= 128K
= 256K
= 512K
Pin Count
H = 64-pin
L = 100-pin
Temperature Range
I
Package
PT = 64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack)
PT = 100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack)
MR = 64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat)
Pattern
Three-digit QTP, SQTP, Code or Special Requirements
(blank otherwise)
ES = Engineering Sample
= -40°C to +85°C (Industrial)
© 2009 Microchip Technology Inc.
Preliminary
DS61143F-page 169
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03/26/09
DS61143F-page 170
Preliminary
© 2009 Microchip Technology Inc.