NSC 54ACT257L

54AC257 • 54ACT257
Quad 2-Input Multiplexer with TRI-STATE ® Outputs
General Description
Features
The ’AC/’ACT257 is a quad 2-input multiplexer with
TRI-STATE outputs. Four bits of data from two sources can
be selected using a Common Data Select input. The four
outputs present the selected data in true (noninverted) form.
The outputs may be switched to a high impedance state by
placing a logic HIGH on the common Output Enable (OE) input, allowing the outputs to interface directly with
bus-oriented systems.
n
n
n
n
n
n
ICC and IOZ reduced by 50%
Multiplexer expansion by tying outputs together
Noninverting TRI-STATE outputs
Outputs source/sink 24 mA
’ACT257 has TTL-compatible inputs
Standard Military Drawing (SMD)
— ’AC257: 5962-88703
— ’ACT257: 5962-89689
Logic Symbols
IEEE/IEC
DS100286-1
DS100286-2
Pin Names
Description
S
Common Data Select Input
OE
TRI-STATE Output Enable Input
I0a–I0d
Data Inputs from Source 0
I1a–I1d
Data Inputs from Source 1
Za–Zd
TRI-STATE Multiplexer Outputs
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
FACT™ is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100286
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54AC257 • 54ACT257 Quad 2-Input Multiplexer with TRI-STATE Outputs
July 1998
Connection Diagrams
Functional Description
The ’AC/’ACT257 is quad 2-input multiplexer with
TRI-STATE outputs. It selects four bits of data from two
sources under control of a Common Data Select input. When
the Select input is LOW, the I0x inputs are selected and when
Select is HIGH, the I1x inputs are selected. The data on the
selected inputs appears at the outputs in true (noninverted)
form. The device is the logic implementation of a 4-pole,
2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. The
logic equations for the outputs are shown below:
Za = OE • (11a • S + I0a • S)
Zb = OE • (11b • S + I0b • S)
Zc = OE • (11c • S + I0c • S)
Zd = OE • (11d • S + I0d • S)
Pin Assignment for
DIP and Flatpak
DS100286-3
When the Output Enable (OE) is HIGH, the outputs are
forced to a high impedance state. If the outputs are tied together, all but one device must be in the high impedance
state to avoid high currents that would exceed the maximum
ratings. Designers should ensure the Output Enable signals
to TRI-STATE devices whose outputs are tied together are
designed so there is no overlap.
Pin Assignment for LCC
Truth Table
DS100286-4
Output
Select
Data
Enable
Input
Inputs
Outputs
OE
S
I0
I1
Z
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
L
X
L
L
L
H
X
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Logic Diagram
DS100286-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC +0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC +0.5V
DC Output Voltage (VO)
DC Output Source or Sink Current
(IO)
DC VCC or Ground Current
Per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ)
CDIP
Supply Voltage (VCC)
’AC
’ACT
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
54AC/ACT
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to VCC +0.5V
−20 mA
+20 mA
−0.5V to VCC +0.5V
± 50 mA
± 50 mA
−65˚C to +150˚C
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
0V to VCC
−55˚C to +125˚C
125 mV/ns
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT™ circuits outside databook specifications.
175˚C
DC Characteristics for ’AC Family Devices
Symbol
Parameter
54AC
TA =
VCC
(V)
Units
Conditions
−55˚C to +125˚C
Guaranteed
Limits
VIH
VIL
VOH
Minimum High
3.0
2.1
Level Input
4.5
3.15
Voltage
5.5
3.85
Maximum Low
3.0
0.9
Level Input
4.5
1.35
Voltage
5.5
1.65
Minimum High
3.0
2.9
Level Output
4.5
4.4
Voltage
5.5
5.4
VOUT = 0.1V
V
or VCC − 0.1V
V
or VCC − 0.1V
VOUT = 0.1V
IOUT = −50 µA
V
(Note 2)
VIN = VIL or VIH
VOL
3.0
2.4
4.5
3.7
5.5
4.7
Maximum Low
3.0
0.1
Level Output
4.5
0.1
Voltage
5.5
0.1
−12 mA
V
IOH
−24 mA
−24 mA
IOUT = 50 µA
V
(Note 2)
VIN = VIL or VIH
IIN
Maximum Input
3.0
0.50
4.5
0.50
5.5
0.50
5.5
± 1.0
12 mA
V
µA
IOL
24 mA
24 mA
VI = VCC, GND
Leakage Current
3
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DC Characteristics for ’AC Family Devices
Symbol
Parameter
54AC
TA =
VCC
(V)
(Continued)
Units
Conditions
−55˚C to +125˚C
Guaranteed
Limits
IOZ
5.5
± 10.0
µA
VI (OE) = VIL, VIH
VI = VCC, GND
VO = VCC, GND
5.5
50
mA
VOLD = 1.65V Max
5.5
−50
mA
VOHD = 3.85V Min
5.5
80.0
µA
VIN = VCC
Maximum
TRI-STATE
Leakage Current
IOLD
IOHD
(Note 3) Minimum
Dynamic Output
Current
ICC
Maximum Quiescent
Supply Current
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
Note 5: ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C.
DC Characteristics for ’ACT Family Devices
Symbol
Parameter
54ACT
TA =
VCC
(V)
Units
Conditions
−55˚C to +125˚C
Guaranteed
Limits
VIH
VIL
VOH
VOL
IIN
Minimum High
Level Input
Voltage
Maximum Low
Level Input
Voltage
Minimum High
Level Output
Voltage
Maximum Low
Level Output
Voltage
Maximum Input
4.5
2.0
5.5
2.0
4.5
0.8
5.5
0.8
4.5
4.4
5.5
5.4
V
VOUT = 0.1V
or VCC − 0.1V
V
VOUT = 0.1V
or VCC − 0.1V
V
IOUT = −50 µA
(Note 6)
VIN = VIL or VIH
4.5
3.70
5.5
4.70
4.5
0.1
5.5
0.1
V
IOH
−24 mA
−24 mA
V
IOUT = 50 µA
(Note 6)
VIN = VIL or VIH
4.5
0.50
5.5
0.50
V
IOL
24 mA
5.5
± 1.0
µA
5.5
± 10.0
µA
VI = VIL, VIH
VO = VCC, GND
5.5
1.6
mA
VI = VCC − 2.1V
5.5
50
mA
VOLD = 1.65V Max
5.5
−50
mA
VOHD = 3.85V Min
24 mA
VI = VCC, GND
Leakage Current
IOZ
Maximum TRI-STATE
Leakage Current
ICCT
Maximum
ICC/Input
IOLD
IOHD
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(Note 7) Minimum
Dynamic Output
Current
4
DC Characteristics for ’ACT Family Devices
Symbol
Parameter
54ACT
TA =
VCC
(V)
(Continued)
Units
Conditions
−55˚C to +125˚C
Guaranteed
Limits
ICC
Maximum Quiescent
5.5
80.0
VIN = VCC
µA
Supply Current
or GND
Note 6: All outputs loaded; thresholds on input associated with output under test.
Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
Note 8: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C.
AC Electrical Characteristics
Symbol
Parameter
54AC
TA = −55˚C
VCC
(V)
(Note 9)
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Units
to +125˚C
CL = 50 pF
Propagation Delay
3.3
1.0
11.0
In to Zn
5.0
1.0
8.0
Propagation Delay
3.3
1.0
11.0
In to Zn
5.0
1.0
8.5
Propagation Delay
3.3
1.0
14.5
S to Zn
5.0
1.0
11.0
Propagation Delay
3.3
1.0
14.5
S to Zn
5.0
1.0
11.0
Output Enable Time
3.3
1.0
13.0
5.0
1.0
10.0
3.3
1.0
11.0
5.0
1.0
9.5
3.3
1.0
13.0
5.0
1.0
11.0
3.3
1.0
10.5
5.0
1.0
9.5
Output Enable Time
Output Disable Time
Output Disable Time
ns
ns
ns
ns
ns
ns
ns
ns
Note 9: Voltage Range 3.3 is 3.0V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics
Symbol
Parameter
54ACT
TA = −55˚C
VCC
(V)
(Note 10)
tPLH
Propagation Delay
Units
to +125˚C
CL = 50 pF
5.0
1.0
8.0
ns
5.0
1.0
9.5
ns
5.0
1.0
11.0
ns
5.0
1.0
11.5
ns
5.0
1.0
9.5
ns
In to Zn
tPHL
Propagation Delay
In to Zn
tPLH
Propagation Delay
S to Zn
tPHL
Propagation Delay
S to Zn
tPZH
Output Enable Time
5
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AC Electrical Characteristics
Symbol
(Continued)
Parameter
54ACT
TA = −55˚C
VCC
(V)
Units
to +125˚C
CL = 50 pF
(Note 10)
tPZL
Output Enable Time
5.0
1.0
9.5
ns
tPHZ
Output Disable Time
5.0
1.0
10.5
ns
tPLZ
Output Disable Time
5.0
1.0
9.5
ns
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
CIN
CPD
Typ
Units
Input Capacitance
Parameter
4.5
pF
Power Dissipation
50.0
pF
Capacitance
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6
Conditions
VCC = OPEN
VCC = 5.0V
Physical Dimensions
inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
16 Lead Ceramic Flatpak (F)
NS Package Number W16A
7
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54AC257 • 54ACT257 Quad 2-Input Multiplexer with TRI-STATE Outputs
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ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
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