IR3086 PRELIMINARY DATA SHEET XPHASETM PHASE IC WITH OVP, FAULT AND OVERTEMP DETECT DESCRIPTION The IR3086 Phase IC combined with an IR XPhaseTM Control IC provides a full featured and flexible way to implement power solutions for the latest high performance CPUs and ASICs. The “Control” IC provides overall system control and interfaces with any number of “Phase” ICs which each drive and monitor a single phase of a multiphase converter. The XPhaseTM architecture results in a power supply that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches. FEATURES • • • • • • • • • • • • • 2.5A Average Gate Drive Current Loss-Less Inductor Current Sense Internal Inductor DCR Temperature Compensation Programmable Phase Delay Programmable Feed-Forward Voltage Mode PWM Ramp Sub 100ns Minimum Pulse Width supports 1MHz per-phase operation Current Sense Amplifier drives a single wire Average Current Share Bus Current Share Amplifier reduces PWM Ramp slope to ensure sharing between phases Body BrakingTM disables Synchronous MOSFET for improved transient response and prevents negative output voltage at converter turn-off OVP comparator with 150ns response Phase Fault Detection Programmable Phase Over-Temperature Detection Small thermally enhanced 20L MLPQ package 6 Page 1 of 15 CSIN+ 16 17 CSIN- PHSFLT 18 19 PGND GATEL 14 13 12 11 VCC VCCL LGND ISHARE GATEH 15 10 VRHOT PWMRMP HOTSET SCOMP 5 IR3086 PHASE IC RMPIN- 9 4 VCCH EAIN 3 RMPIN+ 8 2 7 1 DACIN BIASIN 20 PACKAGE PINOUT 9/1/03 IR3086 ORDERING INFORMATION Device Order Quantity IR3086MTR 3000 IR3086M 5 per Bag ABSOLUTE MAXIMUM RATINGS Operating Junction Temperature……………..150oC Storage Temperature Range………………….-65oC to 150oC ESD Rating………………………………………HBM Class 1C JEDEC standard PIN # PIN NAME VMAX VMIN ISOURCE ISINK 1 2 3 4 5 6 RMPIN+ RMPINHOTSET VRHOT ISHARE SCOMP 20V 20V 20V 20V 20V 20V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V 1mA 1mA 1mA 1mA 5mA 1mA 1mA 1mA 1mA 30mA 5mA 1mA 7 8 9 10 11 EAIN PWMRMP LGND VCC VCCL 20V 20V n/a 24V 27V -0.3V -0.3V n/a -0.3V -0.3V 1mA 1mA 50mA n/a n/a 1mA 20mA n/a 50mA 3A for 100ns, 200mA DC 12 GATEL 27V -0.3V DC, -2V for 100ns 3A for 100ns, 200mA DC 3A for 100ns, 200mA DC 13 PGND 0.3V -0.3V n/a 14 GATEH 27V -0.3V DC, -2V for 100ns 3A for 100ns, 200mA DC 3A for 100ns, 200mA DC 15 VCCH 27V -0.3V n/a 16 17 CSIN+ CSIN- 20V 20V -0.3V -0.3V 1mA 1mA 3A for 100ns, 200mA DC 1mA 1mA 18 19 20 PHSFLT DACIN BIASIN 20V 20V 20V -0.3V -0.3V -0.3V 1mA 1mA 1mA 20mA 1mA 1mA Page 2 of 15 3A for 100ns, 200mA DC 9/1/03 IR3086 ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over: 8.4V ≤ VCC ≤ 14V, 6V ≤ VCCH ≤ 25V, 6V ≤ VCCL ≤ 14V, and 0 oC ≤ TJ ≤ 125 oC, CGATEH = 3.3nF, CGATEL = 6.8nF PARAMETER Gate Drivers GATEH Rise Time GATEH Fall Time GATEL Rise Time GATEL Fall Time GATEL low to GATEH high delay GATEH low to GATEL high delay Disable Pull-Down Current Current Sense Amplifier CSIN+ Bias Current CSIN- Bias Current Input Offset Voltage Gain at TJ = 25 oC Gain at TJ = 125 oC Slew Rate Differential Input Range Common Mode Input Range Rout at TJ = 25 oC Rout at TJ = 125 oC Ramp Discharge Clamp Clamp Voltage Clamp Discharge Current Ramp Comparator Input Offset Voltage Hysteresis RMPIN+, RMPIN- Bias Current Propagation Delay Page 3 of 15 TEST CONDITION VCCH = 12V, Measure 2V to 9V transition time VCCH = 12V, Measure 9V to 2V transition time VCCL = 12V, Measure 2V to 9V transition time VCCL = 12V, Measure 9V to 2V transition time VCCH = VCCL = 12V, Measure the time from GATEL falling to 1V to GATEH rising to 1V VCCH = VCCL = 12V, Measure the time from GATEH falling to 1V to GATEL rising to 1V Force GATH or GATEL = 2V with BIASIN = 0V CSIN+ = CSIN- = DACIN. Measure input referred offset from DACIN MIN TYP MAX UNIT 22 50 ns 22 50 ns 50 75 ns 50 75 ns 10 25 50 ns 10 25 50 ns 15 25 40 µA -0.5 -1 -3 -0.25 -0.4 0.5 0 0 5 µA µA mV 32 27 34 29 12.5 36 31 V/V V/V V/µs mV V kΩ kΩ mV Current Sense Amp output is an internal node. Slew rate at the ISHARE pin will be set by the internal 10kΩ resistor and any stray external capacitance Force I(PWMRMP) = 500µA. Measure V(PWMRMP) – V(DACIN) Note 1 VCCH = 12V. Measure time from RMPIN input (50mV overdrive) to GATEL transition to <11V. -20 0 7.9 9.3 10.5 12.4 100 4 13.1 15.5 -10 5 20 4 8 20 -10 -1 40 0 -0.5 80 10 1 mV mV µA 100 150 240 ns mA 9/1/03 IR3086 PARAMETER PWM Comparator PWM Comparator Input Offset Voltage EAIN & PWMRMP Bias Current Propagation Delay Common Mode Input Range Share Adjust Error Amplifier Input Offset Voltage Input Voltage Range PWMRMP Adjust Current Transconductance SCOMP Source/Sink Current SCOMP Activation Voltage PWMRMP Min Voltage 0% Duty Cycle Comparator Threshold Voltage Propagation Delay OVP Comparator Threshold Voltage Propagation Delay Phase Fault Comparator Threshold Voltage Output Voltage PHSFLT Leakage Current VRHOT Comparator HOTSET Bias Current Output Voltage VRHOT Leakage Current Threshold Hysteresis Threshold Voltage Page 4 of 15 TEST CONDITION Clamp and Current Share Adjust OFF MIN TYP MAX UNIT -5 5 15 mV -1 -0.4 1 µA 70 150 ns 5 V 30 3.5 mV V mA A/V VCCH = 12V. Measure time from PWMRMP input (50mV overdrive) to GATEH transition to < 11V. Exceeding the Common Mode input range results in 100% duty cycle 10 -3.5 4 0.9 20 60 8 1.6 30 150 2.3 40 300 150 225 350 mV Compare to V(DACIN) VCCL = 12V. Measure time from EAIN < 0.9 x V(DACIN) (200mV overdrive) to GATEL transition to < 11V. Note 1. 88 91 100 94 150 % ns Compare to V(DACIN) VCCL = 12V. Measure time from CSIN > V(DACIN) (200mV overdrive) to GATEL transition to <11V. 100 125 150 160 250 mV ns Compare to V(DACIN) I(PHSFLT) = 4mA V(PHSFLT) = 5.5V 88 91 300 0 94 400 10 % mV µA -2 -0.5 150 0 7.0 1 400 10 9.0 MAX 4.73mV/ oC x TJ + 1.356V µA mV EAIN – PWMRMP, Note 1 I(PWMRMP) = 3.5mA, Note 1 Note 1 Amount SCOMP must increase from its minimum voltage until the Ramp Slope Adjust current equals = 10µA I(PWMRMP) = 500µA I(VRHOT) = 29mA V(VRHOT) = 5.5V TJ ≥ 85 oC TJ ≥ 85 oC MIN 4.73mV/ oC x TJ + 1.176V 3.0 TYP 4.73mV/ oC x TJ + 1.241V 20 9/1/03 µA mV µA o C V IR3086 PARAMETER General VCC Supply Current VCCL Supply Current VCCH Supply Current TEST CONDITION MIN TYP MAX UNIT -5 -2 10 2.5 5.5 6.5 -2.5 -0.5 14 5 8 10 2 1 mA mA mA mA µA µA 6V ≤ VCCH ≤ 14V 14V ≤ VCCH ≤ 25V BIASIN Bias Current DACIN Bias Current Note 1: Guaranteed by design, but not tested in production PIN DESCRIPTION PIN# 1 2 3 PIN SYMBOL RMPIN+ RMPINHOTSET 4 VRHOT 5 ISHARE 6 SCOMP 7 EAIN 8 PWMRMP 9 10 11 12 13 14 15 16 17 LGND VCC VCCL GATEL PGND GATEH VCCH CSIN+ CSIN- 18 PHSFLT 19 DACIN 20 BIASIN Page 5 of 15 PIN DESCRIPTION Non-inverting input to Ramp Comparator Inverting input to Ramp Comparator Inverting input to VRHOT comparator. Connect resistor divider from VBIAS to LGND to program VRHOT threshold. Diode or thermistor may be substituted for lower resistor for enhanced/remote temperature sensing. Open Collector output of the VRHOT comparator which drives low if IC junction temperature exceeds the user programmable limit. Connect external pull-up. Output of the Current Sense Amplifier and input to the Share Adjust Error Amplifier. Voltage on this pin is equal to V(DACIN) + 34 [V(CSIN+) – V(CSIN-)]. Connecting ISHARE pins creates a Share Bus enabling current sharing between Phase ICs. The Share bus is also used by the Control IC for voltage positioning and OverCurrent protection. Compensation for the Current Share control loop. Connect a capacitor to ground to set the control loop’s bandwidth. PWM comparator input from the Control IC. Both Gate Driver outputs drive low if the voltage on this pin is less than 91% of V(DACIN). PWM comparator ramp input. Connect a resistor from this pin to the converter input voltage and a capacitor to LGND to program the PWM ramp. Signal ground and IC substrate connection Power for internal circuitry Power for Low-Side Gate Driver Low-Side Gate Driver Output and input to GATEH non-overlap comparator Return for Gate Drivers High-Side Gate Driver Output and input to GATEL non-overlap comparator Power for High-Side Gate Driver Non-inverting input to the Current Sense Amplifier Inverting input to the Current Sense Amplifier and non-inverting input to the OVP comparator Open Collector output of the Phase Fault comparator. Drives low if Phase current is unable to match the level of the SHARE bus due to an external fault. Connect external pull-up. Reference voltage input from the Control IC and inverting input to the OVP comparator. Current sensing and PWM operation referenced to this pin. System reference voltage for internal circuitry 9/1/03 IR3086 SYSTEM THEORY OF OPERATION XPhaseTM Architecture The XPhaseTM architecture is designed for multiphase interleaved buck converters which are used in applications requiring small size, design flexibility, low voltage, high current and fast transient response. The architecture can be used in any multiphase converter ranging from 1 to 16 or more phases where flexibility facilitates the design trade-off of multiphase converters. The scalable architecture can be applied to other applications which require high current or multiple output voltages. As shown in Figure 1, the XPhaseTM architecture consists of a Control IC and a scalable array of phase converters each using a single Phase IC. The Control IC communicates with the Phase ICs through a 5-wire analog bus, i.e. bias voltage, phase timing, average current, error amplifier output, and VID voltage. The Control IC incorporates all the system functions, i.e. VID, PWM ramp oscillator, error amplifier, bias voltage, and fault protections etc. The Phase IC implements the functions required by the converter of each phase, i.e. the gate drivers, PWM comparator and latch, over-voltage protection, and current sensing and sharing. There is no unused or redundant silicon with the XPhaseTM architecture compared to others such as a 4 phase controller that can be configured for 2, 3, or 4 phase operation. PCB Layout is easier since the 5 wire bus eliminates the need for point-to-point wiring between the Control IC and each Phase. The critical gate drive and current sense connections are short and local to the Phase ICs. This improves the PCB layout by lowering the parasitic inductance of the gate drive circuits and reducing the noise of the current sense signal. POWER GOOD PHASE FAULT VR HOT 12V ENABLE VID5 VID0 VID1 IR3081 CONTROL IC PHASE FAULT CIN >> BIAS VOLTAGE VOUT SENSE+ >> PHASE TIMING VID2 << CURRENT SENSE VID3 >> PWM CONTROL CURRENT SHARE >> VID VOLTAGE VID4 IR3086 PHASE IC VOUT+ 0.1uF COUT VOUT- PHASE HOT CCS RCS VOUT SENSE- PHASE FAULT CURRENT SHARE IR3086 PHASE IC 0.1uF PHASE HOT CCS CONTROL BUS RCS ADDITIONAL PHASES INPUT/OUTPUT Figure 1 – System Block Diagram Page 6 of 15 9/1/03 IR3086 PWM Control Method The PWM block diagram of the XPhaseTM architecture is shown in Figure 2. Feed-forward voltage mode control with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used for the voltage control loop. An external RC circuit connected to the input voltage and ground is used to program the slope of the PWM ramp and to provide the feed-forward control at each phase. The PWM ramp slope will change with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change due to variations in the silver box output voltage or due to drops in the PCB related to changes in load current. VIN CONTROL IC PHASE IC SYSTEM REFERENCE VOLTAGE BIASIN RAMP GENERATOR RMPOUT RAMPIN+ - VVALLEY RRAMP1 PWM LATCH CLOCK PULSE GENERATOR RAMPIN- PWM COMPARATOR - VBIAS PWMRMP RPWMRMP X 0.91 + - + + - ISHARE CURRENT SENSE AMP 20mV 10K - X34 RDRP VDRP AMP VOSNS- - + IROSC GND O% DUTY CYCLE COMPARATOR - + RVFB FB IFB SHARE ADJUST ERROR AMP CSCOMP ERROR AMP RAMP DISCHARGE CLAMP SCOMP CPWMRMP EAOUT RAMP SLOPE ADJUST CSIN+ + VOSNSVDAC GATEL + ENABLE - - EAIN VOUT COUT RRAMP2 VDAC VBIAS REGULATOR VOSNS+ RESET DOMINANT R + + GATEH S - VPEAK + 50% DUTY CYCLE CCS RCS CCS RCS CSIN- DACIN VDRP + - IIN PHASE IC SYSTEM REFERENCE VOLTAGE BIASIN RAMPIN+ + RRAMP1 PWM LATCH CLOCK PULSE GENERATOR RAMPIN- GATEH S PWM COMPARATOR - EAIN RESET DOMINANT R GATEL + RRAMP2 20mV - CURRENT SENSE AMP X34 - + + ISHARE 10K X 0.91 - SHARE ADJUST ERROR AMP CSIN+ + SCOMP CSCOMP O% DUTY CYCLE COMPARATOR - RAMP DISCHARGE CLAMP + CPWMRMP RAMP SLOPE ADJUST - RPWMRMP ENABLE + PWMRMP CSIN- DACIN Figure 2 – PWM Block Diagram Frequency and Phase Timing Control An oscillator with programmable frequency is located in the Control IC. The output of the oscillator is a 50% duty cycle triangle waveform with peak and valley voltages of approximately 5V and 1V. This signal is used to program both the switching frequency and phase timing of the Phase ICs. The Phase IC is programmed by resistor divider RRAMP1 and RRAMP2 connected between the VBIAS reference voltage and the Phase IC LGND pin. A comparator in the Phase ICs detects the crossing of the oscillator waveform with the voltage generated by the resistor divider and triggers a clock pulse that starts the PWM cycle. The peak and valley voltages track the VBIAS voltage reducing potential Phase IC timing errors. Figure 3 shows the Phase timing for an 8 phase converter. Note that both slopes of the triangle waveform can be used for synchronization by swapping the RAMP + and – pins. Page 7 of 15 9/1/03 IR3086 50% RAMP DUTY CYCLE RAMP (FROM CONTROL IC) SLOPE = 80mV / % DC VPEAK (5.0V) VPHASE4&5 (4.5V) SLOPE = 1.6mV / ns @ 200kHz SLOPE = 8.0mV / ns @ 1MHz VPHASE3&6 (3.5V) VPHASE2&7 (2.5V) VPHASE1&8 (1.5V) VVALLEY (1.00V) CLK1 PHASE IC CLOCK PULSES CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 Figure 3 – 8 Phase Oscillator Waveforms PWM Operation The PWM comparator is located in the Phase IC. Upon receiving a clock pulse, the PWM latch is set, the PWMRMP voltage begins to increase, the low side driver is turned off, and the high side driver is then turned on. When the PWMRMP voltage exceeds the Error Amp’s output voltage the PWM latch is reset. This turns off the high side driver, turns on the low side driver, and activates the Ramp Discharge Clamp. The clamp quickly discharges the PWMRMP capacitor to the VDAC voltage of the Control IC until the next clock pulse. The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. An Error Amp output voltage greater than the common mode input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement guarantees the Error Amp is always in control and can demand 0 to 100% duty cycle as required. It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of most systems. The inductor current will increase much more rapidly than decrease in response to load transients. This control method is designed to provide “single cycle transient response” where the inductor current changes in response to load transients within a single switching cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. An additional advantage is that differences in ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC. Page 8 of 15 9/1/03 IR3086 Body BrakingTM In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; TSLEW = [L x (IMAX - IMIN)] / Vout The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout + VBODY DIODE. The minimum time required to reduce the current in the inductor in response to a load transient decrease is now; TSLEW = [L x (IMAX - IMIN)] / (Vout + VBODY DIODE) Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be increased by 2X or more. This patent pending technique is referred to as “body braking” and is accomplished through the “0% Duty Cycle Comparator” located in the Phase IC. If the Error Amp’s output voltage drops below 91% of the VDAC voltage this comparator turns off the low side gate driver. Figure 4 depicts PWM operating waveforms under various conditions PHASE IC CLOCK PULSE EAIN PWMRMP VDAC 91% VDAC GATEH GATEL STEADY-STATE OPERATION DUTY CYCLE INCREASE DUE TO LOAD INCREASE DUTY CYCLE DECREASE DUE TO VIN INCREASE (FEED-FORWARD) DUTY CYCLE DECREASE DUE TO LOAD DECREASE (BODY BRAKING) OR FAULT (VCC UV, VCCVID UV, OCP, VID=11111X) STEADY-STATE OPERATION Figure 4 – PWM Operating Waveforms Lossless Average Inductor Current Sensing Inductor current can be sensed by connecting a resistor and a capacitor in parallel with the inductor and measuring the voltage across the capacitor. The equation of the sensing network is, vC ( s ) = v L ( s ) R + sL 1 = iL (s) L 1 + sRS C S 1 + sRS C S Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time constant of the inductor which is the inductance L over the inductor DCR. If the two time constants match, the voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of inductor DC current, but affects the AC component of the inductor current. Page 9 of 15 9/1/03 IR3086 The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in series with inductor, this is the only sense method that can support a single cycle transient response. Other methods provide no information during either load increase (low side sensing) or load decrease (high side sensing). An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional sources of peak-to-average errors. Current Sense Amplifier A high speed differential current sense amplifier is located in the Phase IC, as shown in figure 5. Its gain decreases with increasing temperature and is nominally 34 at 25ºC and 29 at 125ºC (-1470 ppm/ºC). This reduction of gain tends to compensate the 3850 ppm/ºC increase in inductor DCR. Since in most designs the Phase IC junction is hotter than the inductor these two effects tend to cancel such that no additional temperature compensation of the load line is required. The current sense amplifier can accept positive differential input up to 100mV and negative up to -20mV before clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the Control IC and other Phases through an on-chip 10KΩ resistor connected to the ISHARE pin. The ISHARE pins of all the phases are tied together and the voltage on the share bus represents the total current being delivered to the load and is used by the Control IC for voltage positioning and current limit protection. vL iL CSA L RL Rs Cs Vo Co vc CO Figure 5 – Inductor Current Sensing and Current Sense Amplifier Average Current Share Loop Current sharing between phases of the converter is achieved by the average current share loop in each Phase IC. The output of the current sense amplifier is compared with the share bus less a 20mV offset. If current in a phase is smaller than the average current, the share adjust error amplifier of the phase will activate a current source that reduces the slope of its PWM ramp thereby increasing its duty cycle and output current. The crossover frequency of the current share loop can be programmed with a capacitor at the SCOMP pin so that the share loop does not interact with the output voltage loop. Page 10 of 15 9/1/03 IR3086 IR3086 THEORY OF OPERATION Block Diagram The Block diagram of the IR3086 is shown in figure 6 and specific features discussed in the following section. RAMP COMPARATOR S PWM COMPARATOR - EAIN GATEH RESET DOMINANT - - R + SYSTEM REFERENCE VOLTAGE BIASIN VCCH + GATE NON-OVERLAP COMPARATORS ENABLE + + PWMRMP - RAMP DISCHARGE CLAMP - RAMP SLOPE ADJUST 2V - + RMPIN- PWM LATCH CLOCK PULSE GENERATOR + RMPIN+ VCCL GATEL + - SCOMP X 0.91 0% DUTY CYCLE COMPARATOR + + - + X34 VRHOT COMPARATOR DACIN CURRENT SENSE AMP CSIN+ - + - HOTSET + CSINPHSFLT + VRHOT VCC 20mV LGND 130mV INTERNAL CIRCUIT BIAS + 10K + + - VOLTAGE PROPORTIONAL TO ABSOLUTE TEMPERATURE - ISHARE PGND - OVP COMPARATOR - + SHARE ADJUST ERROR AMP FAULT COMPARATOR Figure 6 – IR3086 Block Diagram Tri-State Gate Drivers The gate drivers can deliver up to 3A peak current. An adaptive non-overlap circuit monitors the voltage on the GATEH and GATEL pins to prevent MOSFET shoot-through current while minimizing body diode conduction. An Enable signal is provided by the Control IC to the Phase IC without the additional of a dedicated signal line. The Error Amplifier output of the Control IC drives low in response to any fault condition such as input under voltage or output overload. The IR3086 0% duty cycle comparator detects this and drives both gate outputs low. This tri-state operation prevents negative inductor current and negative output voltage during power-down. The Gate Drivers revert to a high impedance “off” state at VCCL and VCCH supply voltages below the normal operating range. An 80kΩ resistor is connected across the GATEX and PGND pins to prevent the GATEX voltage from rising due to leakage or other cause under these conditions. Page 11 of 15 9/1/03 IR3086 Over Voltage Protection (OVP) The IR3086 includes over-voltage protection that turns on the low side MOSFET to protect the load in the event of a shorted high-side MOSFET or connection of the converter output to an excessive output voltage. A comparator monitors the voltage at the CSIN- pin which is usually connected directly to the converter output. If the voltage exceeds the DACIN voltage plus 130mV the GATEL pin drives high. The OVP circuit over-rides the normal PWM operation and will fully turn-on the low side MOSFET within approximately 150ns. The low side MOSFET will remain ON until the over-voltage condition ceases. When designing for OVP the overall system must be considered. In many cases the over-current protection of the ACDC or DC-DC converter supplying the multiphase converter will be triggered thus providing effective protection without damage as long as all PCB traces and components are sized to handle the worst-case maximum current. If this is not possible a fuse can be added in the input supply to the multiphase converter. One scenario to be careful of is where the input voltage to the multiphase converter may be pulled below the level where the ICs can provide adequate voltage to the low side MOSFET thus defeating OVP. Dynamic changes in the VID code to a lower output voltage may trigger OVP. For example; a 250mV decrease in output voltage combined with a light load condition will cause the low side MOSFETs to turn on and interfere with Body BrakingTM. This will not cause a problem however as Body BrakingTM will resume once the output voltage is less than 130mV above the VID voltage. Excessive distribution impedance between the converter and load or programming of the converter output voltage above the VID voltage may trigger OVP during normal operation. If the voltage dropped across the distribution impedance exceeds the minimum OVP comparator threshold of 100mV plus any voltage positioning the IR3086 can not be used. For example; a converter having 25mV of VID offset, 125mV of AVP at full load, and 75mV of drop in the distribution path at full load would be OK since 100mV + 25mV + 125mV = 250mV which is greater than 75mV. The IR3088 Phase IC without OVP should be used in applications with excessive distribution impedance. Thermal Monitoring (VRHOT) The IR3086 senses its own die temperature and produces a voltage at the input of the VRHOT comparator that is proportional to temperature. An external resistor divider connected from VBIAS to the HOTSET pin and ground can be used to program the thermal trip point of the VRHOT comparator. The VRHOT pin is an open-collector output and should be pulled up to a voltage source through a resistor. If the thermal trip point is reached the VRHOT output drives low. Phase Fault Its possible for multiphase converters to appear to be working correctly with one or more phases not functioning. The output voltage can still be regulated and the full load current may still be delivered. However, the remaining phase(s) will be stressed far beyond their intended design limits and are likely to fail. Loss of a phase can occur due to poor solder connections or mounting during the manufacturing process, or can occur in the field. The most common failure mode of a buck converter is failure of the high side MOSFET. Page 12 of 15 9/1/03 IR3086 The IR3086 has the ability to detect if a phase stops switching and can provide this information to the system through the PHSFLT output pin. If a phase stops switching its output current will drop to zero and the output of its IR3086 current sense amp will be the DACIN voltage. The Share Adjust Amplifier reacts to this by increasing the Ramp Slope Adjust current until it exceeds the externally programmable PWM Ramp bias current. This will cause the voltage at the PWMRMP pin to drop below its normal operating range. The Fault Comparator trips and drives the PHSFLT output to ground when the voltage on the PWMRMP pin falls below 91% of the DACIN voltage. PHSFLT is an open-collector output and should be pulled up to a voltage source through a resistor. APPLICATIONS INFORMATION POWERGOOD VRHOT PHASE FAULT 12V RCS- 10 CCS+ CIN CCS- 18 19 20 16 CSIN+ CSIN- DACIN BIASIN VCCL VOUT SENSE+ 15 14 13 VOUT+ 12 DISTRIBUTION IMPEDANCE 11 COUT VOUTVCC LGND PWMRMP EAIN GATEL 10 6 SCOMP RPHASE2 PGND 0.1uF 10 VOUT SENSE- RPWMRMP 0.1uF RVDRP 19 RCS- 18 CCS+ CCS- 18 16 CSIN+ CSIN- 0.1uF VRHOT ISHARE SCOMP 6 CSCOMP GATEH PGND GATEL VCCL 15 14 13 12 11 VCC HOTSET RPHASE2 RPHASE3 19 IR3086 PHASE IC RMPIN- LGND 4 RCS+ VCCH 10 RSHARE 5 CVDAC DACIN 20 3 RVDAC PHSFLT BIASIN 2 RMPIN+ PWMRMP 1 EAIN RVDRP 17 RBIASIN 15 14 13 8 CSCOMP GATEH 16 ROCSET ROSC ISHARE 9 OCSET 0.1uF 17 VDAC VID4 ROSC IIN TRM4 VID3 20 VRHOT 7 FB VDRP RPHASE3 24 22 EAOUT 21 HOTSET CPWMRMP 8 VID2 RVFB VCC 26 25 23 LGND RMPOUT N/C SS/DEL PWRGD BBFB VID1 12 7 ENABLE 28 VID4 RVFB VBIAS IR3081 CONTROL IC VID0 5 RCS+ VCCH IR3086 PHASE IC RMPIN- RPHASE1 CSS/DEL 4 0.1uF VID5 TRM3 VID3 6 VOSNS- 5 TRM2 4 VID2 TRM1 3 VID1 9 VID0 OSCDS 11 VID5 2 10 1 27 ENABLE RMPIN+ 9 3 7 RSS/DEL 2 CPWMRMP 8 1 PHSFLT RPHASE1 0.1uF 17 RBIASIN 0.1uF 10 RPWMRMP 0.1uF RCS- CCS+ CCS- 16 0.1uF CSIN+ CSIN- 19 18 20 CSCOMP GATEH PGND GATEL 15 14 13 12 11 VCC LGND VCCL 10 SCOMP EAIN ISHARE 6 RPHASE3 DACIN BIASIN VRHOT PWMRMP HOTSET RPHASE2 5 IR3086 PHASE IC RMPIN- 9 4 RCS+ VCCH 7 3 RMPIN+ CPWMRMP 8 2 PHSFLT RPHASE1 1 17 RBIASIN 0.1uF 10 RPWMRMP 0.1uF RCS- CCS+ CCS- 16 0.1uF CSIN+ CSIN- 18 19 20 CSCOMP GATEH PGND GATEL 15 14 13 12 11 VCC VCCL LGND SCOMP EAIN ISHARE 10 VRHOT 6 RPHASE3 DACIN BIASIN HOTSET PWMRMP IR3086 PHASE IC RMPIN- RPHASE2 5 9 4 RCS+ VCCH 7 3 RMPIN+ CPWMRMP 8 2 PHSFLT RPHASE1 1 17 RBIASIN 0.1uF 10 RPWMRMP 0.1uF RCS- CCS+ CCS- 16 GATEH PGND GATEL 15 14 13 12 11 VCC LGND VCCL 10 SCOMP EAIN ISHARE CSCOMP 0.1uF CSIN+ CSIN- 19 18 20 VRHOT 6 RPHASE3 DACIN BIASIN HOTSET PWMRMP IR3086 PHASE IC RMPIN- RPHASE2 5 9 4 RCS+ VCCH 7 3 RMPIN+ CPWMRMP 8 2 PHSFLT RPHASE1 1 17 RBIASIN 0.1uF 10 RPWMRMP 0.1uF Figure 7 – 5 Phase IR3081/3086 EVRD10 Converter Page 13 of 15 9/1/03 IR3086 LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. • Dedicate at least one middle layer for a ground plane, which is then split into signal ground plane (LGND) and power ground plane (PGND). • Connect PGND to LGND pins of each phase IC to the ground tab under it. • In order to reduce the noise coupled to SCOMP pin of phase ICs, use a dedicated wire to connect the capacitor CSCOMP to LGND pin, but connect PWM ramp capacitor CPWMRMP, phase delay programming resistor RRAMP2, decoupling capacitor CVCC to LGND plane through vias. Connect the decoupling capacitor low side gate driver CVCCL and the ground tab under the phase IC to PGND plane through vias. • • Place the decoupling capacitor CVCC as close as possible to VCC pin of the control IC, and place the decoupling capacitors CVCC and CVCCL as close as possible to VCC and VCCL pins of the phase IC respectively. • Bus signals should not cross over the fast transition nodes, such as switching nodes and gate drive output. • Use Kelvin connections for the current sense signals, and use the ground plane to shield the current sense traces. • Place the phase ICs as close as possible to the MOSFETs to reduce the parasitic resistance and inductance of the gate drive paths. • Place the input capacitors close to the drain of top MOSFET and the source of bottom MOSFET. Replace the bigger-package ceramic capacitors with multiple smaller-package ones to reduce the parasitic inductance. • There are two switching power loops. One loop includes the input capacitors, top MOSFET, inductor, output capacitors and the load; another loop consists of bottom MOSFET, inductor, output capacitors and the load. Route the switching power paths using wide and short traces or polygons; use multiple vias for connections between layers. LGND PLANE DACIN RBIASIN DVCCH BIASIN EAIN PHSFLT or OPTIPHS VCCH RCS1 CCS1 CVCCH GATEH CSIN+ PGND CSIN- VCC GATEL LGND VCCL CVCCL To PGND Plane RRAMP1 RRAMP2 SCOMP PWMRMP CVCC To Gate Drive Voltage RMPIN+ RMPIN- VRHOT HOTSET ISHARE EAIN CPWMRMP CSCOMP To LGND Plane To LGND Plane To LGND Plane RPWMRMP To VIN To Signal Bus RCS2 CCS2 To MOSFETs PGND PLANE To To Inductor Switching Current Sensing Node Figure 8 - Layout of Phase IC Components Page 14 of 15 9/1/03 IR3086 PACKAGE INFORMATION 20L MLPQ (4 x 4 mm Body) – θJA = 32oC/W, θJC = 3oC/W 4.40 – 5.00 4.00 2.90 1.20 2.15 Holes: Φ0.3-0.33 0.23 2.15 2.90 4.00 4.40 - 5.00 0.50 0.75-1.05 Note: All dimensions are in Millimeters. Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. www.irf.com Page 15 of 15 9/1/03