SEMICONDUCTOR TECHNICAL DATA The MC10231 is a dual master–slave type D flip–flop. Asynchronous Set (S) and Reset (R) override Clock (CC) and Clock Enable (CE) inputs. Each flip–flop may be clocked separately by holding the common clock in the low state and using the enable inputs for the clocking function. If the common clock is to be used to clock the flip–flop, the Clock Enable inputs must be in the low state. In this case, the enable inputs perform the function of controlling the common clock. The output states of the flip–flop change on the positive transition of the clock. A change in the information present at the data (D) input will not affect the output information at any other time due to master–slave construction. L SUFFIX CERAMIC PACKAGE CASE 620–10 P SUFFIX PLASTIC PACKAGE CASE 648–08 FN SUFFIX PLCC CASE 775–02 PD = 270 mW typ/pkg (No Load) tpd = 2 ns typ tTog= 225 MHz typ tr, tf = 2.0 ns typ (20%–80%) DIP PIN ASSIGNMENT LOGIC DIAGRAM S1 5 D1 7 CE1 6 Q1 2 Q1 3 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 R1 4 CC 9 R2 13 CE2 11 D2 10 1 16 VCC2 Q1 2 15 Q2 Q1 3 14 Q2 R1 4 13 R2 S1 5 12 S2 CE1 6 11 CE2 Q2 15 D1 7 10 D2 Q2 14 VEE 8 9 CC S2 12 Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6–11 of the Motorola MECL Data Book (DL122/D). CLOCKED TRUTH TABLE R–S TRUTH TABLE C D Qn+1 R S Qn+1 L X Qn L L Qn H L L L H H H H H H L L C = CE + CC. A clock H is a clock transition from a low to a high state. H H N.D. N.D. = Not Defined 3/93 Motorola, Inc. 1996 VCC1 3–202 REV 5 MC10231 ELECTRICAL CHARACTERISTICS Test Limits Characteristic Power Supply Drain Current Input Current Symbol Pin Pi Under Test IE 8 72 IinH 4 5 6 7 9 650 650 350 350 460 IinL 4, 5* 6, 7, 9* –30°C Min +25°C Max Min +85°C Max Unit 65 72 mAdc 410 410 220 220 290 410 410 220 220 290 µAdc Typ Max 52 Min µAdc 0.5 0.5 Output Voltage Logic 1 VOH 2 2[ –1.060 –1.060 –0.890 –0.890 –0.960 –0.960 –0.810 –0.810 –0.890 –0.890 –0.700 –0.700 Vdc Output Voltage Logic 0 VOL 3 3[ –1.890 –1.890 –1.675 –1.675 –1.850 –1.850 –1.650 –1.650 –1.825 –1.825 –1.615 –1.615 Vdc Threshold Voltage Logic 1 VOHA 2 2[ –1.080 –1.080 Threshold Voltage Logic 0 VOLA 3 3[ Switching Times Clock Input –0.980 –0.980 –0.910 –0.910 –1.655 –1.655 –1.630 –1.630 Vdc –1.595 –1.595 (50Ω Load) Propagation Delay Vdc ns t9+2– t6+2+ 2 2 1.5 1.5 3.4 3.4 1.5 1.5 2.0 2.0 3.3 3.3 1.6 1.6 3.7 3.7 Rise Time (20 to 80%) t2+ 2 0.9 3.3 1.0 1.3 3.1 1.0 3.6 Fall Time (20 to 80%) t2– 2 0.9 3.3 1.0 1.3 3.1 1.0 3.6 Set Input ns Propagation Delay t5+2+ t12+15+ t5+3– t12+14– 2 15 3 14 1.1 1.1 1.1 1.1 3.4 3.4 3.4 3.4 1.1 1.1 1.1 1.1 2.0 2.0 2.0 2.0 3.3 3.3 3.3 3.3 1.2 1.2 1.2 1.2 3.7 3.7 3.7 3.7 Reset Input ns Propagation Delay t4+2– t13+15– t4+3– t13+14+ 2 15 3 14 1.1 1.1 1.1 1.1 3.4 3.4 3.4 3.4 Setup Time tsetup 7 1.5 1.0 1.5 ns Hold Time thold 7 0.9 0.75 0.9 ns ftog 2 200 * Individually test each input; apply VILmin to pin under test. 200 200 MHz Toggle Frequency (Max) 1.1 1.1 1.1 1.1 [ Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6) MECL Data DL122 — Rev 6 3–203 2.0 2.0 2.0 2.0 3.3 3.3 3.3 3.3 225 1.2 1.2 1.2 1.2 3.7 3.7 3.7 3.7 VIHmax VILmin MOTOROLA MC10231 ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) Characteristic Power Supply Drain Current Input Current @ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE –30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2 Symbol Pin Under Test IE 8 IinH 4 5 6 7 9 IinL 4, 5* 6, 7, 9* TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin VIHAmin VILAmax 4 5 6 7 9 * * VEE (VCC) Gnd 8 1, 16 8 8 8 8 8 1, 16 1, 16 1, 16 1, 16 1, 16 8 8 1, 16 1, 16 Output Voltage Logic 1 VOH 2 2[ 5 7 8 8 1, 16 1, 16 Output Voltage Logic 0 VOL 3 3[ 5 7 8 8 1, 16 1, 16 Threshold Voltage Logic 1 VOHA 2 2[ 5 7 9 8 8 1, 16 1, 16 VOLA 3 3[ 5 7 9 8 8 1, 16 1, 16 +1.11Vdc Pulse In Pulse Out –3.2 V +2.0 V t9+2– t6+2+ 2 2 7 9 6 2 2 8 8 1, 16 1, 16 7 9 2 8 1, 16 9 2 8 1, 16 5 12 5 12 2 15 3 14 8 8 8 8 1, 16 1, 16 1, 16 1, 16 4 13 4 13 2 15 3 14 8 8 8 8 1, 16 1, 16 1, 16 1, 16 Threshold Voltage Logic 0 Switching Times Clock Input (50Ω Load) Propagation Delay Rise Time (20 to 80%) t2+ 2 Fall Time (20 to 80%) t2– 2 t5+2+ t12+15+ t5+3– t12+14– 2 15 3 14 t4+2– t13+15– t4+3– t13+14+ 2 15 3 14 Setup Time tsetup 7 6, 7 2 8 1, 16 Hold Time thold 7 6, 7 2 8 1, 16 6 2 8 1, 16 Set Input Propagation Delay 6 9 Reset Input Propagation Delay 6 9 Toggle Frequency (Max) ftog 2 * * * Individually test each input applying VIH or VIL to input under test. [ Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6) VIHmax VILmin Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. MOTOROLA 3–204 MECL Data DL122 — Rev 6 MC10231 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PLCC PACKAGE CASE 775–02 ISSUE C 0.007 (0.180) M T L–M B Y BRK –N– U N S 0.007 (0.180) M T L–M S S N S D –L– –M– Z W 20 D 1 V 0.010 (0.250) G1 X S T L–M S N S VIEW D–D A 0.007 (0.180) M T L–M S N S R 0.007 (0.180) M T L–M S N S Z C H –T– SEATING PLANE F VIEW S G1 0.010 (0.250) S T L–M S 0.007 (0.180) M T L–M S N S VIEW S S N S NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). MECL Data DL122 — Rev 6 N K 0.004 (0.100) J S K1 E G 0.007 (0.180) M T L–M 3–205 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2_ 10 _ 0.310 0.330 0.040 ––– MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2_ 10 _ 7.88 8.38 1.02 ––– MOTOROLA MC10231 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M –A– 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R 16 S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 T A M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 Mfax: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 ◊ MOTOROLA 3–206 *MC10231/D* MC10231/D MECL Data DL122 — Rev 6