CXA2069Q S2-Compatible 7-Input 3-Output Audio/Video Switch Description The CXA2069Q is a 7-input, 3-output audio/video switch featuring I2C bus compatibility for TVs. This IC has input pins that are compatible with S2 protocol. Features • 4 inputs that are compatible with S2 protocol • Serial control with I2C bus • 7 inputs, 3 outputs • The desired inputs can be selected independently for each of the 3 outputs • Wide band video amplifier (20 MHz, –3 dB) • Y/C MIX circuit • Slave address can be changed (90H/92H) • Audio muting from external pin • High impedance maintained by I2C bus lines (SDA, SCL) even when power is OFF • Wide audio dynamic range (3 Vrms typ.) Applications Audio/video switch featuring I2C bus compatibility for TVs 64 pin QFP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VCC 12 • Operating temperature Topr –20 to +75 • Storage temperature Tstg –65 to +150 • Allowable power dissipation PD 1300 Operating Conditions Supply voltage 9±0.5 V °C °C mW V Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E96Y05B81 CXA2069Q Block Diagram TV 63 V1 1 V2 8 V3 V4 V5 30 V6 60 53 VOUT1 15 49 YIN1 22 56 YOUT1 55 TRAP1 58 COUT1 51 CIN1 44 V/YOUT2 46 TRAP2 47 COUT2 41 VOUT3 39 YOUT3 6dB 6dB 6dB Y1 3 Y2 10 Y3 17 Y4 24 6dB 6dB 6dB C1 5 C2 12 C3 19 C4 26 6dB 6dB 37 COUT3 6dB 57 VGND BIAS 50 BIAS 42 VCC 35 AGND 6dB LTV 62 LV1 2 52 LOUT1 LV2 9 54 ROUT1 LV3 16 LV4 23 LV5 29 LV6 59 RTV 0dB 64 RV1 4 RV2 11 RV3 18 RV4 25 RV5 31 RV6 0dB 6dB 6dB 61 6dB Logic 6dB Audio system is attenuated by 6dB at input, and a total gain is 0dB (LOUT1 and ROUT1 can be changed to –6dB). 6dB —2— 43 LOUT2 45 ROUT2 38 LOUT3 40 ROUT3 36 DC OUT 33 SCL 34 SDA 32 ADR 7 S-1 14 S-2 21 S-3 28 S-4 6 S2-1 13 S2-2 20 S2-3 27 S2-4 48 MUTE 38 LOUT3 39 YOUT3 40 ROUT3 41 VOUT3 42 VCC 43 LOUT2 44 V/YOUT2 45 ROUT2 46 TRAP2 47 COUT2 48 MUTE 49 YIN1 50 BIAS 51 CIN1 S2-1 C1 RV1 Y1 64 LV1 2 V1 1 RTV 63 TV 62 LTV 61 RV6 60 V6 59 LV6 58 COUT1 3 4 5 6 7 8 9 11 10 12 13 14 15 16 17 18 S2-3 19 20 S-3 21 V4 22 LV4 23 Y4 24 RV4 25 C4 26 S2-4 27 LV2 57 VGND Y2 S-4 28 S-1 32 RV5 31 C3 —3— RV2 56 YOUT1 C2 LV5 29 S2-2 55 TRAP1 S-2 V5 30 RV3 54 ROUT1 53 VOUT1 CXA2069Q 37 COUT3 V3 ADR 36 DC OUT LV3 LOUT1 35 AGND Y3 52 33 34 SDA V2 SCL Pin Configuration CXA2069Q CXA2069Q Pin Description Pin No. Symbol 63 1 8 15 22 30 60 TV V1 V2 V3 V4 V5 V6 Pin voltage Equivalent circuit Description VCC 63 22 150 1 4.0 V Video signal inputs. Input composite video signals. 30 8 60 15 3µA VCC 3 3 10 17 24 49 Y1 Y2 Y3 Y4 YIN1 Y/C separation signal inputs. Input luminance signals. The YIN1 pin inputs the signal obtained by Y/C separating the VOUT1 pin output. 10 150 4.0 V 17 24 49 3µA VCC 5 5 12 19 26 51 C1 C2 C3 C4 CIN1 62, 2 9, 16 23, 29 59, 64 4, 11 18, 25 31, 61 LTV, LV1 LV2, LV3 LV4, LV5 LV6, RTV RV1, RV2 RV3, RV4 RV5, RV6 4.5 V Y/C separation signal inputs. Input chrominance signals. The CIN1 pin inputs the signal obtained by Y/C separating the VOUT1 pin output. 20k 12 19 150 26 27k 51 62 64 2 4 9 11 16 18 23 25 29 31 59 61 VCC 4.5 V 33k Audio signal inputs. 27k 15k VCC 250 VCC 53 41 VOUT1 VOUT3 3.9 V Video signal outputs. Output composite video signals. 30k 53 27k 41 —4— 23.5k CXA2069Q Pin No. Symbol Pin voltage Equivalent circuit VCC VCC 44 V/YOUT2 3.8 V YOUT1 VCC VCC Video signal output. Either composite video signal output or luminance signal output can be selected by I2C bus control. 44 VCC VCC 56 Description VCC VCC 3.3 V Video signal outputs. Output luminance signals. 56 39 39 YOUT3 3.8 V VCC VCC 58 47 37 COUT1 COUT2 COUT3 VCC VCC 58 4.5 V Video signal outputs. Output chrominance signals. 47 37 VCC 52 43 38 54 45 40 LOUT1 LOUT2 LOUT3 ROUT1 ROUT2 ROUT3 54 52 45 43 40 38 VCC 56 4.5V Audio signal outputs. Zo=50 Ω (within DC ±2 mA) 20k 20k VCC VCC VCC 6 6 13 20 27 S2-1 S2-2 S2-3 S2-4 13 — 20 27 147 100k —5— Detects the S2-compatible DC superimposed onto the C signal. 4 : 3 video signal at 1.3 V or less 4 : 3 letter-box signal at 1.3 V or more to 2.5 V or less 16 : 9 picture squeezed signal at 2.5 V or more This pin is pulled down to GND by a 100 kΩ resistor, so the 4 : 3 video signal is selected when open. CXA2069Q Pin No. Symbol Pin voltage Equivalent circuit 5V VCC VCC 7 14 21 28 S-1 S-2 S-3 S-4 7 Description VCC 50k 14 — 21 100k 50k 28 100k Composite video/S selector. The detection results are written to the status register. S signal at 3.5 V or less Composite video signal at 3.5 V or more This pin is pulled up to 5 V by a 100 kΩ resistor, so the composite video signal is selected when open. VCC 147 32 ADR — Selects the slave address for the I2C bus. 90H at 1.5 V or less 92H at 2.5 V or more 90H when open. 72k 32 28k VCC I2C bus signal input VILmax=1.5 V VIHmin=3.0 V 4k 33 SCL — 33 10.5k VCC 4k 34 SDA — 34 —6— I2C bus signal input VILmax=1.5 V VIHmin=3.0 V VOLmax=0.4 V CXA2069Q Pin No. Symbol Pin voltage Equivalent circuit Description VCC 4k 36 DC_OUT — 1k Q1 36 28k Outputs the S2-compatible DC superimposed onto the COUT3 output. The DC is superimposed by connecting this pin to the COUT3 output via a capacitor. Control is performed by the I2C bus. When 0 V is output, Q1 is ON and the impedance is 5 kΩ. S2 protocol output impedance of 10 ±3 kΩ is realized by attaching external resistance of 4.7 kΩ. DC_OUT (bus) Output DC 0 4.5 V 1 0V 2 1.9 V 3 4.5 V VCC 55 46 TRAP1 TRAP2 100 3.8 V Connects trap circuit for subcarrier. 55 46 1k VCC 147 48 MUTE — Audio signal output mute. Mute OFF at 1.5 V or less Mute ON at 2.5 V or more Mute OFF when open. 72k 48 28k VCC VCC VCC 20k 50 BIAS 4.5 V Internal reference bias (VCC/2). Connect to GND via a capacitor. 147 50 20k —7— CXA2069Q Electrical Characteristics (Ta=25 °C VCC=9 V) Item Symbol Current consumption ICC Conditions Min. Typ. Max. Unit 40 55 72 mA f=100 kHz, 0.3 Vp-p input 5.9 6.4 6.9 dB f=100 kHz, input frequency where output amplitude is –3 dB with 0.3 Vp-p output serving as 0 dB 15 20 10 15 — MHz No signal, no load Video system (Measurement circuit ; Fig. 1) Gain Frequency response characteristics Frequency response characteristics (Y/C mix) GVv FBWv1 FBWv2 MHz Input dynamic range Ddv f=100 kHz, maximum with distortion < 1.0 % 1.4 — — Vp-p Cross talk Vctv f=4.43 MHz, 1 Vp-p input — — –50 dB –1 0 1 dB 50 — — kHz — 0.03 0.05 % Audio system (Measurement circuits ; Fig. 2 to Fig. 5) Gain Frequency response characteristics GVA FBWA f=1 kHz, 1 Vp-p input, 5.7 kΩ resistor inserted to input f=1 kHz, input frequency where output amplitude is –3 dB with 1 Vp-p output serving as 0 dB f=1 kHz, 2.2 Vp-p input, where 400 Hz HPF+80 kHz LPF are inserted Total harmonic distortion THD Input dynamic range DdA f=1 kHz, maximum with distortion < 0.3 % 2.8 3.0 — Vrms Cross talk VctA f=1 kHz, 1 Vp-p input — –90 –80 dB Ripple rejection ratio VctA f=100 Hz, 0.3 Vp-p applied to VCC — –55 –40 dB Output DC offset Voff Offset voltage between input and output –30 — 30 mV Residual noise VNA 0 20 30 µVrms S/N ratio S/N –100 –90 dB When 400 Hz HPF+30 kHz LPF are inserted f=1 kHz, 1 Vrms input fCL=400 Hz, fCH=30kHz —8— CXA2069Q Logic system Item Symbol High level VIH input voltage Low level VIL input voltage Low level VOL output voltage High level IIH input current Low level IIL input current Maximum clock fSCL frequency Minimum waiting time tBUF for data change Minimum waiting time tHD;STA for data transfer start Low level clock tLOW pulse width High level clock tHIGH pulse width Minimum waiting time tSU;STA for start preparation Minimum data tHD;DAT hold time Minimum data tSU;DAT preparation time Conditions Min. Typ. Max. Unit 3.0 — 5.0 V 0 — 1.5 V With SDA 3 mA current supplied 0 — 0.4 V VIH=4.5V 0 — 10 µA VIL=0.4V 0 — 10 µA 0 — 100 kHz 4.7 — — µs 4.0 — — µs 4.7 — — µs 4.0 — — µs 4.7 — — µs 300 — — ns 250 — — ns Rise time tR — — 1 µs Fall time tF — — 300 ns 4.7 — — µs Minimum waiting time tSU;STO for stop preparation —9— CXA2069Q Measurement point 10k 10k 10k 10k 39 38 37 36 35 34 33 LOUT3 COUT3 DC OUT AGND SDA SCL 10µ 40 YOUT3 10µ 10µ 10µ VCC 53 VOUT1 41 VOUT3 42 ROUT3 43 10µ 10µ 44 LOUT2 10µ 45 V/YOUT2 10µ 1k 10µ 46 LOUT1 10k 10k 10k 10k 75 47 ROUT2 10µ 48 TRAP2 10k 52 49 COUT2 10µ 50 µcon YIN1 10k 51 22µ MUTE 10µ CIN1 10k BIAS 0.1µ 0.47µ 75 10µ 10k V ADR 32 RV5 31 54 ROUT1 V5 30 55 TRAP1 LV5 29 1µ 600 0.47µ 1µ 75 600 10µ 62 LTV V4 22 63 TV S-3 21 C2 S2-2 S-2 V3 LV3 Y3 RV3 C3 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1µ 75 1µ 600 0.47µ 1µ 75 600 0.47µ 75 20 75 600 75 600 75 75 0.1µ 1µ 75 600 1µ 600 75 0.1µ 75 1µ 75 600 Input signal 0.1µ 0.1µ RV2 5 1µ Y2 4 0.47µ LV2 3 0.47µ V2 2 0.47µ S-1 1 0.47µ S2-1 S2-3 C1 RTV 0.47µ 64 RV1 1µ 600 LV4 23 Y1 1µ 75 0.47µ Y4 24 61 RV6 1µ 600 RV4 25 60 V6 600 1µ C4 26 59 LV6 75 0.47µ 600 CXA2069Q 58 COUT1 0.47µ 1µ S2-4 27 75 10µ 600 S-4 28 57 VGND V1 10k 56 YOUT1 LV1 10k Signal is input from one of the following pins: 1, 3, 5, 8, 10, 12, 15, 17, 19, 22, 24, 26, 30, 60 and 63. Output signal is measured from one of the following pins: 37, 39, 41, 44, 47, 53, 56 and 58. Fig. 1 Video system (gain, frequency response characteristics, input dynamic range, cross talk) measurement circuit Measurement point 10k 10k 10k 10k 10k 10k 10k 10k 41 40 39 38 37 36 35 34 33 VCC VOUT3 ROUT3 YOUT3 LOUT3 COUT3 DC OUT AGND SDA SCL 10µ 10µ 42 LOUT2 10µ 10µ 10µ 10µ 43 V/YOUT2 10µ 44 ROUT2 10µ 1k 45 LOUT1 53 VOUT1 ADR 32 RV5 31 54 ROUT1 V5 30 55 TRAP1 LV5 29 5.7k 1µ 0.47µ 600 75 5.7k 1µ 600 10µ C4 26 59 LV6 RV4 25 60 V6 Y4 24 61 RV6 LV4 23 62 LTV V4 22 0.1µ 0.47µ Y2 RV2 C2 S2-2 S-2 V3 LV3 Y3 RV3 C3 9 10 11 12 13 14 15 16 17 18 19 75 600 75 600 75 75 75 600 600 75 600 20 Signal is input from one of the following pins: 2, 4, 9, 11, 16, 18, 23, 25, 29, 31, 59, 61, 62 and 64. Output signal is measured from one of the following pins: 38, 40, 43, 45, 52 and 54. Fig. 2 Audio system (gain, frequency response characteristics, total harmonic distortion, input dynamic range, cross talk) measurement circuit —10— 600 75 5.7k 1µ 0.47µ 0.1µ LV2 8 1µ 5.7k V2 7 0.47µ S-1 6 1µ 5.7k S2-1 5 0.47µ C1 4 0.1µ RV1 3 1µ 5.7k Y1 2 0.47µ LV1 1 1µ 5.7k V1 S2-3 75 5.7k 1µ S-3 21 1µ 5.7k 75 0.47µ 75 0.47µ 63 TV 1µ 5.7k 600 RTV 64 0.47µ 1µ 5.7k CXA2069Q 58 COUT1 75 600 S2-4 27 0.1µ 1µ 5.7k S-4 28 57 VGND 75 600 56 YOUT1 1µ 5.7k 10µ 1µ 5.7k 75 0.47µ Input signal 10µ 0.47µ 46 600 10k 600 47 0.47µ 10k 48 TRAP2 10µ 49 COUT2 10k 50 MUTE 10µ 51 YIN1 10k 52 µcon BIAS 10µ 22µ CIN1 10k 10k 75 10µ 0.1µ 75 V 600 75 CXA2069Q 10k 10k 10k 10k 10k 100Hz, 0.3Vp-p 39 38 37 36 35 34 33 LOUT3 COUT3 DC OUT AGND SDA SCL 10µ 10µ 40 YOUT3 10µ 10µ 41 ROUT3 LOUT2 LOUT1 53 VOUT1 42 VCC 43 VOUT3 44 µcon 10µ 10k 10k 45 ROUT2 10µ 46 V/YOUT2 10µ 10µ 10k 10k 10µ 0.47µ 47 TRAP2 10µ 48 COUT2 10k 52 49 YIN1 10µ 50 MUTE 10k 51 CIN1 10µ BIAS 10k 1k 75 10µ 0.1µ 75 Measurement point V 32 ADR RV5 31 54 ROUT1 V5 30 55 TRAP1 LV5 29 56 YOUT1 S-4 28 1µ 600 0.47µ 1µ 75 600 10µ 10k 57 VGND 10k 10µ 600 1µ S2-4 27 CXA2069Q 58 COUT1 C4 26 59 LV6 LV4 23 62 LTV V4 22 63 TV 75 1µ 600 0.47µ 1µ 75 600 0.47µ 75 S-3 21 S2-2 S-2 V3 LV3 Y3 RV3 C3 11 12 13 14 15 16 17 18 19 1µ 75 75 600 1µ 600 75 75 0.1µ 1µ 1µ 600 20 0.1µ C2 10 0.47µ RV2 9 0.47µ Y2 8 75 0.1µ 75 1µ 600 75 7 75 6 600 5 LV2 4 0.47µ 3 S-1 S2-1 2 S2-3 V2 C1 1 0.47µ RV1 RTV 0.47µ 64 Y1 1µ 600 1µ 75 0.47µ 61 RV6 600 1µ 0.47µ 600 Y4 24 75 1µ V1 600 RV4 25 60 V6 LV1 75 0.47µ 0.1µ A f=100Hz, 0.3Vp-p signal is applied to Vcc and the output signals from Pins 38, 40, 43, 45, 52 and 54 are measured. Fig. 3 Audio system (ripple rejection ratio) measurement circuit Measurement point 10k 10k 10k 10k 10k 10k 10k 10k 37 36 35 34 33 VCC VOUT3 ROUT3 YOUT3 LOUT3 COUT3 DC OUT AGND SDA SCL 10µ 10µ 38 LOUT2 10µ 10µ 10µ 39 V/YOUT2 10µ 40 TRAP2 10µ 10µ 1k 0.47µ 10µ 41 ADR 32 RV5 31 V5 30 56 YOUT1 S-4 28 57 VGND S2-4 27 10µ RV4 25 60 V6 Y4 24 61 RV6 LV4 23 62 LTV V4 22 75 0.47µ 63 TV 1µ 5.7k RTV 64 5.7k 1µ 0.47µ 600 75 5.7k 1µ 600 RV3 C3 18 19 0.47µ 20 75 600 75 600 600 75 5.7k 1µ 0.47µ V Measurement point Fig. 4 Audio system (output DC offset voltage) measurement circuit —11— 75 5.7k 1µ 0.1µ 17 1µ 5.7k Y3 16 0.47µ V3 LV3 S2-3 15 1µ 5.7k 0.47µ S-2 14 75 C2 S2-2 13 75 75 12 0.1µ RV2 11 1µ 5.7k 10 600 75 75 9 600 8 LV2 7 Y2 6 0.47µ V2 5 1µ 5.7k S-1 4 0.47µ S2-1 3 RV1 Y1 2 C1 LV1 1 600 75 0.1µ S-3 21 0.1µ 1µ 5.7k C4 26 59 LV6 75 1µ 5.7k CXA2069Q 58 COUT1 600 1µ 5.7k 0.47µ 600 42 LV5 29 V1 600 43 10µ 75 0.47µ 600 44 55 TRAP1 1µ 5.7k 600 45 54 ROUT1 1µ 5.7k 10k LOUT1 46 53 VOUT1 0.47µ 10k 47 ROUT2 10µ 48 MUTE 10k 52 49 COUT2 10µ 50 YIN1 10k 51 BIAS 10µ 22µ µcon CIN1 10k 10k 75 10µ 0.1µ 75 V 600 75 CXA2069Q 40dB Measurement point 10k 10k 10k 10k 36 35 34 33 SDA SCL 10µ 10µ 10µ 37 AGND VCC 38 DC OUT LOUT2 39 LOUT3 V/YOUT2 40 COUT3 ROUT2 41 YOUT3 42 10µ 10µ 43 VOUT3 44 ROUT3 45 LOUT1 10k 10k 10µ 46 TRAP2 10µ 47 COUT2 10µ 1k 10µ 48 ADR 32 RV5 31 54 ROUT1 V5 30 55 TRAP1 LV5 29 1µ 0.47µ 1µ 600 75 600 10µ V4 22 63 TV S-3 21 LV3 Y3 RV3 C3 11 12 13 14 15 16 17 18 19 75 600 75 600 75 75 600 75 600 75 75 20 0.1µ V3 10 1µ S-2 9 1µ S2-2 8 0.47µ C2 7 0.47µ RV2 6 0.1µ Y2 5 1µ LV2 4 0.47µ V2 3 1µ S-1 2 0.47µ 1 0.1µ S2-1 S2-3 C1 RTV RV1 64 Y1 1µ LV4 23 62 LTV 1µ 75 0.47µ 61 RV6 600 1µ Y4 24 LV1 600 RV4 25 60 V6 0.47µ 1µ C4 26 59 LV6 75 600 CXA2069Q 58 COUT1 V1 75 0.47µ S2-4 27 1µ 1µ S-4 28 57 VGND 0.47µ 10µ 600 56 YOUT1 75 10k 600 49 53 VOUT1 600 10k µcon YIN1 10k 10µ 50 22µ MUTE 10µ 51 BIAS 10k 52 10k 75 0.47µ 75 0.1µ 10µ CIN1 10k 10k 10µ 4.5V 10k V Fig. 5 Audio system (residual noise) measurement circuit —12— 0.1µ 75 1µ 600 0.47µ 1µ 0.47µ 75 600 75 75 75 RV5 31 64 RTV 63 TV 62 LTV 61 RV6 60 V6 1 2 3 4 VIDEO 1 input 5 7 6 8 9 10 VIDEO 2 input 11 12 14 13 15 17 18 VIDEO 3 input 16 S2-3 19 75 20 S-3 21 V4 22 LV4 23 Y4 24 RV4 25 C4 26 0.47µ 1µ 0.47µ 1µ 0.1µ 1µ 0.47µ 1µ 75 1µ Drive this input with low impedance to prevent cross talk for this pin. • Depending on the output bias of the comb filters, pay attention to the polarities of the capacitors since the bias at Pins 49 and 51 is approximately 3.1V and 4.5V, respectively. • Connect Pin 32 to VCC when setting the slave address of the IC to 92H. • The audio output can be muted by setting Pin 48 to 3.5V or more. • The TRAPs (Pins 46 and 55) are of 3.58MHz subcarrier. • The output impedance of the audio signal source must be 4.7kΩ. • Pay attention to the polarities of the capacitors since each output of video system and audio system has optional bias, respectively. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 1µ 0.47µ 1µ 1µ 59 LV6 58 COUT1 V1 VIDEO 1 output 32 S2-4 27 LV1 57 VGND Y1 S-4 28 S2-1 56 YOUT1 0.47µ 75 1µ 470k S-1 LV5 29 75 LV2 55 TRAP1 0.47µ 75 1µ 470k Y2 V5 30 RV1 470k 0.47µ 75 RV2 54 ROUT1 53 VOUT1 1µ 1µ 470k S2-2 1µ CIN1 1µ S-2 0.47µ BIAS CXA2069Q YIN1 75 10p 180µ 620 MUTE C1 ADR COUT2 C2 LOUT1 46 TRAP2 V3 52 33 34 35 36 37 38 39 40 41 42 43 44 45 ROUT2 0.1µ V/YOUT2 47 0.1µ µcon LOUT2 LV3 470k VIDEO 6 input VCC Y3 75 TV input VOUT3 48 1µ ROUT3 49 620 180µ 10p YOUT3 470k V2 LOUT3 50 0.47µ COUT3 51 1k 0.1µ DC OUT 0.47µ 1µ AGND RV3 0.1µ 0.47µ SDA 22µ 0.47µ COMB FILTER 10µ 220 1µ VIDEO 3 output 0.1µ VIDEO 2 output 220 SCL C3 —13— 1µ VIDEO 5 input VIDEO 4 input Application Circuit CXA2069Q CXA2069Q I2C BUS Control Signal 34 SDA tBUF 33 SCL tHD;STA tLOW P tR tHD;DAT tHIGH tF tSU;DAT tSU;STA tSU;STO S P S Fig. 6 I2C BUS Control Signal Timing Chart Description of Operation The CXA2069Q is a TV I2C bus-compatible AV switch IC. The video system and the stereo audio system both have 7 inputs and 3 outputs each. 4 of the 7 video system inputs support S2 and S protocols. The desired inputs can be independently assigned to each output (in the audio system, the left and right channels are processed as one unit) by I2C bus control. However, the same input is assigned to both the video and audio system output 3. I2C BUS Registers 1) I2C BUS The I2C bus (inter-IC bus) is an inter-IC bus system developed by Philips. Two lines (SDA–serial data, SCL–serial clock) provide control over start, stop, data transfer, synchronization, and collision avoidance. The IC outputs are either open collector or open drain, forming a bus line in the wired OR format. SDA A MSB LSB A MSB LSB SCL S P 1 2 3 4 5 6 7 8 9 1 2 9 S : Start condition ; SDA is set “Low” when SCL is “High” P : Stop condition ; SDA is set “High” when SCL is “High” A : Acknowledge ; signal sent from the slave Data is transmitted by MSB-first. One data unit consists of 8 bits, to which the acknowledge signal, which indicates that the data has been accepted by the slave, is attached at the end. Normally, the slave∗1 IC receives data at the rising edge of SCL and the master∗2 IC changes data at the falling edge of SCL. ∗1 ∗2 Slave : An IC that is placed under the control of the master. In a normal system, all devices excluding the central microcomputer are slaves. Master : A central microcomputer or other controlling IC. —14— CXA2069Q 2) Control Registers The CXA2069Q control is exercised by writing 3-byte data into the three 8-bit control registers which control the output selector circuits for the 3 outputs. S Slave address A DATA1 A DATA2 A DATA3 A P S ; Start condition A ; Acknowledge P ; Stop condition O Control register structure (DATA1 to DATA3) • All registers are set to “0” during IC power on. • “∗” indicates undefined. b7 b6 b5 b4 Slave add. DATA1 DATA2 DATA3 1 0 A-GAIN S/COMP1 V/YOUT S/COMP2 ∗ S/COMP3 0 1 V-IN1 V-IN2 AV-IN3 b3 b2 b1 b0 0 0 ADR A-IN1 A-IN2 DC OUT R/W ∗ R/W (1) : Read/write mode 0 : Control data write 1 : Status register read ADR (1) : This bit sets the slave address set by the address pin. 0 : 90H 1 : 92H A-GAIN (1) : LOUT1/ROUT1 output gain selector 0 : 0 dB output 1 : –6 dB output S/COMP1 to S/COMP3 (1 each) : S terminal input/composite signal input selectors By setting S/COMP1 to “0”, when composite signal input is selected, YOUT1/COUT1 output the inputs from YIN1/CIN1 during video 1 output. 0 : Composite signal inputs (TV, V1 to V6 inputs) 1 : S terminal inputs (Y1/C1 to Y4/C4 inputs) V/YOUT (1) : This bit selects the output to Pin 44 (V/YOUT2). 0 : VOUT (composite signal) output 1 : YOUT (luminance signal) output V-IN1 to V-IN2 (3 each) : These bits select the input signals output to each video output. V-IN1 corresponds to the VOUT1 and YOUT1/COUT1 outputs, and V-IN2 to the VOUT2 and YOUT2/COUT2 outputs. 0 : Mute 4 : Selects the V3 and Y3/C3 inputs 1 : Selects the TV input 5 : Selects the V4 and Y4/C4 inputs 2 : Selects the V1 and Y1/C1 inputs 6 : Selects the V5 input 3 : Selects the V2 and Y2/C2 inputs 7 : Selects the V6 input —15— CXA2069Q A-IN1 to A-IN2 (3 each) : These bits select the input signals output to each audio output. A-IN1 corresponds to the LOUT1/ROUT1 outputs, and A-IN2 to the LOUT2/ROUT2 outputs. 0 : Mute 4 : Selects the LV3/RV3 inputs 1 : Selects the LTV/RTV inputs 5 : Selects the LV4/RV4 inputs 2 : Selects the LV1/RV1 inputs 6 : Selects the LV5/RV5 inputs 3 : Selects the LV2/RV2 inputs 7 : Selects the LV6/RV6 inputs AV-IN3 (3) : This bit selects the input signals output to output 3. Both the video output and the audio output are selected at the same time only for AV-IN3. 0 : Mute 4 : Selects the V3, Y3/C3 and LV3/RV3 inputs 1 : Selects the TV and LTV/RTV inputs 5 : Selects the V4, Y4/C4 and LV4/RV4 inputs 2 : Selects the V1, Y1/C1 and LV1/RV1 inputs 6 : Selects the V5 and LV5/RV5 inputs 3 : Selects the V2, Y2/C2 and LV2/RV2 inputs 7 : Selects the V6 and LV6/RV6 inputs DC OUT (2) : These bits set the DC voltage output from Pin 35 (DC OUT). 0 : 4.5 V 1:0V 2 : 1.9 V 3 : 4.5 V 3) Status Registers • When reading two bytes S Slave address A DATA1 • When reading one byte S Slave address A DATA1 S; A; NA ; P; A DATA2 NA P NA P Start condition Acknowledge No acknowledge Stop condition When communication is to be terminated in the status register reading mode, the “no-acknowledge” signal is needed to assure that the master does not issue the acknowledge signal to the slave. It is possible to read only DATA1 of the status register by sending the no-acknowledge signal after DATA1. O Status register structure (DATA1 to DATA2) b7 b6 b5 Slave add. DATA1 DATA2 1 S1SEL S1SEL 0 S2SEL S2SEL 0 S3SEL S3SEL b4 b3 b2 b1 b0 1 S4SEL S4SEL 0 0 ADR 1 —16— S-C1 S-C3 S-C2 S-C4 CXA2069Q S1SEL to S4SEL (1 each) : S-1 to S-4 pin status 0 ; S-1 to S-4 pins are not grounded. 1 ; S-1 to S-4 pins are grounded. S1SEL to S4SEL are actually determined by comparing the S-1 to S-4 pin DC voltages with 3.5 V. S-1 to S-4 pin DC voltage S1SEL to S4SEL 3.5 V or more 0 3.5 V or less 1 S-C1, S-C2, S-C3, S-C4 (2 each) : S2-1, S2-2, S2-3 and S2-4 pin status 0 ; 4 : 3 video signal S2-1 to S2-4 pin DC voltage 1 ; 4 : 3 letter-box signal 1.3 V or less 2 ; 16 : 9 video squeezed signal 1.3 V or more to 2.5 V or less 3 ; No signal 2.5 V or more S-C1 to S-C4 are actually determined by S-1 to S-4 OPEN comparing the S2-1 to S2-4 pin DC voltages with two threshold. However, when the S-1 to S-4 pins are open, the outputs are fixed to “3”. S-C1 to S-C4 0 1 2 3 4) Power-on Reset The CXA2069Q has an internal power-on reset function that sets each control register to “0” during IC power ON. The power-on reset VTH has hysteresis. Power-on reset released Power-on reset 4.5V 5.6V —17— VCC CXA2069Q Video system frequency response characteristics Video system input/output gain [dB] 8 TV, V1 to V6 → VOUT1 to VOUT3 Y1 to Y4 → YOUT1 to YOUT3 C1 to C4 → COUT1 to COUT3 6 Y1/C1 to Y4/C4 → VOUT1 to VOUT3 4 2 0 –2 100k 1M 10M 100M Frequency [Hz] Audio system frequency response characteristics Audio system input/output gain [dB] 2 L/RTV, L/R1 to L/R6 → LOUT1 (0dB) L/RTV, L/R1 to L/R6 → LOUT2 to LOUT3 0 –2 –4 L/RTV, L/R1 to L/R6 → LOUT1 (–6dB) –6 –8 1k 10k 100k Frequency [Hz] Audio system distortion vs. Input amplitude 10 Total harmonic distortion [%] f=1kHz 400Hz HPF, 80kHz LPF 1 0.1 LOUT1 output (0dB gain) LOUT2 and LOUT 3 outputs 0.01 0.002 0 1 2 Input amplitude [Vrms] 3 —18— 4 1M CXA2069Q Package Outline Unit : mm 64PIN QFP(PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.1 0.15 – 0.05 0.15 64 20 1 16.3 32 + 0.4 14.0 – 0.1 52 17.9 ± 0.4 33 + 0.2 0.1 – 0.05 19 + 0.35 2.75 – 0.15 + 0.15 0.4 – 0.1 1.0 0.2 M 0° to10° 0.8 ± 0.2 51 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-64P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE QFP064-P-1420 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 1.5g JEDEC CODE —19—