SONY CXA2040Q

CXA2040Q
I2C Bus-Compatible Video Switch
For the availability of this product, please contact the sales office.
Description
The CXA2040Q is an I2C bus-compatible 5-input,
3-output video switch for TVs.
32 pin QFP (Plastic)
Features
• Serial data control via I2C bus
• 5 composite video input systems
• 2 Y/C (S terminal) input systems
• 3 composite video output systems
• 1 Y/C (S terminal) output system
• Input can be selected independently for each
output system.
• SYNC_ID function for CV1 system input
• Built-in 6dB amplifier for CVOUT2 system output
• Built-in Y/C MIX circuit
• Slave address can be changed (90H/92H).
• High impedance maintained by I2C bus line (SDA,
SCL) even when power is OFF.
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VCC
12
V
• Operating temperature
Topr –20 to +75 °C
• Storage temperature
Tstg –65 to +150 °C
• Allowable power dissipation PD
1.0
W
(when mounted on a 50mm × 50mm board)
Operating Conditions
Supply voltage
Applications
TVs
VCC
9.0 ± 0.5
V
Structure
Bipolar silicon monolithic IC
NC
CV1
SYNCTC
SDA
SCL
ADR
NC
CVOUT1
Pin Configuration (Top View)
24
23
22
21
20
19
18
17
CV2 25
16 NC
VCC 26
15 CVOUT2
CV3 27
14 NC
13 CVOUT3
NC 28
12 NC
CV4 29
GND 30
11 YOUT
CV5 31
10 NC
BIAS 32
NC
C1
S1
5
6
7
8
NC
4
C2
3
S2
2
Y2
1
Y1
9 COUT
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95Z44-ST
CXA2040Q
GND
VCC
SCL
SDA
ADR
S1
S2
Block Diagram
30
26
20
21
19
4
6
I2C BUS DECODER
SYNCTC 22
SYNC DETECT
CV1
CV2
CV1
CV1 23
CV3
CV4
CV5
17 CVOUT1
SW1
CV6
CV2
CV2 25
CV7
MUTE
CV3
CV3 27
CV1
CV2
CV3
6dB
CV4
CV4
CV4 29
CV5
SW2
15 CVOUT2
SW3
13 CVOUT3
SW4
11 YOUT
SW5
9 COUT
CV6
CV7
MUTE
CV5
CV5 31
CV1
CV2
CV6
Y1 1
CV3
CV4
CV5
CV6
CV7
C1 3
MUTE
CV7
Y2 5
Y1
Y2
MUTE
C2 7
C1
C2
MUTE
BIAS 32
BIAS
MUTE
∗ Numbers inside circles indicate the IC pin numbers.
–2–
CXA2040Q
Pin Description
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC
20k
1
1
5
3
7
Y1
Y2
C1
C2
5
4.5V
147
3
×2
7
28k
VCC
4
6
50k
S1
S2
50k
4
6
100k
×4
Y/C separation signal inputs.
Biased to approximately 4.5V.
Input the input signals through
capacitors. Connect protective
resistor of 220Ω between these
pins and the capacitors.
Y1 and Y2 pins: Luminance
signals input.
C1 and C2 pins: Chrominance
signals input.
Applying a DC voltage to S1 and
S2 pins allows these voltages to
be applied to the microcomputer
as the I2C bus status register data.
S1, S2 = 0 to 2V
OPEN = 0, SEL = 1
S1, S2 = 4.75 to 7.25V
OPEN = 0, SEL = 0
S1, S2 = 9.5 to 12V
OPEN = 1, SEL = 0
VCC
200
11
9
YOUT
COUT
×5
4.5V
1.2k
×2
11
9
Y/C signal outputs.
YOUT pin: Luminance signal
output.
COUT pin: Chrominance signal
output.
×6
×2
200
1.2k
VCC
17
15
13
CVOUT1
CVOUT2
CVOUT3
4.5V
17
×5
15
13
×6
×2
×2
–3–
Composite video signal outputs.
CVOUT1, CVOUT2:
0dB output with respect to
the input signal.
CVOUT2:
+6dB output with respect
to the input signal.
CXA2040Q
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC
Selects the slave address for the
I2C bus.
90H at 1.0V or less
92H at 3.5V or more
90H when open
19
19
72k
ADR
28k
VCC
I2C bus signal input.
Connect protective resistor of
220Ω between this pin and the
SCL line.
4k
20
SCL
—
20
×4
VCC
I2C bus signal input.
Connect protective resistor of
220Ω between this pin and the
SDA line.
4k
21
21
SDA
—
×6
VCC
1.2k
147
Sync tip clamp time constant for
Sync Separation.
Connect 68kΩ resistor between
this pin and VCC.
Connect 10µF capacitor between
this pin and GND.
147
22
SYNCTC
22
1.2k
–4–
CXA2040Q
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC
20k
23
CV1
4.5V
147
23
28k
Composite video signal input.
Biased to approximately 4.5V.
Input the input signal through
capacitor. Connect protective
resistor of 220Ω between this pin
and the capacitor.
The composite video signal input
to CV1 is also taken into the
"SYNC DETECT circuit" of which
SYNC is existed or not.
VCC
25
Composite video signal input.
Biased to approximately 4.5V.
Input the input signals through
capacitors. Connect protective
resistor of 220Ω between these
pins and the capacitors.
20k
25
27
29
31
CV2
CV3
CV4
CV5
4.5V
26
VCC
9.0V∗1
Power supply.
Apply 9.0V.
30
GND
0.0V∗1
GND.
27
147
29
31
28k
VCC
1.2k
32
BIAS
4.5V
22.5k
32
20k
2
8
10
12
14
16
18
24
28
4.5V bias.
Attach a decoupling capacitor
between this pin and GND.
This pin cannot be used as an
external power supply.
NC (not connected).
Connect to GND.
If these NC pins are not connected
to GND, the cross talk and other
desired values indicated in the
Electrical Characteristics cannot
be obtained.
NC
∗1 Applied externally.
–5–
ICC
VBIAS
GCV11
GCV21
GCVM11
Pin voltage
CV system
gain 1
CV system
gain 2
CV system
(Y/C MIX)
gain 1
2
3
4
5
Symbol
Current
consumption
Item
–6–
Select each input with I2C bus
control and obtain the I/O gain.
Y1 and C1 (CV6) In or
Y2 and C2 (CV7) In
100kHz, 0.15Vp-p CW
Select each input with I2C bus
control and obtain the I/O gain.
CV1 In, CV2 In, CV3 In,
CV4 In or CV5 In
100kHz, 0.3Vp-p CW
Select each input with I2C bus
control and obtain the I/O gain.
CV1 In, CV2 In, CV3 In,
CV4 In or CV5 In
100kHz, 0.3Vp-p CW
VCC = 9V, no signal
VCC = 9V, no signal
Measurement conditions
13, 17
15
13, 17
32
26
Measurement pins
VCV21
0.3Vp-p
VCV11
0.3Vp-p
VCVM11
VCV21
5.75
–0.40
4.25
18.0
Min.
VCVM11
20Log
–0.40
0.3Vp-p
∗ Since the sum of 0.15Vp-p
and 0.15Vp-p is input to
each switch, calculations
are performed with 0.3Vp-p.
20Log
20Log
VCV11
Measure the pin voltage.
Measure the pin inflow
current.
Measurement contents
See Electrical Characteristics Measurement Circuit 2 for Cross talk and MUTE.
See Electrical Characteristics Measurement Circuit 1 for all other items.
1
No.
Electrical Characteristics
0.10
6.25
0.00
4.50
27.7
Typ.
0.60
6.75
0.40
4.75
39.0
Max.
dB
dB
dB
V
mA
Unit
(Ta = 25°C, VCC = 9V)
CXA2040Q
–7–
GC11
∆GCV12
CV system
frequency
response 1
9
7
C system
gain
GY11
Y system
gain
8
GCVM21
CV system
(Y/C MIX)
gain 2
6
Symbol
Item
No.
Select each input with I2C bus
control and obtain the I/O gain.
Then obtain the difference from the
I/O gain measured by Test 3.
CV1 In, CV2 In, CV3 In,
CV4 In or CV5 In
10MHz, 0.3Vp-p CW
Select each input with I2C bus
control and obtain the I/O gain.
C1 In or C2 In
100kHz, 0.3Vp-p CW
Select each input with I2C bus
control and obtain the I/O gain.
Y1 In or Y2 In
100kHz, 0.3Vp-p CW
Select each input with I2C bus
control and obtain the I/O gain.
Y1 and C1 (CV6) In or
Y2 and C2 (CV7) In
100kHz, 0.15Vp-p CW
Measurement conditions
13, 17
9
11
15
Measurement pins
VCV12
VCV11
VC11
0.3Vp-p
VY11
0.3Vp-p
VCV12
VC11
∗ VCV11 and VCV12 should be
the same I/O.
20Log
20Log
20Log
VY11
VCVM21
20Log
0.3Vp-p
∗ Since the sum of 0.15Vp-p
and 0.15Vp-p is input to
each switch, calculations
are performed with 0.3Vp-p.
VCVM21
Measurement contents
–0.85
–0.40
–0.40
5.75
Min.
–0.15
0.00
0.00
6.40
Typ.
0.55
0.40
0.40
7.05
Max.
dB
dB
dB
dB
Unit
CXA2040Q
–8–
∆GCVM22
∆GY12
Y system
frequency
response
13
11
12
∆GCVM12
CV system
(Y/C MIX)
frequency
response 1
CV system
(Y/C MIX)
frequency
response 2
∆GCV22
CV system
frequency
response 2
10
Symbol
Item
No.
Select each input with I2C bus
control and obtain the I/O gain.
Then obtain the difference from the
I/O gain measured by Test 7.
Y1 In or Y2 In
10MHz, 0.3Vp-p CW
Select each input with I2C bus
control and obtain the I/O gain.
Then obtain the difference from the
I/O gain measured by Test 6.
Y1 and C1 (CV6) In or
Y2 and C2 (CV7) In
10MHz, 0.15Vp-p CW
Select each input with I2C bus
control and obtain the I/O gain.
Then obtain the difference from the
I/O gain measured by Test 5.
Y1 and C1 (CV6) In or
Y2 and C2 (CV7) In
10MHz, 0.15Vp-p CW
Select each input with I2C bus
control and obtain the I/O gain.
Then obtain the difference from the
I/O gain measured by Test 4.
CV1 In, CV2 In, CV3 In,
CV4 In or CV5 In
10MHz, 0.3Vp-p CW
Measurement conditions
11
15
13, 17
15
Measurement pins
VCVM12
VCVM11
VCVM22
VCVM21
VY12
VY11
∗ VY11 and VY12 should be the
same input.
20Log
VY12
∗ VCVM21 and VCVM22 should
be the same input.
20Log
VCVM22
∗ VCVM11 and VCVM12 should
be the same I/O.
20Log
VCVM12
20Log VCV22
VCV21
∗ VCV21 and VCV22 should be
the same I/O.
VCV22
Measurement contents
–0.70
–1.75
–1.75
–0.85
Min.
0.00
–0.25
–0.25
–0.15
Typ.
0.70
1.25
1.25
0.55
Max.
dB
dB
dB
dB
Unit
CXA2040Q
–9–
VY13
VC13
C system
input dynamic
range
17
VCVMC33
VCVMY33
VCV13
Symbol
Y system
input dynamic
range
CV system
(Y/C MIX)
input dynamic
range
CV system
input dynamic
range
Item
16
15
14
No.
Select each input with I2C bus
control and then increase the input
waveform amplitude.
C1 In or C2 In
f = 100 kHz CW
Select each input with I2C bus
control and then increase the input
waveform amplitude.
Y1 In or Y2 In
f = 100kHz CW
Select each input with I2C bus
control and then increase the input
waveform amplitude.
C1 (CV6) In or C2 (CV7) In
f = 100kHz CW
Select each input with I2C bus
control and then increase the input
waveform amplitude.
Y1 (CV6) In or Y2 (CV7) In
f = 100kHz CW
Select each input with I2C bus
control and then increase the input
waveform amplitude.
CV1 In, CV2 In, CV3 In,
CV4 In or CV5 In
f = 100kHz CW
Measurement conditions
3, 7
1, 5
3, 7
1, 5
23, 25, 27,
29, 31
Measurement pins
Typ.
2.2
Max.
Vp-p
Unit
2.2
Vp-p
The value for the PAL
composite signal should
correspond to an amplitude of
approximately 1Vp-p + 3dB.
Min.
0.95
Vp-p
The input waveform
amplitude value when Pin 9
output waveform distortion
factor = 1%.
VC13
The input waveform
amplitude value when Pin 11
output waveform distortion
factor = 1%.
VY13
Vp-p
Vp-p
The value for the C signal
should correspond to an
amplitude of approximately
2.2Vp-p.
2.2
The value for the PAL Y signal
should correspond to an
amplitude of approximately
1Vp-p + 3dB.
2.2
The value for the PAL C signal
The input waveform amplitude
value when Pins 13, 15 or 17 output should correspond to an amplitude
of approximately 0.66Vp-p + 3dB.
waveform distortion factor = 1%.
VCVMC
C1 or C2 input waveform
The value for the PAL Y signal
The input waveform amplitude
value when Pins 13, 15 or 17 output should correspond to an amplitude
of approximately 1Vp-p + 3dB.
waveform distortion factor = 1%.
VCVMY
Y1 or Y2 input waveform
The input waveform
amplitude value when Pins
13, 15 or 17 output waveform
distortion factor = 1%.
VCV13
Measurement contents
CXA2040Q
GM2
19
MUTE
(CV system 2)
GM1
MUTE
CV system 1,
Y system,
C system
20
GCRS
Symbol
Cross talk
Item
18
No.
9, 11,
13, 17
Set this pin to MUTE status with I2C
bus control and input a 4.43MHz,
1Vp-p CW to one input pin system.
Then ground the remaining 8 input
pins via capacitors.
15
9, 11, 13,
15, 17
Select the input with I2C bus control
and ground that input pin via a
capacitor. Input a 4.43MHz, 1Vp-p
CW to one input pin system among
the remaining 8 input pins (7 input
pins for Y/C MIX). Then ground the
remaining 7 input pins (6 input pins
for Y/C MIX) via capacitors.
Set this pin to MUTE status with I2C
bus control and input a 4.43MHz,
1Vp-p CW to one input pin system.
Then ground the remaining 8 input
pins via capacitors.
Measurement pins
Measurement conditions
VX
1Vp-p
– 10 –
VX
1Vp-p
VX
20Log 1Vp-p
VX
Read the output waveform
value.
20Log
VX
Read the output waveform
value.
20Log
VX
Read the output waveform
value.
Measurement contents
Min.
Typ.
–45
–50
–55
Max.
dB
dB
dB
Unit
CXA2040Q
– 11 –
SYNCD22
SYNC
discrimination 22
24
22
SYNCD12
SYNCD21
SYNC
discrimination 21
21
23
SYNCD11
SYNC
discrimination 11
SYNC
discrimination 12
Symbol
Item
No.
10.17µs
63.56µs
CV1 In: Sig-4
5.72µs
63.56µs
CV1 In: Sig-3
4.70µs
63.56µs
CV1 In: Sig-2
4.70µs
63.56µs
CV1 In: Sig-1
Duty = 84%
286mV
Duty = 91%
286mV
30mV
100mV
Measurement conditions
21 (SDA)
21 (SDA)
21 (SDA)
21 (SDA)
Measurement pins
Input Sig-4 to CV1 and check
that bit 5 "SYNCSEP" of the
I2C bus status register is "0"
when the Sig-4 duty is 84%
or less (the sync width is
10.17µs or more).
Input Sig-3 to CV1 and check
that bit 5 "SYNCSEP" of the
I2C bus status register is "1"
when the Sig-3 duty is 91%
or more (the sync width is
5.72µs or less).
Input Sig-2 to CV1 and check
that bit 5 "SYNCSEP" of the
I2C bus status register is "0"
when the Sig-2 sync level is
30mV or less.
Input Sig-1 to CV1 and check
that bit 5 "SYNCSEP" of the
I2C bus status register is "1"
when the Sig-1 sync level is
100mV or more.
Measurement contents
Typ.
Max.
mV
Unit
mV
%
%
Sync is determined not to exist
when a rectangular wave with
a duty of 84% or less is input
to CV1 even when the sync
level is 100mV or more.
84
Sync is determined to exist
when the sync level is 100mV
or more and a rectangular
wave with a duty of 91% or
more is input to CV1.
91
The Sig-2 sync level should
correspond to approximately
–19dB when the 1Vp-p NTSC
composite signal sync level
(286mV) is set as 0dB.
30
The Sig-1 sync level should
correspond to approximately
–9dB when the 1Vp-p NTSC
composite signal sync level
(286mV) is set as 0dB.
100
Min.
CXA2040Q
25
No.
ADR threshold
voltage
Item
VADRVTH
Symbol
Vary the Pin 19 VADR.
Measurement conditions
21
Measurement pins
Min.
1.0
Measurement contents
The slave address goes to
92H at high level and 90H at
low level.
Typ.
3.5
Max.
V
Unit
CXA2040Q
– 12 –
CXA2040Q
Electrical Characteristics Measurement Circuit 1
10k
I2C bus
I/O
68k
VADR
CV1
2.2µ
10µ
24
23
22
21
20
19
18
17
NC
CV1
SYNCTC
SDA
SCL
ADR
NC
CVOUT1
25 CV2
CV2
0.1µ
CVOUT2 15
26 VCC
VCC
NC 16
2.2µ
9V
CV5
10µ
10k
10µ
10k
2.2µ
CVOUT3 13
28 NC
CV4
10k
NC 14
27 CV3
CV3
10µ
29 CV4
NC 12
30 GND
YOUT 11
2.2µ
31 CV5
NC 10
32 BIAS
COUT 9
2.2µ
NC
C1
S1
Y2
S2
C2
NC
0.01µ
Y1
33µ
1
2
3
4
5
6
7
8
Vs1
0.47µ 10k
Vs2
2.2µ
2.2µ
2.2µ
2.2µ
Y1
C1
Y2
C2
∗1 Unless otherwise specified in the Measurement conditions column of Electrical Characteristics, all
are
GND.
∗2 Unless otherwise specified in the Measurement conditions column of Electrical Characteristics, the supply
voltages are as follows.
VCC = 9V, VS1 = 0V, VS2 = 0V
VADR = 0V when operated with a slave address of 90H.
VADR = 9V (VCC) when operated with a slave address of 92H.
– 13 –
CXA2040Q
Electrical Characteristics Measurement Circuit 2 (Cross talk, MUTE)
I2C bus
I/O
68k
VADR
CV1
0.1µ
23
22
21
20
19
18
17
NC
CV1
SYNCTC
SDA
SCL
ADR
NC
CVOUT1
2.2µ
24
25 CV2
CV2
NC 16
2.2µ
26 VCC
CVOUT2 15
27 CV3
NC 14
VCC 9V
CV3
2.2µ
CVOUT3 13
28 NC
CV4
CV5
29 CV4
NC 12
30 GND
YOUT 11
31 CV5
NC 10
32 BIAS
COUT 9
2.2µ
2.2µ
NC
C1
S1
Y2
S2
C2
NC
0.01µ
Y1
33µ
1
2
3
4
5
6
7
8
2.2µ
2.2µ
2.2µ
2.2µ
Y1
C1
Y2
C2
∗1 Unless otherwise specified in the Measurement conditions column of Electrical Characteristics, all
are
GND.
∗2 Unless otherwise specified in the Measurement conditions column of Electrical Characteristics, the supply
voltages are as follows.
VCC = 9V
VADR = 0V when operated with a slave address of 90H.
VADR = 9V (VCC) when operated with a slave address of 92H.
– 14 –
CXA2040Q
I2C Bus Control Map
1) Control Register
The CXA2040Q control system is comprised of 4 bytes of control registers which control the various outputs.
The inputs which are to be output are selected by writing the respective input data into the control register.
S
Slave address
A DATA1 A DATA2 A DATA3 A DATA4 A P
S: START CONDITION
A: ACKNOWLEDGE
P: STOP CONDITION
• Slave address
1
0
0
1
0
0
X
R/W bit
This bit is set to "0" when data is to be written into the control
registers.
0
Value set by the address pin
DATA1
DATA2
DATA3
DATA4
Controls the video output 1.
Controls the video output 2.
Controls the video output 3.
Controls the S terminal output.
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
X
X
video select
X
X
X
Each register is set to "0" upon POWER ON.
• Video switch control map
bit5 bit4 bit3 Selected input signal
0
0
0
MUTE
0
0
1
CV1/YC1
0
1
0
CV2/YC2
0
1
1
CV3
1
0
0
CV4
1
0
1
CV5
1
1
0
CV6
1
1
1
CV7
Other conditions: MUTE
– 15 –
CXA2040Q
2) Status Register
S
Slave address
A
DATA
NA P
S: START CONDITION
P: STOP CONDITION
A: ACKNOWLEDGE
• Slave address
1
0
0
1
0
0
X
R/W bit
This bit is set to "1" when data is to be read into the status
registers.
1
Value set by the address pin
DATA
bit7
bit6
bit5
bit4
bit3
PON
RES
X
SYNC
SEP
X
S1
OPEN
bit2
bit1
S1
S2
SEL OPEN
bit0
S2
SEL
(1) PONRES
Returns "1" when the CXA2040Q is POWER ON RESET. Becomes "0" after reading once.
(2) SYNCSEP
"1" returns if sync exists, "0" if sync does not exist.
(3) OPEN/SEL for S1 and S2 is determined by comparing the DC voltages for S1 and S2 pins with two
threshold levels.
DC voltages for S1 and S2 pins S1, S2 OPEN S1, S2 SEL
2V or less
0
1
4.75 to 7.25V
0
0
9.5 to 12V
1
0
3) POWER ON RESET
The CXA2040Q incorporates a POWER ON RESET function which sets each control register to "0" upon
POWER ON. (Which goes to MUTE status.)
The POWER ON RESET VTH has hysteresis. The POWER ON VCC and released VCC are as shown below.
Also, the PONRES bit of the status register is read to determine whether the IC is reset upon POWER ON.
POWER ON RESET RELEASE
POWER ON RESET
Vcc
4.7V
– 16 –
5.9V
CXA2040Q
Description of Operation
1) Composite Video System I/Os
There are three systems of composite outputs. Each output switch can select the eight systems of CV1 to CV5
composite video inputs, CV6 and CV7 Y/C MIX (composite video) inputs and MUTE. All composite video
inputs are input from the input pins to each switch by DC coupling. CV6 is the composite video signal obtained
by inputting Y1 and C1 to an adder and adding Y1 and C1. CV7 is the composite video signal obtained by
inputting Y2 and C2 to an adder and adding Y2 and C2. The CV6 and CV7 composite video signals are input
from the input pins to each switch by DC coupling. When MUTE is selected, the internal bias DC output
(approximately VCC/2 [V]) is input to each switch. Only one type of input is selected by the I2C bus control
register. The CVOUT1 and CVOUT3 switches output the signal selected by the I2C bus at a gain of 0 [dB] with
respect to the input signal. The switch output stages are push-pull circuits which output at low impedance. The
CVOUT2 switch outputs the signal selected by the I2C bus amplified to +6 [dB] with respect to the input signal.
The switch output stage is a push-pull circuit which outputs at low impedance. The switches are DC coupled
from input to output.
2) Y System I/Os
The YOUT switch can select the three systems of Y1, Y2 and MUTE. Y1 and Y2 are input from the input pins
to the switch by DC coupling. When MUTE is selected, the internal bias DC output (approximately VCC/2 [V]) is
input to the switch. Only one type of input is selected by the I2C bus control register. The YOUT switch outputs
the signal selected by the I2C bus at a gain of 0 [dB] with respect to the input signal. The switch output stage is
a push-pull circuit which outputs at low impedance. The switch is DC coupled from input to output.
3) C System I/Os
The COUT switch can select the three systems of C1, C2 and MUTE. C1 and C2 are input from the input pins
to the switch by DC coupling. When MUTE is selected, the internal bias DC output (approximately VCC/2 [V]) is
input to the switch. Only one type of input is selected by the I2C bus control register. The COUT switch outputs
the signal selected by the I2C bus at a gain of 0 [dB] with respect to the input signal. The switch output stage is
a push-pull circuit which outputs at low impedance. The switch is DC coupled from input to output.
– 17 –
CXA2040Q
4) Sync Discrimination
68k
Vcc
0.1µ
22
IC
SYNCTC
Input signal
23
2.2µ
Sync tip clamp and
comparator
Duty
discrimination
I2C
CV1
Fig. 1. Sync discrimination circuit block diagram
Fig. 1 shows the block diagram for the sync discrimination circuit. The signal input from Pin 23 (CV1) is sync tip
clamped by the external element attached to Pin 22. This signal is compared with a threshold voltage which is
larger than the sync tip level. If the signal is smaller than the threshold level, it does not proceed to the
following stage. At this time, the IC determines that sync does not exist. If the signal is larger than the threshold
level, it proceeds to the duty discrimination block. If the duty is greater than 91%, the duty discrimination block
determines that sync exists and sends the data to the I2C. If the duty is less than 84%, sync is determined not
to exist and the data is sent to the I2C. The duty discrimination block also has a time constant. After sync is
determined to exist, the sync status is held for approximately 14H (NTSC signal) even if the IC goes to a status
where sync does not exist such as no signal, etc. If there is no signal or sync does not exist for longer than
14H, the status switches from sync exists to sync does not exist.
– 18 –
CXA2040Q
Application Circuit
VCC
I2C BUS
68k
0.1µ
2.2µ
VADR
220
220
Composite video
signal inputs
75
Vcc
23
22
21
20
19
18
17
CV1
SYNCTC
SDA
SCL
ADR
NC
CVOUT1
220
33µ
24
NC
75
2.2µ
0.01µ
25 CV2
9V
10µ
Composite
video signal
0dB output 3
NC 14
27 CV3
220
28 NC
75
CVOUT3 13
CXA2040Q
2.2µ
10µ
Composite
video signal
+6dB output 2
NC 16
CVOUT2 15
26 VCC
2.2µ
10µ
Composite
video signal
0dB output 1
220
29 CV4
NC 12
30 GND
YOUT 11
220
75
10µ
31 CV5
NC 10
32 BIAS
COUT 9
S1
2
3
4
5
6
Vs1
220
220
Chrominance
signal input 1
8
220
2.2µ
75
75
Luminance
signal input 1
220
2.2µ
7
0.47µ
Chrominance
signal output
Vs2
2.2µ
75
Luminance
signal input 2
2.2µ
NC
C1
1
C2
NC
0.01µ
Y1
33µ
75
Chrominance
signal input 2
75
S2
220
Y2
2.2µ
Luminance
signal output
∗1 Input pins of Pins 1, 3, 5, 7, 23, 25, 27, 29 and 31 are biased to approximately 4.2 to 4.7V. Therefore, care
should be taken for the capacitance polarity.
∗2 Output pins of Pins 9, 11, 13, 15 and 17 are biased to approximately 3.8 to 4.8V. Therefore, care should be
taken for the capacitance polarity.
∗3 Set VADR to 0V (GND) when the IC slave address is 90H, or to 9V (VCC) when the IC slave address is 92H.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 19 –
CXA2040Q
Notes on Operation
• Connect the power supply side of the by-pass capacitor between the power supply and GND as close to the
pin as possible.
• Take care not to allow interference signals to enter Pin 32 (BIAS). If interference signals enter Pin 32, the
signal S/N, cross talk and MUTE will deteriorate. Therefore, connect the by-pass capacitor, etc. as close to
the pins as possible.
• For dual surface boards, using one side as a solid earth is best.
• Pins 2, 8, 10, 12, 14, 16, 18, 24 and 28 are NC (not connected) pins. Connect these NC pins to GND. If these
NC pins are not connected to GND, the cross talk and other desired values indicated in the Electrical
Characteristics cannot be obtained.
• Input pins of Pins 1, 3, 5, 7, 23, 25, 27, 29 and 31 are biased to approximately 4.2 to 4.7V. Therefore, care
should be taken for the capacitance polarity.
• Output pins of Pins 9, 11, 13, 15 and 17 are biased to approximately 3.8 to 4.8V. Therefore, care should be
taken for the capacitance polarity.
– 20 –
CXA2040Q
Curve Data
CV1 to 5 inputs —
CVOUT2 frequency response
2
8
0
6
Video I/O gain [dB]
Video I/O gain [dB]
CV1 to 5 inputs —
CVOUT1, 3 frequency response
–2
–4
–6
2
0
–8
–2
0.1
1
10
0.1
10
Frequency [MHz]
Y/C MIX input —
CVOUT1, 3 frequency response
Y/C MIX input —
CVOUT2 frequency response
2
8
0
6
–2
–4
–6
4
2
0
–8
–2
0.1
1
10
0.1
Frequency [MHz]
1
10
Frequency [MHz]
Y input — YOUT frequency response
C input — COUT frequency response
2
2
0
0
Video I/O gain [dB]
Video I/O gain [dB]
1
Frequency [MHz]
Video I/O gain [dB]
Video I/O gain [dB]
4
–2
–4
–6
–2
–4
–6
–8
–8
0.1
1
10
0.1
Frequency [MHz]
1
Frequency [MHz]
– 21 –
10
CXA2040Q
Package Outline
Unit: mm
32PIN QFP (PLASTIC)
9.0 ± 0.2
24
0.1
+ 0.35
1.5 – 0.15
+ 0.3
7.0 – 0.1
17
16
32
9
(8.0)
25
1
+ 0.2
0.1 – 0.1
0.8
+ 0.15
0.3 – 0.1
± 0.12 M
+ 0.1
0.127 – 0.05
0° to 10°
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-32P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP032-P-0707-A
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
0.2g
JEDEC CODE
– 22 –
0.50
8