SN74ALVCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES281 – OCTOBER 1999 D D D D Member of the Texas Instruments Widebus+ Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Packaged in Plastic Fine-Pitch Ball Grid Array Package D D description This 32-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH32244 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as eight 4-bit buffers, four 8-bit buffers, two 16-bit buffers, or one 32-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH32244 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each 4-bit buffer) INPUTS OE A OUTPUT Y L H H L L L H X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus+ are trademarks of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALVCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES281 – OCTOBER 1999 GKE PACKAGE (TOP VIEW) 1 2 3 4 5 terminal assignments 6 1 2 3 4 5 6 A A 1Y2 1Y1 1OE 2OE 1A1 1A2 B B 1Y4 1Y3 GND GND 1A3 1A4 C C 2Y2 2Y1 2A2 D 2Y4 2Y3 VCC GND 2A1 D VCC GND 2A3 2A4 E 3Y2 3Y1 GND GND 3A1 3A2 F 3Y4 3Y3 3A4 4Y2 4Y1 VCC GND 3A3 G VCC GND 4A1 4A2 H 4Y4 4Y3 4OE 3OE 4A3 4A4 E F G H J 5Y2 5Y1 5OE 6OE 5A1 5A2 J K 5Y4 5Y3 GND GND 5A3 5A4 K L 6Y2 6Y1 6A2 M 6Y4 6Y3 VCC GND 6A1 L VCC GND 6A3 6A4 M N 7Y2 7Y1 GND GND 7A1 7A2 N P 7Y4 7Y3 8Y2 8Y1 VCC GND 7A4 R VCC GND 7A3 P 8A1 8A2 R T 8Y3 8Y4 8OE 7OE 8A4 8A3 T 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES281 – OCTOBER 1999 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 5OE 5A1 5A2 5A3 5A4 6OE 6A1 6A2 6A3 6A4 A3 3OE A5 A2 A6 A1 B5 B2 B6 B1 1Y1 3A1 1Y2 3A2 1Y3 3A3 1Y4 3A4 A4 4OE C5 C2 C6 C1 D5 D2 D6 D1 2Y1 4A1 2Y2 4A2 2Y3 4A3 2Y4 4A4 J3 7OE J5 J2 J6 J1 K5 K2 K6 K1 5Y1 7A1 5Y2 7A2 5Y3 7A3 5Y4 7A4 J4 8OE L5 L2 L6 L1 M5 M2 M6 M1 6Y1 8A1 6Y2 8A2 6Y3 8A3 6Y4 8A4 POST OFFICE BOX 655303 H4 E5 E2 E6 E1 F5 F2 F6 F1 3Y1 3Y2 3Y3 3Y4 H3 G5 G2 G6 G1 H6 H1 H5 H2 4Y1 4Y2 4Y3 4Y4 T4 N5 N2 N6 N1 P5 P2 P6 P1 7Y1 7Y2 7Y3 7Y4 T3 R5 R2 R6 R1 T6 T1 T5 T2 • DALLAS, TEXAS 75265 8Y1 8Y2 8Y3 8Y4 3 SN74ALVCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES281 – OCTOBER 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) VCC Supply voltage VIH High-level input voltage Operating Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V MIN MAX 1.65 3.6 1.5 2 0.35 × VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VI VO Input voltage 0 Output voltage 0 IOL ∆t/∆v Low level output current Low-level V 1.7 Low-level input voltage High level output current High-level 0.7 V 0.8 VCC VCC VCC = 1.65 V VCC = 2.3 V –4 VCC = 2.7 V VCC = 3 V –12 –8 V V mA –24 VCC = 1.65 V VCC = 2.3 V 4 VCC = 2.7 V VCC = 3 V 12 Input transition rise or fall rate V 0.65 × VCC VIL IOH UNIT 8 mA 24 10 ns/V TA Operating free-air temperature –40 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES281 – OCTOBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA IOH = –8 mA VOH 12 mA IOH = –12 IOH = –24 mA IOL = 100 µA VOL II II(hold) ( ) 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2.2 MAX 0.2 0.45 2.3 V 0.7 IOL = 12 mA IOL = 24 mA 2.7 V 0.4 3V 0.55 VI = VCC or GND VI = 0.58 V 3.6 V ±5 1.65 V 25 VI = 1.07 V VI = 0.7 V 1.65 V –25 2.3 V 45 VI = 1.7 V VI = 0.8 V 2.3 V –45 3V 75 3V –75 ∆ICC One input at VCC – 0.6 V, IO = 0 Other inputs at VCC or GND V µA µA 3.6 V ±500 3.6 V ±10 µA 40 µA 750 µA 3.6 V 3 V to 3.6 V VI = VCC or GND UNIT V 1.65 V VO = VCC or GND VI = VCC or GND, Data inputs 1.65 V VCC–0.2 1.2 1.65 V to 3.6 V IOZ ICC Ci TYP† IOL = 4 mA IOL = 8 mA VI = 2 V VI = 0 to 3.6 V‡ Control inputs MIN 3 33V 3.3 pF 6 Co Outputs VO = VCC or GND 3.3 V 7 pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) TO (OUTPUT) tpd A ten OE PARAMETER VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V MAX § MIN MAX Y MIN § 1 Y § § § § tdis Y OE § This information was not available at the time of publication. VCC = 2.7 V MIN VCC = 3.3 V ± 0.3 V UNIT MAX MIN MAX 3.7 3.6 1 3 ns 1 5.7 5.4 1 4.4 ns 1 5.2 4.6 1 4.1 ns operating characteristics, TA = 25°C PARAMETER Cpd d Power dissipation capacitance TEST CONDITIONS Outputs enabled Outputs disabled 0 CL = 0, VCC = 1.8 V TYP § f = 10 MHz § VCC = 2.5 V TYP VCC = 3.3 V TYP 16 19 4 5 UNIT pF § This information was not available at the time of publication. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ALVCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES281 – OCTOBER 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.15 V 2 × VCC S1 1 kΩ From Output Under Test Open GND CL = 30 pF (see Note A) 1 kΩ TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC Input VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES281 – OCTOBER 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC Input VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74ALVCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES281 – OCTOBER 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 500 Ω From Output Under Test 6V Open S1 GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 1.5 V Input 0V 1.5 V VOLTAGE WAVEFORMS PULSE DURATION 0V tsu th 2.7 V Data Input 1.5 V 1.5 V 0V Output Control (low-level enabling) VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 0V tPLH 1.5 V 1.5 V 0V tPLZ 1.5 V Output Waveform 1 S1 at 6 V (see Note B) 3V 1.5 V VOL + 0.3 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Output Waveform 2 S1 at GND (see Note B) VOL tPHZ tPZH tPHL VOH Output 2.7 V tPZL 2.7 V Input 1.5 V 2.7 V Timing Input 1.5 V VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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