TI SN74ALVCH16344DL

SN74ALVCH16344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES054F – SEPTEMBER 1995 – REVISED FEBRUARY 1999
D
D
D
D
D
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus  Family
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
OE1
1B1
1B2
GND
1B3
1B4
VCC
1A
2B1
2B2
GND
2B3
2B4
2A
3A
3B1
3B2
GND
3B3
3B4
4A
VCC
4B1
4B2
GND
4B3
4B4
OE2
description
This 1-bit to 4-bit address driver is designed for
1.65-V to 3.6-V VCC operation.
The SN74ALVCH16344 is used in applications in
which four separate memory locations must be
addressed by a single address.
To ensure the high-impedance state during power
up or power down, OE should be tied to VCC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold
unused or floating inputs at a valid logic level.
The SN74ALVCH16344 is characterized for
operation from –40°C to 85°C.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
OE4
8B1
8B2
GND
8B3
8B4
VCC
8A
7B1
7B2
GND
7B3
7B4
7A
6A
6B1
6B2
GND
6B3
6B4
5A
VCC
5B1
5B2
GND
5B3
5B4
OE3
FUNCTION TABLE
INPUTS
OE
A
OUTPUT
Bn
L
H
H
L
L
L
H
H
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ALVCH16344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES054F – SEPTEMBER 1995 – REVISED FEBRUARY 1999
logic diagram (positive logic)
OE4
56
29
OE3
OE2
OE1
28
1
2
3
1A
34
1B1
5B1
33
1B2
8
5A
5
6
9
31
5B3
1B3
30
1B4
41
2B1
10
2A
6A
12
13
16
17
6B1
6B2
42
38
2B3
37
2B4
48
3B1
47
3B2
15
6B3
6B4
7B1
7B2
43
3A
7A
19
20
23
24
21
45
3B3
44
3B4
55
4B1
54
4B2
4A
49
7B3
7B4
8B1
8B2
8A
26
27
2
5B4
40
2B2
14
5B2
36
52
4B3
51
4B4
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• DALLAS, TEXAS 75265
8B3
8B4
SN74ALVCH16344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES054F – SEPTEMBER 1995 – REVISED FEBRUARY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
High-level input voltage
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VIL
VI
VO
IOH
Low-level input voltage
MIN
MAX
1.65
3.6
2
0.35 × VCC
0.7
0
0
IOL
Low level output current
Low-level
∆t/∆v
Input transition rise or fall rate
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
V
0.8
Output voltage
VCC = 2.7 V
VCC = 3 V
V
1.7
Input voltage
High level output current
High-level
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V
VCC = 2.3 V
UNIT
VCC
VCC
V
V
–4
–12
–12
mA
–24
4
12
12
mA
24
10
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74ALVCH16344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES054F – SEPTEMBER 1995 – REVISED FEBRUARY 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
IOH = –100 µA
IOH = –4 mA
1.65 V
IOH = –6 mA
VOH
IOH = –12 mA
IOH = –24 mA
IOL = 100 µA
IOZ
ICC
∆ICC
Ci
Data inputs
2
2.3 V
1.7
UNIT
2.7 V
2.2
3V
2.4
3V
2
V
0.2
2.3 V
0.4
2.3 V
0.7
2.7 V
0.4
3V
0.55
±5
3.6 V
VI = 0.58 V
VI = 1.07 V
1.65 V
25
1.65 V
–25
VI = 0.7 V
VI = 1.7 V
2.3 V
45
2.3 V
–45
VI = 0.8 V
VI = 2 V
3V
75
3V
–75
V
µA
µA
VI = 0 to 3.6 V‡
3.6 V
±500
VO = VCC or GND
VI = VCC or GND,
3.6 V
±10
µA
3.6 V
40
µA
750
µA
IO = 0
Other inputs at VCC or GND
One input at VCC – 0.6 V,
Control inputs
2.3 V
0.45
IOL = 24 mA
VI = VCC or GND
II(hold)
(
)
MAX
VCC–0.2
1.2
1.65 V
IOL = 12 mA
II
TYP†
1.65 V to 3.6 V
IOL = 4 mA
IOL = 6 mA
VOL
MIN
3 V to 3.6 V
VI = VCC or GND
2.5
33V
3.3
pF
3.5
Co
Outputs
VO = VCC or GND
3.3 V
4
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
VCC = 1.8 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
B
TYP
§
1
ten
OE
B
§
tdis
OE
B
§
POST OFFICE BOX 655303
UNIT
MIN
MAX
4.6
4.6
1.4
4
ns
1
6.2
6.2
1.2
5.1
ns
1
5.1
4.4
1.2
4
ns
0.35
ns
0.5
ns
§ This information was not available at the time of publication.
¶ Skew between outputs of same bank and same package (same transition).
# Skew between outputs of all banks and same package (A1 through A8 tied together).
• DALLAS, TEXAS 75265
MIN
VCC = 3.3 V
± 0.3 V
MAX
tsk(o)¶
tsk(o)#
4
VCC = 2.7 V
SN74ALVCH16344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES054F – SEPTEMBER 1995 – REVISED FEBRUARY 1999
operating characteristics, TA = 25°C
PARAMETER
Outputs enabled
Power dissipation
capacitance
Cpd
d
VCC = 1.8 V
TYP
†
TEST CONDITIONS
CL = 50 pF,
pF
Outputs disabled
f = 10 MHz
VCC = 2.5 V
TYP
†
VCC = 3.3 V
TYP
68
84
11
14
UNIT
pF
† This information was not available at the time of publication.
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN74ALVCH16344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES054F – SEPTEMBER 1995 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ALVCH16344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES054F – SEPTEMBER 1995 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
GND
CL = 50 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
Open
500 Ω
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
1.5 V
Input
1.5 V
0V
1.5 V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
Output
Control
(low-level
enabling)
1.5 V
0V
tPLZ
tPZL
2.7 V
Input
1.5 V
1.5 V
0V
tPLH
1.5 V
3V
1.5 V
tPZH
VOH
Output
Output
Waveform 1
S1 at 6 V
(see Note B)
tPHL
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
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Copyright  1999, Texas Instruments Incorporated