Data Sheet Programmable Low Voltage 1:10 LVDS Clock Driver ADN4670 FEATURES Low output skew <30 ps (typical) Distributes one differential clock input to 10 LVDS clock outputs Programmable—one of two differential clock inputs can be selected (CLK0, CLK1) and individual differential clock outputs enabled/disabled Signaling rate up to 1.1 GHz (typical) 2.375 V to 2.625 V power supply range ±100 mV differential input threshold Input common-mode range from rail-to-rail I/O pins fail-safe during power-down: VDD = 0 V Available in 32-lead LFCSP and LQFP packages Industrial operating temperature range: −40°C to +85°C FUNCTIONAL BLOCK DIAGRAM CK SI 11-BIT SHIFT REGISTER EN 11-BIT CONTROL REGISTER 9876543210 10 MUX 1 12-BIT COUNTER Q9 Q9 0 CLK0 CLK0 0 CLK1 CLK1 1 Q8 Q8 Q7 Q7 MUX Q6 Q6 APPLICATIONS Q5 Q5 Clock distribution networks Q4 Q4 Q3 Q3 Q2 Q2 Q0 Q0 08870-001 Q1 Q1 Figure 1. GENERAL DESCRIPTION The ADN4670 is a low voltage differential signaling (LVDS) clock driver that expands a differential clock input signal to 10 differential clock outputs. The device is programmable using a simple serial interface, so that one of two clock inputs can be selected (CLK0/CLK0 or CLK1/CLK1) and any of the differential outputs (Q0/Q0 to Q9/Q9) can be enabled or disabled (tristated). The ADN4670 is designed for use in 50 Ω transmission line environments. first 10 bits determine which outputs are enabled (0 = disabled, 1 = enabled), while the 11th bit selects the clock input (0 = CLK0, 1 = CLK1). A 12th clock pulse transfers data from the shift register to the control register. The ADN4670 is fully specified over the industrial temperature range and is available in a 32-lead LFCSP and LQFP packages. When the enable input EN is high, the device may be programmed by clocking 11 data bits into the shift register. The Rev. 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ADN4670 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................6 Applications ....................................................................................... 1 ESD Caution...................................................................................6 Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions..............................7 General Description ......................................................................... 1 Theory of Operation .........................................................................8 Revision History ............................................................................... 2 LVDS Reciever Input Termination .............................................8 Specifications..................................................................................... 3 Fail-Safe Operation .......................................................................8 Jitter Characteristics ..................................................................... 3 Programming .................................................................................8 LVDS Switching Characteristics ................................................. 4 Outline Dimensions ..........................................................................9 Programming Logic AC Characteristics ................................... 5 Ordering Guide .............................................................................9 REVISION HISTORY 1/12—Rev. 0 to Rev. A Added LQFP Package.................................................... Throughout Updated Outline Dimensions ......................................................... 9 Changes to Ordering Guide ............................................................ 9 4/10—Revision 0: Initial Version Rev. A | Page 2 of 12 Data Sheet ADN4670 SPECIFICATIONS VDD = 2.375 V to 2.625 V; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter RECEIVER Input High Threshold at CLK0/CLK0 or CLK1/CLK1 Input Low Threshold at CLK0/CLK0 or CLK1/CLK1 Symbol Min VTH VTL −100 Typ Differential Input Voltage Input Common-Mode Voltage Input Current at CLK0, CLK0, CLK1, or CLK1 Input Capacitance DRIVER Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Output Short Circuit Current |VID| VIC IIH, IIL CI 200 0.5|VID| −5 |VOD| ΔVOD VOS ΔVOS IOS 250 450 0.95 1.2 Reference Output Voltage Output Capacitance SUPPLY CURRENT Supply Current VBB CO 1.15 Max Unit 100 mV mV Conditions/Comments mV VDD − 0.5|VID| +5 μA pF VI = VDD or VI = 0 V VI = VDD or GND 600 50 1.45 350 −20 20 1.35 mV mV V mV mA mA V pF RL = 100 Ω 100 35 110 mA mA 150 160 mA 3 1.25 3 IDD −40°C to +85°C VO = 0 V |VOD| = 0 V VDD = 2.5 V, I = −100 µA VO = VDD or GND All outputs tristated, f = 0 Hz All outputs enabled and loaded, RL = 100 Ω, f = 100 MHz All outputs enabled and loaded, RL = 100 Ω, f = 800 MHz JITTER CHARACTERISTICS Table 2. Parameter Symbol Additive Phase Jitter from Input to LVDS Outputs, Q3 and Q3 tJITTER LVDS Min Rev. A | Page 3 of 12 Typ 281 111 Max Unit Conditions/Comments fS rms fS rms 12 kHz to 5 MHz, fOUT = 30.72 MHz 12 kHz to 20 MHz, fOUT = 125 MHz ADN4670 Data Sheet LVDS SWITCHING CHARACTERISTICS VDD = 2.375 V to 2.625 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Symbol Propagation Delay Low to High Propagation Delay High to Low Duty Cycle Output Skew2 Pulse Skew3 Part-to-Part Output Skew4 Output Rise Time Output Fall Time Maximum Input Frequency tPLHx tPHLx tDUTY tSK(O) tSK(P) tSK(PP) tr tf fCLK Min Typ Max1 Unit Conditions/Comments 2 2 3 3 55 ns ns % ps ps ps ps From CLK0/CLK0 or CLK1/ CLK1 to any Qx/Qx From CLK0/CLK0 or CLK1/ CLK1 to any Qx/Qx From CLK0/CLK0 or CLK1/ CLK1 to any Qx/Qx Any Qx/Qx Any Qx/Qx Any Qx/Qx Any Qx/Qx, 20% to 80%, RL = 100 Ω CL = 5 pF Any Qx/Qx, 80% to 20%, RL = 100 Ω CL = 5 pF From CLK0/CLK0 or CLK1/ CLK1 to any Qx/Qx 45 30 50 600 350 350 900 1100 MHz 1 Guaranteed by design and characterization. Output skew is defined as the difference between the largest and smallest values of TPLHx within a device or the difference between the largest and smallest values of TPHLx within a device, whichever of the two is greater. 3 Pulse skew is defined as the magnitude of the maximum difference between tPLH and tPHL for any channel of a device, that is, |tPHLx – tHLPx|. 4 Part-to-part output skew is defined as the difference between the largest and smallest values of TPLHx across multiple devices or the difference between the largest and smallest values of TPHLx across multiple devices, whichever of the two is greater. 2 CLK CLK Q0 Q0 tPLH0 tPHL0 Q1 Q1 tPLH1 tPHL1 Q9 tPLH9 tPHL9 Figure 2. Waveforms for Calculation of tSK(O) and tSK(PP) Rev. A | Page 4 of 12 08870-002 Q9 Data Sheet ADN4670 DIFFERENTIAL OUTPUT SIGNAL VOD = (Qx) – (Qx) 80% 250mV 5% 0V DIFFERENTIAL 5% 250mV t/2 08870-003 20% t/2 Figure 3. Test Criteria for fCLK, tr, tf, and VOD PROGRAMMING LOGIC AC CHARACTERISTICS VDD = 2.375 V to 2.625 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter Maximum Frequency at CK Input Setup Time, SI to CK Hold Time, CK to SI EN to CK Removal Time Start-Up Time Minimum Clock Pulse Width Logic Input High Level Logic Input Low Level High Level Logic Input Current, CK High Level Logic Input Current, SI and EN Low Level Logic Input Current, CK Low Level Logic Input Current, SI and EN Symbol fMAX tSU tH tREMOVAL tSTARTUP tW VIH VIL IIH IIL Min 100 Typ 150 Max 2 1.5 1.5 1 3 2 −5 +10 −10 −5 0.8 +5 −30 +30 +5 Unit MHz ns ns ns µs ns V V µA µA µA µA Rev. A | Page 5 of 12 Conditions/Comments Time for which SI must not change before the CK 0-to-1 transition Time for which SI must not change after the CK 0-to-1 transition Removal time, EN to CK Start-up time after disable through SI VDD = 2.5 V VDD = 2.5 V VI = VDD VI = VDD VI = GND VI = GND ADN4670 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VCC to GND Input Voltage to GND Output Voltage to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) Power Dissipation LFCSP Package θJA Thermal Impedance LQFP Package θJA Thermal Impedance Reflow Soldering Peak Temperature Pb-Free ESD (Human Body Model, 1.5 kΩ 100 pF) Rating −0.3 V to +2.8 V −0.2 V to ( VDD + 0.2) V −0.2 V to ( VDD + 0.2) V −40°C to +85°C −65°C to +150°C 150°C (TJ max − TA)/θJA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 32.5°C/W 59°C/W 260°C ± 5°C 4000 V Rev. A | Page 6 of 12 Data Sheet ADN4670 32 31 30 29 28 27 26 25 VDD Q0 Q0 Q1 Q1 Q2 Q2 VSS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADN4670 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 VSS Q9 Q9 Q8 Q8 Q7 Q7 VDD Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 08870-004 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CK SI CLK0 CLK0 VBB CLK1 CLK1 EN NOTES 1. THE EXPOSED PAD CAN BE CONNECTED TO GROUND OR LEFT FLOATING. Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic CK 2 SI 3 4 5 6 7 8 CLK0 CLK0 VBB CLK1 CLK1 EN 9, 25 10, 12, 14, 17, 19, 21, 23, 26, 28, 30 VSS Q9 to Q0 11, 13, 15, 18, 20, 22, 24, 27, 29, 31 Q9 to Q0 16, 32 VDD Description Programming Clock. Programming data is clocked in on a low-to-high transition at this input. If left open-circuit, it is pulled high by a 120 kΩ resistor. Serial Data Input. This is the input for programming data. If left open-circuit, it is pulled low by a 120 kΩ resistor. Noninverting Differential Clock Input 0. Inverting Differential Clock Input 0. Reference Voltage Output. Noninverting Differential Clock Input 1. Inverting Differential Clock Input 1. Active-High Enable Input. When this input is high, programming is enabled. If left open-circuit, it is pulled low by a 120 kΩ resistor. Device Ground. Inverted Clock Output. When the differential input voltage is between CLKx and CLKx > 100 mV, this output sinks current. When the differential input voltage is between CLKx and CLKx < −100 mV, this output sources current. Noninverted Clock Output. When the differential input voltage is between CLKx and CLKx > 100 mV, this output sources current. When the differential input voltage is between CLKx and CLKx < −100 mV, this output sinks current. Power Supply Input. This part can be operated from 2.375 V to 2.625 V. Rev. A | Page 7 of 12 ADN4670 Data Sheet THEORY OF OPERATION PROGRAMMING The ADN4670 is a clock driver/expander for low voltage differential signaling (LVDS). It takes a differential clock signal of typically 350 mV and expands it to 10 differential clock outputs with very low skew (typically < 30 ps). The device receives a differential current signal from a source such as a twisted pair cable, which develops a voltage of typically ±350 mV across a 100 Ω terminating resistor. This signal passes via a differential multiplexer to 10 drivers that each output a differential current signal. Three control inputs are provided for programming the ADN4670. EN is the enable input, which allows programming when high, SI is the serial data input, and CK is the serial clock input, which clocks data into the device on a low-to-high clock transition. Each of these inputs has an internal pull-up or pull-down resistor of 120 kΩ. EN and SI are pulled low if left open-circuit while CK is pulled high. The default condition if these inputs are left open-circuit is that all outputs are enabled, and the state of SI selects the inputs (0 = CLK0/CLK0 , 1 = CLK1/CLK1). This is the standard operating mode for which no programming of the device is required. The device is programmable using a simple serial interface. One of two differential clock inputs (CLK0/CLK0 or CLK1/ CLK1), can be selected and any of the differential outputs (Q0/Q0 to Q9/Q9) can be enabled or disabled. Programming is enabled by taking EN high. The data on SI is then clocked into the device on each 0-to-1 transition of CK. Data on SI must be stable for the setup time (tSU) before the clock transition and remain stable for the hold time (tH) after the clock transition. To program the device, 11 bits of data are needed, starting with Bit 0, which enables or disables outputs Q9/Q9, through to Bit 10, which selects either CLK0/CLK0 or CLK1/CLK1 as the inputs. A 12th clock pulse is then required to transfer data from the shift register to the control register. LVDS RECIEVER INPUT TERMINATION Terminate the clock inputs with 100 Ω resistors from CLK0 to CLK0 and CLK1 to /CLK1, placed as close as possible to the input pins. FAIL-SAFE OPERATION In power-down mode (VDD = 0 V), the ADN4670 has fail-safe input and output pins. In power-on mode, fail-safe biasing can be achieved by connecting 10 kΩ pull-up resistors from CLK0 and CLK1 to VDD and 10 kΩ pull-down resistors from CLK0 and CLK1 to GND. A low-to-high transition on EN resets the control register and the next 12 CK pulses are programmed. Table 5. Control Logic Truth Table CK L L L L L L EN L L L L L L SI L L L H H H CLK0 L H Open X X X CLK0 CLK1 X X X L H Open H L Open X X X CLK1 Q0 to Q9 L H L L H L X X X H L Open Q0 to Q9 H L H H L H Table 6. State Machine Inputs EN L L H H L SI L H L H X CK X X ↑ ↑ X Output Default state with all outputs enabled, CLK0 selected, and the control register disabled All outputs enabled, CLK1 selected, and the control register disabled First stage stores low, other stage stores data of previous stage First stage stores high, other stage stores data of previous stage Reset the state machine, control register, and shift register Table 7. Serial Input Sequence Bit 10 CLK_SEL Bit 9 Q0 Bit 8 Q1 Bit 7 Q2 Bit 6 Q3 Bit 5 Q4 Bit 4 Q5 Table 8. Control Register Bit 10 L H X Bit[9:0] H H L Qx[9:0] CLK0 CLK1 Outputs disabled Rev. A | Page 8 of 12 Bit 3 Q6 Bit 2 Q7 Bit 1 Q8 Bit 0 Q9 Data Sheet ADN4670 OUTLINE DIMENSIONS 5.10 5.00 SQ 4.90 1 24 0.50 BSC 8 17 TOP VIEW 0.80 0.75 0.70 16 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.25 3.10 SQ 2.95 EXPOSED PAD 0.50 0.40 0.30 PIN 1 INDICATOR 32 25 112408-A PIN 1 INDICATOR 0.30 0.25 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. Figure 5. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-7) Dimensions shown in millimeters 0.75 0.60 0.45 1.60 MAX 9.00 BSC SQ 32 25 1 24 PIN 1 7.00 BSC SQ TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 SEATING PLANE VIEW A 0.20 0.09 7° 3.5° 0° 0.10 MAX COPLANARITY 8 17 9 0.80 BSC LEAD PITCH VIEW A 16 0.45 0.37 0.30 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBA Figure 6. 32-Lead Low Profile Quad Flat Package [LQFP] (ST-32-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADN4670BCPZ ADN4670BCPZ-REEL7 ADN4670BSTZ ADN4670BSTZ-REEL7 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Low Profile Quad Flat Package [LQFP] 32-Lead Low Profile Quad Flat Package [LQFP] Z = RoHS Compliant Part. Rev. A | Page 9 of 12 Package Option CP-32-7 CP-32-7 ST-32-2 ST-32-2 ADN4670 Data Sheet NOTES Rev. A | Page 10 of 12 Data Sheet ADN4670 NOTES Rev. A | Page 11 of 12 ADN4670 Data Sheet NOTES ©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08870-0-1/12(A) Rev. A | Page 12 of 12